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0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Texas Instruments TSC2046 SPI ADC driver
0004  *
0005  * Copyright (c) 2021 Oleksij Rempel <kernel@pengutronix.de>, Pengutronix
0006  */
0007 
0008 #include <linux/bitfield.h>
0009 #include <linux/delay.h>
0010 #include <linux/module.h>
0011 #include <linux/spi/spi.h>
0012 
0013 #include <asm/unaligned.h>
0014 
0015 #include <linux/iio/buffer.h>
0016 #include <linux/iio/trigger_consumer.h>
0017 #include <linux/iio/triggered_buffer.h>
0018 #include <linux/iio/trigger.h>
0019 
0020 /*
0021  * The PENIRQ of TSC2046 controller is implemented as level shifter attached to
0022  * the X+ line. If voltage of the X+ line reaches a specific level the IRQ will
0023  * be activated or deactivated.
0024  * To make this kind of IRQ reusable as trigger following additions were
0025  * implemented:
0026  * - rate limiting:
0027  *   For typical touchscreen use case, we need to trigger about each 10ms.
0028  * - hrtimer:
0029  *   Continue triggering at least once after the IRQ was deactivated. Then
0030  *   deactivate this trigger to stop sampling in order to reduce power
0031  *   consumption.
0032  */
0033 
0034 #define TI_TSC2046_NAME             "tsc2046"
0035 
0036 /* This driver doesn't aim at the peak continuous sample rate */
0037 #define TI_TSC2046_MAX_SAMPLE_RATE      125000
0038 #define TI_TSC2046_SAMPLE_BITS \
0039     BITS_PER_TYPE(struct tsc2046_adc_atom)
0040 #define TI_TSC2046_MAX_CLK_FREQ \
0041     (TI_TSC2046_MAX_SAMPLE_RATE * TI_TSC2046_SAMPLE_BITS)
0042 
0043 #define TI_TSC2046_SAMPLE_INTERVAL_US       10000
0044 
0045 #define TI_TSC2046_START            BIT(7)
0046 #define TI_TSC2046_ADDR             GENMASK(6, 4)
0047 #define TI_TSC2046_ADDR_TEMP1           7
0048 #define TI_TSC2046_ADDR_AUX         6
0049 #define TI_TSC2046_ADDR_X           5
0050 #define TI_TSC2046_ADDR_Z2          4
0051 #define TI_TSC2046_ADDR_Z1          3
0052 #define TI_TSC2046_ADDR_VBAT            2
0053 #define TI_TSC2046_ADDR_Y           1
0054 #define TI_TSC2046_ADDR_TEMP0           0
0055 
0056 /*
0057  * The mode bit sets the resolution of the ADC. With this bit low, the next
0058  * conversion has 12-bit resolution, whereas with this bit high, the next
0059  * conversion has 8-bit resolution. This driver is optimized for 12-bit mode.
0060  * So, for this driver, this bit should stay zero.
0061  */
0062 #define TI_TSC2046_8BIT_MODE            BIT(3)
0063 
0064 /*
0065  * SER/DFR - The SER/DFR bit controls the reference mode, either single-ended
0066  * (high) or differential (low).
0067  */
0068 #define TI_TSC2046_SER              BIT(2)
0069 
0070 /*
0071  * If VREF_ON and ADC_ON are both zero, then the chip operates in
0072  * auto-wake/suspend mode. In most case this bits should stay zero.
0073  */
0074 #define TI_TSC2046_PD1_VREF_ON          BIT(1)
0075 #define TI_TSC2046_PD0_ADC_ON           BIT(0)
0076 
0077 /*
0078  * All supported devices can do 8 or 12bit resolution. This driver
0079  * supports only 12bit mode, here we have a 16bit data transfer, where
0080  * the MSB and the 3 LSB are 0.
0081  */
0082 #define TI_TSC2046_DATA_12BIT           GENMASK(14, 3)
0083 
0084 #define TI_TSC2046_MAX_CHAN         8
0085 #define TI_TSC2046_MIN_POLL_CNT         3
0086 #define TI_TSC2046_EXT_POLL_CNT         3
0087 #define TI_TSC2046_POLL_CNT \
0088     (TI_TSC2046_MIN_POLL_CNT + TI_TSC2046_EXT_POLL_CNT)
0089 #define TI_TSC2046_INT_VREF         2500
0090 
0091 /* Represents a HW sample */
0092 struct tsc2046_adc_atom {
0093     /*
0094      * Command transmitted to the controller. This field is empty on the RX
0095      * buffer.
0096      */
0097     u8 cmd;
0098     /*
0099      * Data received from the controller. This field is empty for the TX
0100      * buffer
0101      */
0102     __be16 data;
0103 } __packed;
0104 
0105 /* Layout of atomic buffers within big buffer */
0106 struct tsc2046_adc_group_layout {
0107     /* Group offset within the SPI RX buffer */
0108     unsigned int offset;
0109     /*
0110      * Amount of tsc2046_adc_atom structs within the same command gathered
0111      * within same group.
0112      */
0113     unsigned int count;
0114     /*
0115      * Settling samples (tsc2046_adc_atom structs) which should be skipped
0116      * before good samples will start.
0117      */
0118     unsigned int skip;
0119 };
0120 
0121 struct tsc2046_adc_dcfg {
0122     const struct iio_chan_spec *channels;
0123     unsigned int num_channels;
0124 };
0125 
0126 struct tsc2046_adc_ch_cfg {
0127     unsigned int settling_time_us;
0128     unsigned int oversampling_ratio;
0129 };
0130 
0131 enum tsc2046_state {
0132     TSC2046_STATE_SHUTDOWN,
0133     TSC2046_STATE_STANDBY,
0134     TSC2046_STATE_POLL,
0135     TSC2046_STATE_POLL_IRQ_DISABLE,
0136     TSC2046_STATE_ENABLE_IRQ,
0137 };
0138 
0139 struct tsc2046_adc_priv {
0140     struct spi_device *spi;
0141     const struct tsc2046_adc_dcfg *dcfg;
0142 
0143     struct iio_trigger *trig;
0144     struct hrtimer trig_timer;
0145     enum tsc2046_state state;
0146     int poll_cnt;
0147     spinlock_t state_lock;
0148 
0149     struct spi_transfer xfer;
0150     struct spi_message msg;
0151 
0152     struct {
0153         /* Scan data for each channel */
0154         u16 data[TI_TSC2046_MAX_CHAN];
0155         /* Timestamp */
0156         s64 ts __aligned(8);
0157     } scan_buf;
0158 
0159     /*
0160      * Lock to protect the layout and the SPI transfer buffer.
0161      * tsc2046_adc_group_layout can be changed within update_scan_mode(),
0162      * in this case the l[] and tx/rx buffer will be out of sync to each
0163      * other.
0164      */
0165     struct mutex slock;
0166     struct tsc2046_adc_group_layout l[TI_TSC2046_MAX_CHAN];
0167     struct tsc2046_adc_atom *rx;
0168     struct tsc2046_adc_atom *tx;
0169 
0170     unsigned int count;
0171     unsigned int groups;
0172     u32 effective_speed_hz;
0173     u32 scan_interval_us;
0174     u32 time_per_scan_us;
0175     u32 time_per_bit_ns;
0176 
0177     struct tsc2046_adc_ch_cfg ch_cfg[TI_TSC2046_MAX_CHAN];
0178 };
0179 
0180 #define TI_TSC2046_V_CHAN(index, bits, name)            \
0181 {                               \
0182     .type = IIO_VOLTAGE,                    \
0183     .indexed = 1,                       \
0184     .channel = index,                   \
0185     .info_mask_separate = BIT(IIO_CHAN_INFO_RAW),       \
0186     .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),   \
0187     .datasheet_name = "#name",              \
0188     .scan_index = index,                    \
0189     .scan_type = {                      \
0190         .sign = 'u',                    \
0191         .realbits = bits,               \
0192         .storagebits = 16,              \
0193         .endianness = IIO_CPU,              \
0194     },                          \
0195 }
0196 
0197 #define DECLARE_TI_TSC2046_8_CHANNELS(name, bits) \
0198 const struct iio_chan_spec name ## _channels[] = { \
0199     TI_TSC2046_V_CHAN(0, bits, TEMP0), \
0200     TI_TSC2046_V_CHAN(1, bits, Y), \
0201     TI_TSC2046_V_CHAN(2, bits, VBAT), \
0202     TI_TSC2046_V_CHAN(3, bits, Z1), \
0203     TI_TSC2046_V_CHAN(4, bits, Z2), \
0204     TI_TSC2046_V_CHAN(5, bits, X), \
0205     TI_TSC2046_V_CHAN(6, bits, AUX), \
0206     TI_TSC2046_V_CHAN(7, bits, TEMP1), \
0207     IIO_CHAN_SOFT_TIMESTAMP(8), \
0208 }
0209 
0210 static DECLARE_TI_TSC2046_8_CHANNELS(tsc2046_adc, 12);
0211 
0212 static const struct tsc2046_adc_dcfg tsc2046_adc_dcfg_tsc2046e = {
0213     .channels = tsc2046_adc_channels,
0214     .num_channels = ARRAY_SIZE(tsc2046_adc_channels),
0215 };
0216 
0217 /*
0218  * Convert time to a number of samples which can be transferred within this
0219  * time.
0220  */
0221 static unsigned int tsc2046_adc_time_to_count(struct tsc2046_adc_priv *priv,
0222                           unsigned long time)
0223 {
0224     unsigned int bit_count, sample_count;
0225 
0226     bit_count = DIV_ROUND_UP(time * NSEC_PER_USEC, priv->time_per_bit_ns);
0227     sample_count = DIV_ROUND_UP(bit_count, TI_TSC2046_SAMPLE_BITS);
0228 
0229     dev_dbg(&priv->spi->dev, "Effective speed %u, time per bit: %u, count bits: %u, count samples: %u\n",
0230         priv->effective_speed_hz, priv->time_per_bit_ns,
0231         bit_count, sample_count);
0232 
0233     return sample_count;
0234 }
0235 
0236 static u8 tsc2046_adc_get_cmd(struct tsc2046_adc_priv *priv, int ch_idx,
0237                   bool keep_power)
0238 {
0239     u32 pd;
0240 
0241     /*
0242      * if PD bits are 0, controller will automatically disable ADC, VREF and
0243      * enable IRQ.
0244      */
0245     if (keep_power)
0246         pd = TI_TSC2046_PD0_ADC_ON;
0247     else
0248         pd = 0;
0249 
0250     switch (ch_idx) {
0251     case TI_TSC2046_ADDR_TEMP1:
0252     case TI_TSC2046_ADDR_AUX:
0253     case TI_TSC2046_ADDR_VBAT:
0254     case TI_TSC2046_ADDR_TEMP0:
0255         pd |= TI_TSC2046_SER | TI_TSC2046_PD1_VREF_ON;
0256     }
0257 
0258     return TI_TSC2046_START | FIELD_PREP(TI_TSC2046_ADDR, ch_idx) | pd;
0259 }
0260 
0261 static u16 tsc2046_adc_get_value(struct tsc2046_adc_atom *buf)
0262 {
0263     return FIELD_GET(TI_TSC2046_DATA_12BIT, get_unaligned_be16(&buf->data));
0264 }
0265 
0266 static int tsc2046_adc_read_one(struct tsc2046_adc_priv *priv, int ch_idx,
0267                 u32 *effective_speed_hz)
0268 {
0269     struct tsc2046_adc_ch_cfg *ch = &priv->ch_cfg[ch_idx];
0270     struct tsc2046_adc_atom *rx_buf, *tx_buf;
0271     unsigned int val, val_normalized = 0;
0272     int ret, i, count_skip = 0, max_count;
0273     struct spi_transfer xfer;
0274     struct spi_message msg;
0275     u8 cmd;
0276 
0277     if (!effective_speed_hz) {
0278         count_skip = tsc2046_adc_time_to_count(priv, ch->settling_time_us);
0279         max_count = count_skip + ch->oversampling_ratio;
0280     } else {
0281         max_count = 1;
0282     }
0283 
0284     if (sizeof(*tx_buf) * max_count > PAGE_SIZE)
0285         return -ENOSPC;
0286 
0287     tx_buf = kcalloc(max_count, sizeof(*tx_buf), GFP_KERNEL);
0288     if (!tx_buf)
0289         return -ENOMEM;
0290 
0291     rx_buf = kcalloc(max_count, sizeof(*rx_buf), GFP_KERNEL);
0292     if (!rx_buf) {
0293         ret = -ENOMEM;
0294         goto free_tx;
0295     }
0296 
0297     /*
0298      * Do not enable automatic power down on working samples. Otherwise the
0299      * plates will never be completely charged.
0300      */
0301     cmd = tsc2046_adc_get_cmd(priv, ch_idx, true);
0302 
0303     for (i = 0; i < max_count - 1; i++)
0304         tx_buf[i].cmd = cmd;
0305 
0306     /* automatically power down on last sample */
0307     tx_buf[i].cmd = tsc2046_adc_get_cmd(priv, ch_idx, false);
0308 
0309     memset(&xfer, 0, sizeof(xfer));
0310     xfer.tx_buf = tx_buf;
0311     xfer.rx_buf = rx_buf;
0312     xfer.len = sizeof(*tx_buf) * max_count;
0313     spi_message_init_with_transfers(&msg, &xfer, 1);
0314 
0315     /*
0316      * We aren't using spi_write_then_read() because we need to be able
0317      * to get hold of the effective_speed_hz from the xfer
0318      */
0319     ret = spi_sync(priv->spi, &msg);
0320     if (ret) {
0321         dev_err_ratelimited(&priv->spi->dev, "SPI transfer failed %pe\n",
0322                     ERR_PTR(ret));
0323         goto free_bufs;
0324     }
0325 
0326     if (effective_speed_hz)
0327         *effective_speed_hz = xfer.effective_speed_hz;
0328 
0329     for (i = 0; i < max_count - count_skip; i++) {
0330         val = tsc2046_adc_get_value(&rx_buf[count_skip + i]);
0331         val_normalized += val;
0332     }
0333 
0334     ret = DIV_ROUND_UP(val_normalized, max_count - count_skip);
0335 
0336 free_bufs:
0337     kfree(rx_buf);
0338 free_tx:
0339     kfree(tx_buf);
0340 
0341     return ret;
0342 }
0343 
0344 static size_t tsc2046_adc_group_set_layout(struct tsc2046_adc_priv *priv,
0345                        unsigned int group,
0346                        unsigned int ch_idx)
0347 {
0348     struct tsc2046_adc_ch_cfg *ch = &priv->ch_cfg[ch_idx];
0349     struct tsc2046_adc_group_layout *cur;
0350     unsigned int max_count, count_skip;
0351     unsigned int offset = 0;
0352 
0353     if (group)
0354         offset = priv->l[group - 1].offset + priv->l[group - 1].count;
0355 
0356     count_skip = tsc2046_adc_time_to_count(priv, ch->settling_time_us);
0357     max_count = count_skip + ch->oversampling_ratio;
0358 
0359     cur = &priv->l[group];
0360     cur->offset = offset;
0361     cur->count = max_count;
0362     cur->skip = count_skip;
0363 
0364     return sizeof(*priv->tx) * max_count;
0365 }
0366 
0367 static void tsc2046_adc_group_set_cmd(struct tsc2046_adc_priv *priv,
0368                       unsigned int group, int ch_idx)
0369 {
0370     struct tsc2046_adc_group_layout *l = &priv->l[group];
0371     unsigned int i;
0372     u8 cmd;
0373 
0374     /*
0375      * Do not enable automatic power down on working samples. Otherwise the
0376      * plates will never be completely charged.
0377      */
0378     cmd = tsc2046_adc_get_cmd(priv, ch_idx, true);
0379 
0380     for (i = 0; i < l->count - 1; i++)
0381         priv->tx[l->offset + i].cmd = cmd;
0382 
0383     /* automatically power down on last sample */
0384     priv->tx[l->offset + i].cmd = tsc2046_adc_get_cmd(priv, ch_idx, false);
0385 }
0386 
0387 static u16 tsc2046_adc_get_val(struct tsc2046_adc_priv *priv, int group)
0388 {
0389     struct tsc2046_adc_group_layout *l;
0390     unsigned int val, val_normalized = 0;
0391     int valid_count, i;
0392 
0393     l = &priv->l[group];
0394     valid_count = l->count - l->skip;
0395 
0396     for (i = 0; i < valid_count; i++) {
0397         val = tsc2046_adc_get_value(&priv->rx[l->offset + l->skip + i]);
0398         val_normalized += val;
0399     }
0400 
0401     return DIV_ROUND_UP(val_normalized, valid_count);
0402 }
0403 
0404 static int tsc2046_adc_scan(struct iio_dev *indio_dev)
0405 {
0406     struct tsc2046_adc_priv *priv = iio_priv(indio_dev);
0407     struct device *dev = &priv->spi->dev;
0408     int group;
0409     int ret;
0410 
0411     ret = spi_sync(priv->spi, &priv->msg);
0412     if (ret < 0) {
0413         dev_err_ratelimited(dev, "SPI transfer failed: %pe\n", ERR_PTR(ret));
0414         return ret;
0415     }
0416 
0417     for (group = 0; group < priv->groups; group++)
0418         priv->scan_buf.data[group] = tsc2046_adc_get_val(priv, group);
0419 
0420     ret = iio_push_to_buffers_with_timestamp(indio_dev, &priv->scan_buf,
0421                          iio_get_time_ns(indio_dev));
0422     /* If the consumer is kfifo, we may get a EBUSY here - ignore it. */
0423     if (ret < 0 && ret != -EBUSY) {
0424         dev_err_ratelimited(dev, "Failed to push scan buffer %pe\n",
0425                     ERR_PTR(ret));
0426 
0427         return ret;
0428     }
0429 
0430     return 0;
0431 }
0432 
0433 static irqreturn_t tsc2046_adc_trigger_handler(int irq, void *p)
0434 {
0435     struct iio_poll_func *pf = p;
0436     struct iio_dev *indio_dev = pf->indio_dev;
0437     struct tsc2046_adc_priv *priv = iio_priv(indio_dev);
0438 
0439     mutex_lock(&priv->slock);
0440     tsc2046_adc_scan(indio_dev);
0441     mutex_unlock(&priv->slock);
0442 
0443     iio_trigger_notify_done(indio_dev->trig);
0444 
0445     return IRQ_HANDLED;
0446 }
0447 
0448 static int tsc2046_adc_read_raw(struct iio_dev *indio_dev,
0449                 struct iio_chan_spec const *chan,
0450                 int *val, int *val2, long m)
0451 {
0452     struct tsc2046_adc_priv *priv = iio_priv(indio_dev);
0453     int ret;
0454 
0455     switch (m) {
0456     case IIO_CHAN_INFO_RAW:
0457         ret = tsc2046_adc_read_one(priv, chan->channel, NULL);
0458         if (ret < 0)
0459             return ret;
0460 
0461         *val = ret;
0462 
0463         return IIO_VAL_INT;
0464     case IIO_CHAN_INFO_SCALE:
0465         /*
0466          * Note: the TSC2046 has internal voltage divider on the VBAT
0467          * line. This divider can be influenced by external divider.
0468          * So, it is better to use external voltage-divider driver
0469          * instead, which is calculating complete chain.
0470          */
0471         *val = TI_TSC2046_INT_VREF;
0472         *val2 = chan->scan_type.realbits;
0473         return IIO_VAL_FRACTIONAL_LOG2;
0474     }
0475 
0476     return -EINVAL;
0477 }
0478 
0479 static int tsc2046_adc_update_scan_mode(struct iio_dev *indio_dev,
0480                     const unsigned long *active_scan_mask)
0481 {
0482     struct tsc2046_adc_priv *priv = iio_priv(indio_dev);
0483     unsigned int ch_idx, group = 0;
0484     size_t size;
0485 
0486     mutex_lock(&priv->slock);
0487 
0488     size = 0;
0489     for_each_set_bit(ch_idx, active_scan_mask, ARRAY_SIZE(priv->l)) {
0490         size += tsc2046_adc_group_set_layout(priv, group, ch_idx);
0491         tsc2046_adc_group_set_cmd(priv, group, ch_idx);
0492         group++;
0493     }
0494 
0495     priv->groups = group;
0496     priv->xfer.len = size;
0497     priv->time_per_scan_us = size * 8 * priv->time_per_bit_ns / NSEC_PER_USEC;
0498 
0499     if (priv->scan_interval_us < priv->time_per_scan_us)
0500         dev_warn(&priv->spi->dev, "The scan interval (%d) is less then calculated scan time (%d)\n",
0501              priv->scan_interval_us, priv->time_per_scan_us);
0502 
0503     mutex_unlock(&priv->slock);
0504 
0505     return 0;
0506 }
0507 
0508 static const struct iio_info tsc2046_adc_info = {
0509     .read_raw     = tsc2046_adc_read_raw,
0510     .update_scan_mode = tsc2046_adc_update_scan_mode,
0511 };
0512 
0513 static enum hrtimer_restart tsc2046_adc_timer(struct hrtimer *hrtimer)
0514 {
0515     struct tsc2046_adc_priv *priv = container_of(hrtimer,
0516                              struct tsc2046_adc_priv,
0517                              trig_timer);
0518     unsigned long flags;
0519 
0520     /*
0521      * This state machine should address following challenges :
0522      * - the interrupt source is based on level shifter attached to the X
0523      *   channel of ADC. It will change the state every time we switch
0524      *   between channels. So, we need to disable IRQ if we do
0525      *   iio_trigger_poll().
0526      * - we should do iio_trigger_poll() at some reduced sample rate
0527      * - we should still trigger for some amount of time after last
0528      *   interrupt with enabled IRQ was processed.
0529      */
0530 
0531     spin_lock_irqsave(&priv->state_lock, flags);
0532     switch (priv->state) {
0533     case TSC2046_STATE_ENABLE_IRQ:
0534         if (priv->poll_cnt < TI_TSC2046_POLL_CNT) {
0535             priv->poll_cnt++;
0536             hrtimer_start(&priv->trig_timer,
0537                       ns_to_ktime(priv->scan_interval_us *
0538                           NSEC_PER_USEC),
0539                       HRTIMER_MODE_REL_SOFT);
0540 
0541             if (priv->poll_cnt >= TI_TSC2046_MIN_POLL_CNT) {
0542                 priv->state = TSC2046_STATE_POLL_IRQ_DISABLE;
0543                 enable_irq(priv->spi->irq);
0544             } else {
0545                 priv->state = TSC2046_STATE_POLL;
0546             }
0547         } else {
0548             priv->state = TSC2046_STATE_STANDBY;
0549             enable_irq(priv->spi->irq);
0550         }
0551         break;
0552     case TSC2046_STATE_POLL_IRQ_DISABLE:
0553         disable_irq_nosync(priv->spi->irq);
0554         fallthrough;
0555     case TSC2046_STATE_POLL:
0556         priv->state = TSC2046_STATE_ENABLE_IRQ;
0557         /* iio_trigger_poll() starts hrtimer */
0558         iio_trigger_poll(priv->trig);
0559         break;
0560     case TSC2046_STATE_SHUTDOWN:
0561         break;
0562     case TSC2046_STATE_STANDBY:
0563         fallthrough;
0564     default:
0565         dev_warn(&priv->spi->dev, "Got unexpected state: %i\n",
0566              priv->state);
0567         break;
0568     }
0569     spin_unlock_irqrestore(&priv->state_lock, flags);
0570 
0571     return HRTIMER_NORESTART;
0572 }
0573 
0574 static irqreturn_t tsc2046_adc_irq(int irq, void *dev_id)
0575 {
0576     struct iio_dev *indio_dev = dev_id;
0577     struct tsc2046_adc_priv *priv = iio_priv(indio_dev);
0578     unsigned long flags;
0579 
0580     hrtimer_try_to_cancel(&priv->trig_timer);
0581 
0582     spin_lock_irqsave(&priv->state_lock, flags);
0583     if (priv->state != TSC2046_STATE_SHUTDOWN) {
0584         priv->state = TSC2046_STATE_ENABLE_IRQ;
0585         priv->poll_cnt = 0;
0586 
0587         /* iio_trigger_poll() starts hrtimer */
0588         disable_irq_nosync(priv->spi->irq);
0589         iio_trigger_poll(priv->trig);
0590     }
0591     spin_unlock_irqrestore(&priv->state_lock, flags);
0592 
0593     return IRQ_HANDLED;
0594 }
0595 
0596 static void tsc2046_adc_reenable_trigger(struct iio_trigger *trig)
0597 {
0598     struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
0599     struct tsc2046_adc_priv *priv = iio_priv(indio_dev);
0600     ktime_t tim;
0601 
0602     /*
0603      * We can sample it as fast as we can, but usually we do not need so
0604      * many samples. Reduce the sample rate for default (touchscreen) use
0605      * case.
0606      */
0607     tim = ns_to_ktime((priv->scan_interval_us - priv->time_per_scan_us) *
0608               NSEC_PER_USEC);
0609     hrtimer_start(&priv->trig_timer, tim, HRTIMER_MODE_REL_SOFT);
0610 }
0611 
0612 static int tsc2046_adc_set_trigger_state(struct iio_trigger *trig, bool enable)
0613 {
0614     struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
0615     struct tsc2046_adc_priv *priv = iio_priv(indio_dev);
0616     unsigned long flags;
0617 
0618     if (enable) {
0619         spin_lock_irqsave(&priv->state_lock, flags);
0620         if (priv->state == TSC2046_STATE_SHUTDOWN) {
0621             priv->state = TSC2046_STATE_STANDBY;
0622             enable_irq(priv->spi->irq);
0623         }
0624         spin_unlock_irqrestore(&priv->state_lock, flags);
0625     } else {
0626         spin_lock_irqsave(&priv->state_lock, flags);
0627 
0628         if (priv->state == TSC2046_STATE_STANDBY ||
0629             priv->state == TSC2046_STATE_POLL_IRQ_DISABLE)
0630             disable_irq_nosync(priv->spi->irq);
0631 
0632         priv->state = TSC2046_STATE_SHUTDOWN;
0633         spin_unlock_irqrestore(&priv->state_lock, flags);
0634 
0635         hrtimer_cancel(&priv->trig_timer);
0636     }
0637 
0638     return 0;
0639 }
0640 
0641 static const struct iio_trigger_ops tsc2046_adc_trigger_ops = {
0642     .set_trigger_state = tsc2046_adc_set_trigger_state,
0643     .reenable = tsc2046_adc_reenable_trigger,
0644 };
0645 
0646 static int tsc2046_adc_setup_spi_msg(struct tsc2046_adc_priv *priv)
0647 {
0648     unsigned int ch_idx;
0649     size_t size;
0650     int ret;
0651 
0652     /*
0653      * Make dummy read to set initial power state and get real SPI clock
0654      * freq. It seems to be not important which channel is used for this
0655      * case.
0656      */
0657     ret = tsc2046_adc_read_one(priv, TI_TSC2046_ADDR_TEMP0,
0658                    &priv->effective_speed_hz);
0659     if (ret < 0)
0660         return ret;
0661 
0662     /*
0663      * In case SPI controller do not report effective_speed_hz, use
0664      * configure value and hope it will match.
0665      */
0666     if (!priv->effective_speed_hz)
0667         priv->effective_speed_hz = priv->spi->max_speed_hz;
0668 
0669 
0670     priv->scan_interval_us = TI_TSC2046_SAMPLE_INTERVAL_US;
0671     priv->time_per_bit_ns = DIV_ROUND_UP(NSEC_PER_SEC,
0672                          priv->effective_speed_hz);
0673 
0674     /*
0675      * Calculate and allocate maximal size buffer if all channels are
0676      * enabled.
0677      */
0678     size = 0;
0679     for (ch_idx = 0; ch_idx < ARRAY_SIZE(priv->l); ch_idx++)
0680         size += tsc2046_adc_group_set_layout(priv, ch_idx, ch_idx);
0681 
0682     if (size > PAGE_SIZE) {
0683         dev_err(&priv->spi->dev,
0684             "Calculated scan buffer is too big. Try to reduce spi-max-frequency, settling-time-us or oversampling-ratio\n");
0685         return -ENOSPC;
0686     }
0687 
0688     priv->tx = devm_kzalloc(&priv->spi->dev, size, GFP_KERNEL);
0689     if (!priv->tx)
0690         return -ENOMEM;
0691 
0692     priv->rx = devm_kzalloc(&priv->spi->dev, size, GFP_KERNEL);
0693     if (!priv->rx)
0694         return -ENOMEM;
0695 
0696     priv->xfer.tx_buf = priv->tx;
0697     priv->xfer.rx_buf = priv->rx;
0698     priv->xfer.len = size;
0699     spi_message_init_with_transfers(&priv->msg, &priv->xfer, 1);
0700 
0701     return 0;
0702 }
0703 
0704 static void tsc2046_adc_parse_fwnode(struct tsc2046_adc_priv *priv)
0705 {
0706     struct fwnode_handle *child;
0707     struct device *dev = &priv->spi->dev;
0708     unsigned int i;
0709 
0710     for (i = 0; i < ARRAY_SIZE(priv->ch_cfg); i++) {
0711         priv->ch_cfg[i].settling_time_us = 1;
0712         priv->ch_cfg[i].oversampling_ratio = 1;
0713     }
0714 
0715     device_for_each_child_node(dev, child) {
0716         u32 stl, overs, reg;
0717         int ret;
0718 
0719         ret = fwnode_property_read_u32(child, "reg", &reg);
0720         if (ret) {
0721             dev_err(dev, "invalid reg on %pfw, err: %pe\n", child,
0722                 ERR_PTR(ret));
0723             continue;
0724         }
0725 
0726         if (reg >= ARRAY_SIZE(priv->ch_cfg)) {
0727             dev_err(dev, "%pfw: Unsupported reg value: %i, max supported is: %zu.\n",
0728                 child, reg, ARRAY_SIZE(priv->ch_cfg));
0729             continue;
0730         }
0731 
0732         ret = fwnode_property_read_u32(child, "settling-time-us", &stl);
0733         if (!ret)
0734             priv->ch_cfg[reg].settling_time_us = stl;
0735 
0736         ret = fwnode_property_read_u32(child, "oversampling-ratio",
0737                            &overs);
0738         if (!ret)
0739             priv->ch_cfg[reg].oversampling_ratio = overs;
0740     }
0741 }
0742 
0743 static int tsc2046_adc_probe(struct spi_device *spi)
0744 {
0745     const struct tsc2046_adc_dcfg *dcfg;
0746     struct device *dev = &spi->dev;
0747     struct tsc2046_adc_priv *priv;
0748     struct iio_dev *indio_dev;
0749     struct iio_trigger *trig;
0750     int ret;
0751 
0752     if (spi->max_speed_hz > TI_TSC2046_MAX_CLK_FREQ) {
0753         dev_err(dev, "SPI max_speed_hz is too high: %d Hz. Max supported freq is %zu Hz\n",
0754             spi->max_speed_hz, TI_TSC2046_MAX_CLK_FREQ);
0755         return -EINVAL;
0756     }
0757 
0758     dcfg = device_get_match_data(dev);
0759     if (!dcfg)
0760         return -EINVAL;
0761 
0762     spi->bits_per_word = 8;
0763     spi->mode &= ~SPI_MODE_X_MASK;
0764     spi->mode |= SPI_MODE_0;
0765     ret = spi_setup(spi);
0766     if (ret < 0)
0767         return dev_err_probe(dev, ret, "Error in SPI setup\n");
0768 
0769     indio_dev = devm_iio_device_alloc(dev, sizeof(*priv));
0770     if (!indio_dev)
0771         return -ENOMEM;
0772 
0773     priv = iio_priv(indio_dev);
0774     priv->dcfg = dcfg;
0775 
0776     priv->spi = spi;
0777 
0778     indio_dev->name = TI_TSC2046_NAME;
0779     indio_dev->modes = INDIO_DIRECT_MODE;
0780     indio_dev->channels = dcfg->channels;
0781     indio_dev->num_channels = dcfg->num_channels;
0782     indio_dev->info = &tsc2046_adc_info;
0783 
0784     tsc2046_adc_parse_fwnode(priv);
0785 
0786     ret = tsc2046_adc_setup_spi_msg(priv);
0787     if (ret)
0788         return ret;
0789 
0790     mutex_init(&priv->slock);
0791 
0792     ret = devm_request_irq(dev, spi->irq, &tsc2046_adc_irq,
0793                    IRQF_NO_AUTOEN, indio_dev->name, indio_dev);
0794     if (ret)
0795         return ret;
0796 
0797     trig = devm_iio_trigger_alloc(dev, "touchscreen-%s", indio_dev->name);
0798     if (!trig)
0799         return -ENOMEM;
0800 
0801     priv->trig = trig;
0802     iio_trigger_set_drvdata(trig, indio_dev);
0803     trig->ops = &tsc2046_adc_trigger_ops;
0804 
0805     spin_lock_init(&priv->state_lock);
0806     priv->state = TSC2046_STATE_SHUTDOWN;
0807     hrtimer_init(&priv->trig_timer, CLOCK_MONOTONIC,
0808              HRTIMER_MODE_REL_SOFT);
0809     priv->trig_timer.function = tsc2046_adc_timer;
0810 
0811     ret = devm_iio_trigger_register(dev, trig);
0812     if (ret) {
0813         dev_err(dev, "failed to register trigger\n");
0814         return ret;
0815     }
0816 
0817     ret = devm_iio_triggered_buffer_setup(dev, indio_dev, NULL,
0818                           &tsc2046_adc_trigger_handler, NULL);
0819     if (ret) {
0820         dev_err(dev, "Failed to setup triggered buffer\n");
0821         return ret;
0822     }
0823 
0824     /* set default trigger */
0825     indio_dev->trig = iio_trigger_get(priv->trig);
0826 
0827     return devm_iio_device_register(dev, indio_dev);
0828 }
0829 
0830 static const struct of_device_id ads7950_of_table[] = {
0831     { .compatible = "ti,tsc2046e-adc", .data = &tsc2046_adc_dcfg_tsc2046e },
0832     { }
0833 };
0834 MODULE_DEVICE_TABLE(of, ads7950_of_table);
0835 
0836 static struct spi_driver tsc2046_adc_driver = {
0837     .driver = {
0838         .name = "tsc2046",
0839         .of_match_table = ads7950_of_table,
0840     },
0841     .probe = tsc2046_adc_probe,
0842 };
0843 module_spi_driver(tsc2046_adc_driver);
0844 
0845 MODULE_AUTHOR("Oleksij Rempel <kernel@pengutronix.de>");
0846 MODULE_DESCRIPTION("TI TSC2046 ADC");
0847 MODULE_LICENSE("GPL v2");
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