iio/adc/ti-ads8688.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (C) 2015 Prevas A/S
0004  */
0005
0006 #include <linux/device.h>
0007 #include <linux/kernel.h>
0008 #include <linux/slab.h>
0009 #include <linux/sysfs.h>
0010 #include <linux/spi/spi.h>
0011 #include <linux/regulator/consumer.h>
0012 #include <linux/err.h>
0013 #include <linux/module.h>
0014 #include <linux/of.h>
0015
0016 #include <linux/iio/iio.h>
0017 #include <linux/iio/buffer.h>
0018 #include <linux/iio/trigger_consumer.h>
0019 #include <linux/iio/triggered_buffer.h>
0020 #include <linux/iio/sysfs.h>
0021
0022 #define ADS8688_CMD_REG(x)      (x << 8)
0023 #define ADS8688_CMD_REG_NOOP        0x00
0024 #define ADS8688_CMD_REG_RST     0x85
0025 #define ADS8688_CMD_REG_MAN_CH(chan)    (0xC0 | (4 * chan))
0026 #define ADS8688_CMD_DONT_CARE_BITS  16
0027
0028 #define ADS8688_PROG_REG(x)     (x << 9)
0029 #define ADS8688_PROG_REG_RANGE_CH(chan) (0x05 + chan)
0030 #define ADS8688_PROG_WR_BIT     BIT(8)
0031 #define ADS8688_PROG_DONT_CARE_BITS 8
0032
0033 #define ADS8688_REG_PLUSMINUS25VREF 0
0034 #define ADS8688_REG_PLUSMINUS125VREF    1
0035 #define ADS8688_REG_PLUSMINUS0625VREF   2
0036 #define ADS8688_REG_PLUS25VREF      5
0037 #define ADS8688_REG_PLUS125VREF     6
0038
0039 #define ADS8688_VREF_MV         4096
0040 #define ADS8688_REALBITS        16
0041 #define ADS8688_MAX_CHANNELS        8
0042
0043 /*
0044  * enum ads8688_range - ADS8688 reference voltage range
0045  * @ADS8688_PLUSMINUS25VREF: Device is configured for input range ±2.5 * VREF
0046  * @ADS8688_PLUSMINUS125VREF: Device is configured for input range ±1.25 * VREF
0047  * @ADS8688_PLUSMINUS0625VREF: Device is configured for input range ±0.625 * VREF
0048  * @ADS8688_PLUS25VREF: Device is configured for input range 0 - 2.5 * VREF
0049  * @ADS8688_PLUS125VREF: Device is configured for input range 0 - 1.25 * VREF
0050  */
0051 enum ads8688_range {
0052     ADS8688_PLUSMINUS25VREF,
0053     ADS8688_PLUSMINUS125VREF,
0054     ADS8688_PLUSMINUS0625VREF,
0055     ADS8688_PLUS25VREF,
0056     ADS8688_PLUS125VREF,
0057 };
0058
0059 struct ads8688_chip_info {
0060     const struct iio_chan_spec *channels;
0061     unsigned int num_channels;
0062 };
0063
0064 struct ads8688_state {
0065     struct mutex            lock;
0066     const struct ads8688_chip_info  *chip_info;
0067     struct spi_device       *spi;
0068     struct regulator        *reg;
0069     unsigned int            vref_mv;
0070     enum ads8688_range      range[8];
0071     union {
0072         __be32 d32;
0073         u8 d8[4];
0074     } data[2] __aligned(IIO_DMA_MINALIGN);
0075 };
0076
0077 enum ads8688_id {
0078     ID_ADS8684,
0079     ID_ADS8688,
0080 };
0081
0082 struct ads8688_ranges {
0083     enum ads8688_range range;
0084     unsigned int scale;
0085     int offset;
0086     u8 reg;
0087 };
0088
0089 static const struct ads8688_ranges ads8688_range_def[5] = {
0090     {
0091         .range = ADS8688_PLUSMINUS25VREF,
0092         .scale = 76295,
0093         .offset = -(1 << (ADS8688_REALBITS - 1)),
0094         .reg = ADS8688_REG_PLUSMINUS25VREF,
0095     }, {
0096         .range = ADS8688_PLUSMINUS125VREF,
0097         .scale = 38148,
0098         .offset = -(1 << (ADS8688_REALBITS - 1)),
0099         .reg = ADS8688_REG_PLUSMINUS125VREF,
0100     }, {
0101         .range = ADS8688_PLUSMINUS0625VREF,
0102         .scale = 19074,
0103         .offset = -(1 << (ADS8688_REALBITS - 1)),
0104         .reg = ADS8688_REG_PLUSMINUS0625VREF,
0105     }, {
0106         .range = ADS8688_PLUS25VREF,
0107         .scale = 38148,
0108         .offset = 0,
0109         .reg = ADS8688_REG_PLUS25VREF,
0110     }, {
0111         .range = ADS8688_PLUS125VREF,
0112         .scale = 19074,
0113         .offset = 0,
0114         .reg = ADS8688_REG_PLUS125VREF,
0115     }
0116 };
0117
0118 static ssize_t ads8688_show_scales(struct device *dev,
0119                    struct device_attribute *attr, char *buf)
0120 {
0121     struct ads8688_state *st = iio_priv(dev_to_iio_dev(dev));
0122
0123     return sprintf(buf, "0.%09u 0.%09u 0.%09u\n",
0124                ads8688_range_def[0].scale * st->vref_mv,
0125                ads8688_range_def[1].scale * st->vref_mv,
0126                ads8688_range_def[2].scale * st->vref_mv);
0127 }
0128
0129 static ssize_t ads8688_show_offsets(struct device *dev,
0130                     struct device_attribute *attr, char *buf)
0131 {
0132     return sprintf(buf, "%d %d\n", ads8688_range_def[0].offset,
0133                ads8688_range_def[3].offset);
0134 }
0135
0136 static IIO_DEVICE_ATTR(in_voltage_scale_available, S_IRUGO,
0137                ads8688_show_scales, NULL, 0);
0138 static IIO_DEVICE_ATTR(in_voltage_offset_available, S_IRUGO,
0139                ads8688_show_offsets, NULL, 0);
0140
0141 static struct attribute *ads8688_attributes[] = {
0142     &iio_dev_attr_in_voltage_scale_available.dev_attr.attr,
0143     &iio_dev_attr_in_voltage_offset_available.dev_attr.attr,
0144     NULL,
0145 };
0146
0147 static const struct attribute_group ads8688_attribute_group = {
0148     .attrs = ads8688_attributes,
0149 };
0150
0151 #define ADS8688_CHAN(index)                 \
0152 {                               \
0153     .type = IIO_VOLTAGE,                    \
0154     .indexed = 1,                       \
0155     .channel = index,                   \
0156     .info_mask_separate = BIT(IIO_CHAN_INFO_RAW)        \
0157                   | BIT(IIO_CHAN_INFO_SCALE)    \
0158                   | BIT(IIO_CHAN_INFO_OFFSET),  \
0159     .scan_index = index,                    \
0160     .scan_type = {                      \
0161         .sign = 'u',                    \
0162         .realbits = 16,                 \
0163         .storagebits = 16,              \
0164         .endianness = IIO_BE,               \
0165     },                          \
0166 }
0167
0168 static const struct iio_chan_spec ads8684_channels[] = {
0169     ADS8688_CHAN(0),
0170     ADS8688_CHAN(1),
0171     ADS8688_CHAN(2),
0172     ADS8688_CHAN(3),
0173 };
0174
0175 static const struct iio_chan_spec ads8688_channels[] = {
0176     ADS8688_CHAN(0),
0177     ADS8688_CHAN(1),
0178     ADS8688_CHAN(2),
0179     ADS8688_CHAN(3),
0180     ADS8688_CHAN(4),
0181     ADS8688_CHAN(5),
0182     ADS8688_CHAN(6),
0183     ADS8688_CHAN(7),
0184 };
0185
0186 static int ads8688_prog_write(struct iio_dev *indio_dev, unsigned int addr,
0187                   unsigned int val)
0188 {
0189     struct ads8688_state *st = iio_priv(indio_dev);
0190     u32 tmp;
0191
0192     tmp = ADS8688_PROG_REG(addr) | ADS8688_PROG_WR_BIT | val;
0193     tmp <<= ADS8688_PROG_DONT_CARE_BITS;
0194     st->data[0].d32 = cpu_to_be32(tmp);
0195
0196     return spi_write(st->spi, &st->data[0].d8[1], 3);
0197 }
0198
0199 static int ads8688_reset(struct iio_dev *indio_dev)
0200 {
0201     struct ads8688_state *st = iio_priv(indio_dev);
0202     u32 tmp;
0203
0204     tmp = ADS8688_CMD_REG(ADS8688_CMD_REG_RST);
0205     tmp <<= ADS8688_CMD_DONT_CARE_BITS;
0206     st->data[0].d32 = cpu_to_be32(tmp);
0207
0208     return spi_write(st->spi, &st->data[0].d8[0], 4);
0209 }
0210
0211 static int ads8688_read(struct iio_dev *indio_dev, unsigned int chan)
0212 {
0213     struct ads8688_state *st = iio_priv(indio_dev);
0214     int ret;
0215     u32 tmp;
0216     struct spi_transfer t[] = {
0217         {
0218             .tx_buf = &st->data[0].d8[0],
0219             .len = 4,
0220             .cs_change = 1,
0221         }, {
0222             .tx_buf = &st->data[1].d8[0],
0223             .rx_buf = &st->data[1].d8[0],
0224             .len = 4,
0225         },
0226     };
0227
0228     tmp = ADS8688_CMD_REG(ADS8688_CMD_REG_MAN_CH(chan));
0229     tmp <<= ADS8688_CMD_DONT_CARE_BITS;
0230     st->data[0].d32 = cpu_to_be32(tmp);
0231
0232     tmp = ADS8688_CMD_REG(ADS8688_CMD_REG_NOOP);
0233     tmp <<= ADS8688_CMD_DONT_CARE_BITS;
0234     st->data[1].d32 = cpu_to_be32(tmp);
0235
0236     ret = spi_sync_transfer(st->spi, t, ARRAY_SIZE(t));
0237     if (ret < 0)
0238         return ret;
0239
0240     return be32_to_cpu(st->data[1].d32) & 0xffff;
0241 }
0242
0243 static int ads8688_read_raw(struct iio_dev *indio_dev,
0244                 struct iio_chan_spec const *chan,
0245                 int *val, int *val2, long m)
0246 {
0247     int ret, offset;
0248     unsigned long scale_mv;
0249
0250     struct ads8688_state *st = iio_priv(indio_dev);
0251
0252     mutex_lock(&st->lock);
0253     switch (m) {
0254     case IIO_CHAN_INFO_RAW:
0255         ret = ads8688_read(indio_dev, chan->channel);
0256         mutex_unlock(&st->lock);
0257         if (ret < 0)
0258             return ret;
0259         *val = ret;
0260         return IIO_VAL_INT;
0261     case IIO_CHAN_INFO_SCALE:
0262         scale_mv = st->vref_mv;
0263         scale_mv *= ads8688_range_def[st->range[chan->channel]].scale;
0264         *val = 0;
0265         *val2 = scale_mv;
0266         mutex_unlock(&st->lock);
0267         return IIO_VAL_INT_PLUS_NANO;
0268     case IIO_CHAN_INFO_OFFSET:
0269         offset = ads8688_range_def[st->range[chan->channel]].offset;
0270         *val = offset;
0271         mutex_unlock(&st->lock);
0272         return IIO_VAL_INT;
0273     }
0274     mutex_unlock(&st->lock);
0275
0276     return -EINVAL;
0277 }
0278
0279 static int ads8688_write_reg_range(struct iio_dev *indio_dev,
0280                    struct iio_chan_spec const *chan,
0281                    enum ads8688_range range)
0282 {
0283     unsigned int tmp;
0284
0285     tmp = ADS8688_PROG_REG_RANGE_CH(chan->channel);
0286
0287     return ads8688_prog_write(indio_dev, tmp, range);
0288 }
0289
0290 static int ads8688_write_raw(struct iio_dev *indio_dev,
0291                  struct iio_chan_spec const *chan,
0292                  int val, int val2, long mask)
0293 {
0294     struct ads8688_state *st = iio_priv(indio_dev);
0295     unsigned int scale = 0;
0296     int ret = -EINVAL, i, offset = 0;
0297
0298     mutex_lock(&st->lock);
0299     switch (mask) {
0300     case IIO_CHAN_INFO_SCALE:
0301         /* If the offset is 0 the ±2.5 * VREF mode is not available */
0302         offset = ads8688_range_def[st->range[chan->channel]].offset;
0303         if (offset == 0 && val2 == ads8688_range_def[0].scale * st->vref_mv) {
0304             mutex_unlock(&st->lock);
0305             return -EINVAL;
0306         }
0307
0308         /* Lookup new mode */
0309         for (i = 0; i < ARRAY_SIZE(ads8688_range_def); i++)
0310             if (val2 == ads8688_range_def[i].scale * st->vref_mv &&
0311                 offset == ads8688_range_def[i].offset) {
0312                 ret = ads8688_write_reg_range(indio_dev, chan,
0313                     ads8688_range_def[i].reg);
0314                 break;
0315             }
0316         break;
0317     case IIO_CHAN_INFO_OFFSET:
0318         /*
0319          * There are only two available offsets:
0320          * 0 and -(1 << (ADS8688_REALBITS - 1))
0321          */
0322         if (!(ads8688_range_def[0].offset == val ||
0323             ads8688_range_def[3].offset == val)) {
0324             mutex_unlock(&st->lock);
0325             return -EINVAL;
0326         }
0327
0328         /*
0329          * If the device are in ±2.5 * VREF mode, it's not allowed to
0330          * switch to a mode where the offset is 0
0331          */
0332         if (val == 0 &&
0333             st->range[chan->channel] == ADS8688_PLUSMINUS25VREF) {
0334             mutex_unlock(&st->lock);
0335             return -EINVAL;
0336         }
0337
0338         scale = ads8688_range_def[st->range[chan->channel]].scale;
0339
0340         /* Lookup new mode */
0341         for (i = 0; i < ARRAY_SIZE(ads8688_range_def); i++)
0342             if (val == ads8688_range_def[i].offset &&
0343                 scale == ads8688_range_def[i].scale) {
0344                 ret = ads8688_write_reg_range(indio_dev, chan,
0345                     ads8688_range_def[i].reg);
0346                 break;
0347             }
0348         break;
0349     }
0350
0351     if (!ret)
0352         st->range[chan->channel] = ads8688_range_def[i].range;
0353
0354     mutex_unlock(&st->lock);
0355
0356     return ret;
0357 }
0358
0359 static int ads8688_write_raw_get_fmt(struct iio_dev *indio_dev,
0360                      struct iio_chan_spec const *chan,
0361                      long mask)
0362 {
0363     switch (mask) {
0364     case IIO_CHAN_INFO_SCALE:
0365         return IIO_VAL_INT_PLUS_NANO;
0366     case IIO_CHAN_INFO_OFFSET:
0367         return IIO_VAL_INT;
0368     }
0369
0370     return -EINVAL;
0371 }
0372
0373 static const struct iio_info ads8688_info = {
0374     .read_raw = &ads8688_read_raw,
0375     .write_raw = &ads8688_write_raw,
0376     .write_raw_get_fmt = &ads8688_write_raw_get_fmt,
0377     .attrs = &ads8688_attribute_group,
0378 };
0379
0380 static irqreturn_t ads8688_trigger_handler(int irq, void *p)
0381 {
0382     struct iio_poll_func *pf = p;
0383     struct iio_dev *indio_dev = pf->indio_dev;
0384     /* Ensure naturally aligned timestamp */
0385     u16 buffer[ADS8688_MAX_CHANNELS + sizeof(s64)/sizeof(u16)] __aligned(8);
0386     int i, j = 0;
0387
0388     for (i = 0; i < indio_dev->masklength; i++) {
0389         if (!test_bit(i, indio_dev->active_scan_mask))
0390             continue;
0391         buffer[j] = ads8688_read(indio_dev, i);
0392         j++;
0393     }
0394
0395     iio_push_to_buffers_with_timestamp(indio_dev, buffer,
0396             iio_get_time_ns(indio_dev));
0397
0398     iio_trigger_notify_done(indio_dev->trig);
0399
0400     return IRQ_HANDLED;
0401 }
0402
0403 static const struct ads8688_chip_info ads8688_chip_info_tbl[] = {
0404     [ID_ADS8684] = {
0405         .channels = ads8684_channels,
0406         .num_channels = ARRAY_SIZE(ads8684_channels),
0407     },
0408     [ID_ADS8688] = {
0409         .channels = ads8688_channels,
0410         .num_channels = ARRAY_SIZE(ads8688_channels),
0411     },
0412 };
0413
0414 static int ads8688_probe(struct spi_device *spi)
0415 {
0416     struct ads8688_state *st;
0417     struct iio_dev *indio_dev;
0418     int ret;
0419
0420     indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
0421     if (indio_dev == NULL)
0422         return -ENOMEM;
0423
0424     st = iio_priv(indio_dev);
0425
0426     st->reg = devm_regulator_get_optional(&spi->dev, "vref");
0427     if (!IS_ERR(st->reg)) {
0428         ret = regulator_enable(st->reg);
0429         if (ret)
0430             return ret;
0431
0432         ret = regulator_get_voltage(st->reg);
0433         if (ret < 0)
0434             goto err_regulator_disable;
0435
0436         st->vref_mv = ret / 1000;
0437     } else {
0438         /* Use internal reference */
0439         st->vref_mv = ADS8688_VREF_MV;
0440     }
0441
0442     st->chip_info = &ads8688_chip_info_tbl[spi_get_device_id(spi)->driver_data];
0443
0444     spi->mode = SPI_MODE_1;
0445
0446     spi_set_drvdata(spi, indio_dev);
0447
0448     st->spi = spi;
0449
0450     indio_dev->name = spi_get_device_id(spi)->name;
0451     indio_dev->modes = INDIO_DIRECT_MODE;
0452     indio_dev->channels = st->chip_info->channels;
0453     indio_dev->num_channels = st->chip_info->num_channels;
0454     indio_dev->info = &ads8688_info;
0455
0456     ads8688_reset(indio_dev);
0457
0458     mutex_init(&st->lock);
0459
0460     ret = iio_triggered_buffer_setup(indio_dev, NULL, ads8688_trigger_handler, NULL);
0461     if (ret < 0) {
0462         dev_err(&spi->dev, "iio triggered buffer setup failed\n");
0463         goto err_regulator_disable;
0464     }
0465
0466     ret = iio_device_register(indio_dev);
0467     if (ret)
0468         goto err_buffer_cleanup;
0469
0470     return 0;
0471
0472 err_buffer_cleanup:
0473     iio_triggered_buffer_cleanup(indio_dev);
0474
0475 err_regulator_disable:
0476     if (!IS_ERR(st->reg))
0477         regulator_disable(st->reg);
0478
0479     return ret;
0480 }
0481
0482 static void ads8688_remove(struct spi_device *spi)
0483 {
0484     struct iio_dev *indio_dev = spi_get_drvdata(spi);
0485     struct ads8688_state *st = iio_priv(indio_dev);
0486
0487     iio_device_unregister(indio_dev);
0488     iio_triggered_buffer_cleanup(indio_dev);
0489
0490     if (!IS_ERR(st->reg))
0491         regulator_disable(st->reg);
0492 }
0493
0494 static const struct spi_device_id ads8688_id[] = {
0495     {"ads8684", ID_ADS8684},
0496     {"ads8688", ID_ADS8688},
0497     {}
0498 };
0499 MODULE_DEVICE_TABLE(spi, ads8688_id);
0500
0501 static const struct of_device_id ads8688_of_match[] = {
0502     { .compatible = "ti,ads8684" },
0503     { .compatible = "ti,ads8688" },
0504     { }
0505 };
0506 MODULE_DEVICE_TABLE(of, ads8688_of_match);
0507
0508 static struct spi_driver ads8688_driver = {
0509     .driver = {
0510         .name   = "ads8688",
0511         .of_match_table = ads8688_of_match,
0512     },
0513     .probe      = ads8688_probe,
0514     .remove     = ads8688_remove,
0515     .id_table   = ads8688_id,
0516 };
0517 module_spi_driver(ads8688_driver);
0518
0519 MODULE_AUTHOR("Sean Nyekjaer <sean@geanix.dk>");
0520 MODULE_DESCRIPTION("Texas Instruments ADS8688 driver");
0521 MODULE_LICENSE("GPL v2");