iio/adc/ti-ads7950.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Texas Instruments ADS7950 SPI ADC driver
0004  *
0005  * Copyright 2016 David Lechner <david@lechnology.com>
0006  *
0007  * Based on iio/ad7923.c:
0008  * Copyright 2011 Analog Devices Inc
0009  * Copyright 2012 CS Systemes d'Information
0010  *
0011  * And also on hwmon/ads79xx.c
0012  * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
0013  *  Nishanth Menon
0014  */
0015
0016 #include <linux/acpi.h>
0017 #include <linux/bitops.h>
0018 #include <linux/device.h>
0019 #include <linux/err.h>
0020 #include <linux/gpio/driver.h>
0021 #include <linux/interrupt.h>
0022 #include <linux/kernel.h>
0023 #include <linux/module.h>
0024 #include <linux/regulator/consumer.h>
0025 #include <linux/slab.h>
0026 #include <linux/spi/spi.h>
0027
0028 #include <linux/iio/buffer.h>
0029 #include <linux/iio/iio.h>
0030 #include <linux/iio/sysfs.h>
0031 #include <linux/iio/trigger_consumer.h>
0032 #include <linux/iio/triggered_buffer.h>
0033
0034 /*
0035  * In case of ACPI, we use the 5000 mV as default for the reference pin.
0036  * Device tree users encode that via the vref-supply regulator.
0037  */
0038 #define TI_ADS7950_VA_MV_ACPI_DEFAULT   5000
0039
0040 #define TI_ADS7950_CR_GPIO  BIT(14)
0041 #define TI_ADS7950_CR_MANUAL    BIT(12)
0042 #define TI_ADS7950_CR_WRITE BIT(11)
0043 #define TI_ADS7950_CR_CHAN(ch)  ((ch) << 7)
0044 #define TI_ADS7950_CR_RANGE_5V  BIT(6)
0045 #define TI_ADS7950_CR_GPIO_DATA BIT(4)
0046
0047 #define TI_ADS7950_MAX_CHAN 16
0048 #define TI_ADS7950_NUM_GPIOS    4
0049
0050 #define TI_ADS7950_TIMESTAMP_SIZE (sizeof(int64_t) / sizeof(__be16))
0051
0052 /* val = value, dec = left shift, bits = number of bits of the mask */
0053 #define TI_ADS7950_EXTRACT(val, dec, bits) \
0054     (((val) >> (dec)) & ((1 << (bits)) - 1))
0055
0056 #define TI_ADS7950_MAN_CMD(cmd)         (TI_ADS7950_CR_MANUAL | (cmd))
0057 #define TI_ADS7950_GPIO_CMD(cmd)        (TI_ADS7950_CR_GPIO | (cmd))
0058
0059 /* Manual mode configuration */
0060 #define TI_ADS7950_MAN_CMD_SETTINGS(st) \
0061     (TI_ADS7950_MAN_CMD(TI_ADS7950_CR_WRITE | st->cmd_settings_bitmask))
0062 /* GPIO mode configuration */
0063 #define TI_ADS7950_GPIO_CMD_SETTINGS(st) \
0064     (TI_ADS7950_GPIO_CMD(st->gpio_cmd_settings_bitmask))
0065
0066 struct ti_ads7950_state {
0067     struct spi_device   *spi;
0068     struct spi_transfer ring_xfer;
0069     struct spi_transfer scan_single_xfer[3];
0070     struct spi_message  ring_msg;
0071     struct spi_message  scan_single_msg;
0072
0073     /* Lock to protect the spi xfer buffers */
0074     struct mutex        slock;
0075     struct gpio_chip    chip;
0076
0077     struct regulator    *reg;
0078     unsigned int        vref_mv;
0079
0080     /*
0081      * Bitmask of lower 7 bits used for configuration
0082      * These bits only can be written when TI_ADS7950_CR_WRITE
0083      * is set, otherwise it retains its original state.
0084      * [0-3] GPIO signal
0085      * [4]   Set following frame to return GPIO signal values
0086      * [5]   Powers down device
0087      * [6]   Sets Vref range1(2.5v) or range2(5v)
0088      *
0089      * Bits present on Manual/Auto1/Auto2 commands
0090      */
0091     unsigned int        cmd_settings_bitmask;
0092
0093     /*
0094      * Bitmask of GPIO command
0095      * [0-3] GPIO direction
0096      * [4-6] Different GPIO alarm mode configurations
0097      * [7]   GPIO 2 as device range input
0098      * [8]   GPIO 3 as device power down input
0099      * [9]   Reset all registers
0100      * [10-11] N/A
0101      */
0102     unsigned int        gpio_cmd_settings_bitmask;
0103
0104     /*
0105      * DMA (thus cache coherency maintenance) may require the
0106      * transfer buffers to live in their own cache lines.
0107      */
0108     u16 rx_buf[TI_ADS7950_MAX_CHAN + 2 + TI_ADS7950_TIMESTAMP_SIZE]
0109         __aligned(IIO_DMA_MINALIGN);
0110     u16 tx_buf[TI_ADS7950_MAX_CHAN + 2];
0111     u16 single_tx;
0112     u16 single_rx;
0113
0114 };
0115
0116 struct ti_ads7950_chip_info {
0117     const struct iio_chan_spec *channels;
0118     unsigned int num_channels;
0119 };
0120
0121 enum ti_ads7950_id {
0122     TI_ADS7950,
0123     TI_ADS7951,
0124     TI_ADS7952,
0125     TI_ADS7953,
0126     TI_ADS7954,
0127     TI_ADS7955,
0128     TI_ADS7956,
0129     TI_ADS7957,
0130     TI_ADS7958,
0131     TI_ADS7959,
0132     TI_ADS7960,
0133     TI_ADS7961,
0134 };
0135
0136 #define TI_ADS7950_V_CHAN(index, bits)              \
0137 {                               \
0138     .type = IIO_VOLTAGE,                    \
0139     .indexed = 1,                       \
0140     .channel = index,                   \
0141     .info_mask_separate = BIT(IIO_CHAN_INFO_RAW),       \
0142     .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),   \
0143     .address = index,                   \
0144     .datasheet_name = "CH##index",              \
0145     .scan_index = index,                    \
0146     .scan_type = {                      \
0147         .sign = 'u',                    \
0148         .realbits = bits,               \
0149         .storagebits = 16,              \
0150         .shift = 12 - (bits),               \
0151         .endianness = IIO_CPU,              \
0152     },                          \
0153 }
0154
0155 #define DECLARE_TI_ADS7950_4_CHANNELS(name, bits) \
0156 const struct iio_chan_spec name ## _channels[] = { \
0157     TI_ADS7950_V_CHAN(0, bits), \
0158     TI_ADS7950_V_CHAN(1, bits), \
0159     TI_ADS7950_V_CHAN(2, bits), \
0160     TI_ADS7950_V_CHAN(3, bits), \
0161     IIO_CHAN_SOFT_TIMESTAMP(4), \
0162 }
0163
0164 #define DECLARE_TI_ADS7950_8_CHANNELS(name, bits) \
0165 const struct iio_chan_spec name ## _channels[] = { \
0166     TI_ADS7950_V_CHAN(0, bits), \
0167     TI_ADS7950_V_CHAN(1, bits), \
0168     TI_ADS7950_V_CHAN(2, bits), \
0169     TI_ADS7950_V_CHAN(3, bits), \
0170     TI_ADS7950_V_CHAN(4, bits), \
0171     TI_ADS7950_V_CHAN(5, bits), \
0172     TI_ADS7950_V_CHAN(6, bits), \
0173     TI_ADS7950_V_CHAN(7, bits), \
0174     IIO_CHAN_SOFT_TIMESTAMP(8), \
0175 }
0176
0177 #define DECLARE_TI_ADS7950_12_CHANNELS(name, bits) \
0178 const struct iio_chan_spec name ## _channels[] = { \
0179     TI_ADS7950_V_CHAN(0, bits), \
0180     TI_ADS7950_V_CHAN(1, bits), \
0181     TI_ADS7950_V_CHAN(2, bits), \
0182     TI_ADS7950_V_CHAN(3, bits), \
0183     TI_ADS7950_V_CHAN(4, bits), \
0184     TI_ADS7950_V_CHAN(5, bits), \
0185     TI_ADS7950_V_CHAN(6, bits), \
0186     TI_ADS7950_V_CHAN(7, bits), \
0187     TI_ADS7950_V_CHAN(8, bits), \
0188     TI_ADS7950_V_CHAN(9, bits), \
0189     TI_ADS7950_V_CHAN(10, bits), \
0190     TI_ADS7950_V_CHAN(11, bits), \
0191     IIO_CHAN_SOFT_TIMESTAMP(12), \
0192 }
0193
0194 #define DECLARE_TI_ADS7950_16_CHANNELS(name, bits) \
0195 const struct iio_chan_spec name ## _channels[] = { \
0196     TI_ADS7950_V_CHAN(0, bits), \
0197     TI_ADS7950_V_CHAN(1, bits), \
0198     TI_ADS7950_V_CHAN(2, bits), \
0199     TI_ADS7950_V_CHAN(3, bits), \
0200     TI_ADS7950_V_CHAN(4, bits), \
0201     TI_ADS7950_V_CHAN(5, bits), \
0202     TI_ADS7950_V_CHAN(6, bits), \
0203     TI_ADS7950_V_CHAN(7, bits), \
0204     TI_ADS7950_V_CHAN(8, bits), \
0205     TI_ADS7950_V_CHAN(9, bits), \
0206     TI_ADS7950_V_CHAN(10, bits), \
0207     TI_ADS7950_V_CHAN(11, bits), \
0208     TI_ADS7950_V_CHAN(12, bits), \
0209     TI_ADS7950_V_CHAN(13, bits), \
0210     TI_ADS7950_V_CHAN(14, bits), \
0211     TI_ADS7950_V_CHAN(15, bits), \
0212     IIO_CHAN_SOFT_TIMESTAMP(16), \
0213 }
0214
0215 static DECLARE_TI_ADS7950_4_CHANNELS(ti_ads7950, 12);
0216 static DECLARE_TI_ADS7950_8_CHANNELS(ti_ads7951, 12);
0217 static DECLARE_TI_ADS7950_12_CHANNELS(ti_ads7952, 12);
0218 static DECLARE_TI_ADS7950_16_CHANNELS(ti_ads7953, 12);
0219 static DECLARE_TI_ADS7950_4_CHANNELS(ti_ads7954, 10);
0220 static DECLARE_TI_ADS7950_8_CHANNELS(ti_ads7955, 10);
0221 static DECLARE_TI_ADS7950_12_CHANNELS(ti_ads7956, 10);
0222 static DECLARE_TI_ADS7950_16_CHANNELS(ti_ads7957, 10);
0223 static DECLARE_TI_ADS7950_4_CHANNELS(ti_ads7958, 8);
0224 static DECLARE_TI_ADS7950_8_CHANNELS(ti_ads7959, 8);
0225 static DECLARE_TI_ADS7950_12_CHANNELS(ti_ads7960, 8);
0226 static DECLARE_TI_ADS7950_16_CHANNELS(ti_ads7961, 8);
0227
0228 static const struct ti_ads7950_chip_info ti_ads7950_chip_info[] = {
0229     [TI_ADS7950] = {
0230         .channels   = ti_ads7950_channels,
0231         .num_channels   = ARRAY_SIZE(ti_ads7950_channels),
0232     },
0233     [TI_ADS7951] = {
0234         .channels   = ti_ads7951_channels,
0235         .num_channels   = ARRAY_SIZE(ti_ads7951_channels),
0236     },
0237     [TI_ADS7952] = {
0238         .channels   = ti_ads7952_channels,
0239         .num_channels   = ARRAY_SIZE(ti_ads7952_channels),
0240     },
0241     [TI_ADS7953] = {
0242         .channels   = ti_ads7953_channels,
0243         .num_channels   = ARRAY_SIZE(ti_ads7953_channels),
0244     },
0245     [TI_ADS7954] = {
0246         .channels   = ti_ads7954_channels,
0247         .num_channels   = ARRAY_SIZE(ti_ads7954_channels),
0248     },
0249     [TI_ADS7955] = {
0250         .channels   = ti_ads7955_channels,
0251         .num_channels   = ARRAY_SIZE(ti_ads7955_channels),
0252     },
0253     [TI_ADS7956] = {
0254         .channels   = ti_ads7956_channels,
0255         .num_channels   = ARRAY_SIZE(ti_ads7956_channels),
0256     },
0257     [TI_ADS7957] = {
0258         .channels   = ti_ads7957_channels,
0259         .num_channels   = ARRAY_SIZE(ti_ads7957_channels),
0260     },
0261     [TI_ADS7958] = {
0262         .channels   = ti_ads7958_channels,
0263         .num_channels   = ARRAY_SIZE(ti_ads7958_channels),
0264     },
0265     [TI_ADS7959] = {
0266         .channels   = ti_ads7959_channels,
0267         .num_channels   = ARRAY_SIZE(ti_ads7959_channels),
0268     },
0269     [TI_ADS7960] = {
0270         .channels   = ti_ads7960_channels,
0271         .num_channels   = ARRAY_SIZE(ti_ads7960_channels),
0272     },
0273     [TI_ADS7961] = {
0274         .channels   = ti_ads7961_channels,
0275         .num_channels   = ARRAY_SIZE(ti_ads7961_channels),
0276     },
0277 };
0278
0279 /*
0280  * ti_ads7950_update_scan_mode() setup the spi transfer buffer for the new
0281  * scan mask
0282  */
0283 static int ti_ads7950_update_scan_mode(struct iio_dev *indio_dev,
0284                        const unsigned long *active_scan_mask)
0285 {
0286     struct ti_ads7950_state *st = iio_priv(indio_dev);
0287     int i, cmd, len;
0288
0289     len = 0;
0290     for_each_set_bit(i, active_scan_mask, indio_dev->num_channels) {
0291         cmd = TI_ADS7950_MAN_CMD(TI_ADS7950_CR_CHAN(i));
0292         st->tx_buf[len++] = cmd;
0293     }
0294
0295     /* Data for the 1st channel is not returned until the 3rd transfer */
0296     st->tx_buf[len++] = 0;
0297     st->tx_buf[len++] = 0;
0298
0299     st->ring_xfer.len = len * 2;
0300
0301     return 0;
0302 }
0303
0304 static irqreturn_t ti_ads7950_trigger_handler(int irq, void *p)
0305 {
0306     struct iio_poll_func *pf = p;
0307     struct iio_dev *indio_dev = pf->indio_dev;
0308     struct ti_ads7950_state *st = iio_priv(indio_dev);
0309     int ret;
0310
0311     mutex_lock(&st->slock);
0312     ret = spi_sync(st->spi, &st->ring_msg);
0313     if (ret < 0)
0314         goto out;
0315
0316     iio_push_to_buffers_with_timestamp(indio_dev, &st->rx_buf[2],
0317                        iio_get_time_ns(indio_dev));
0318
0319 out:
0320     mutex_unlock(&st->slock);
0321     iio_trigger_notify_done(indio_dev->trig);
0322
0323     return IRQ_HANDLED;
0324 }
0325
0326 static int ti_ads7950_scan_direct(struct iio_dev *indio_dev, unsigned int ch)
0327 {
0328     struct ti_ads7950_state *st = iio_priv(indio_dev);
0329     int ret, cmd;
0330
0331     mutex_lock(&st->slock);
0332     cmd = TI_ADS7950_MAN_CMD(TI_ADS7950_CR_CHAN(ch));
0333     st->single_tx = cmd;
0334
0335     ret = spi_sync(st->spi, &st->scan_single_msg);
0336     if (ret)
0337         goto out;
0338
0339     ret = st->single_rx;
0340
0341 out:
0342     mutex_unlock(&st->slock);
0343
0344     return ret;
0345 }
0346
0347 static int ti_ads7950_get_range(struct ti_ads7950_state *st)
0348 {
0349     int vref;
0350
0351     if (st->vref_mv) {
0352         vref = st->vref_mv;
0353     } else {
0354         vref = regulator_get_voltage(st->reg);
0355         if (vref < 0)
0356             return vref;
0357
0358         vref /= 1000;
0359     }
0360
0361     if (st->cmd_settings_bitmask & TI_ADS7950_CR_RANGE_5V)
0362         vref *= 2;
0363
0364     return vref;
0365 }
0366
0367 static int ti_ads7950_read_raw(struct iio_dev *indio_dev,
0368                    struct iio_chan_spec const *chan,
0369                    int *val, int *val2, long m)
0370 {
0371     struct ti_ads7950_state *st = iio_priv(indio_dev);
0372     int ret;
0373
0374     switch (m) {
0375     case IIO_CHAN_INFO_RAW:
0376         ret = ti_ads7950_scan_direct(indio_dev, chan->address);
0377         if (ret < 0)
0378             return ret;
0379
0380         if (chan->address != TI_ADS7950_EXTRACT(ret, 12, 4))
0381             return -EIO;
0382
0383         *val = TI_ADS7950_EXTRACT(ret, chan->scan_type.shift,
0384                       chan->scan_type.realbits);
0385
0386         return IIO_VAL_INT;
0387     case IIO_CHAN_INFO_SCALE:
0388         ret = ti_ads7950_get_range(st);
0389         if (ret < 0)
0390             return ret;
0391
0392         *val = ret;
0393         *val2 = (1 << chan->scan_type.realbits) - 1;
0394
0395         return IIO_VAL_FRACTIONAL;
0396     }
0397
0398     return -EINVAL;
0399 }
0400
0401 static const struct iio_info ti_ads7950_info = {
0402     .read_raw       = &ti_ads7950_read_raw,
0403     .update_scan_mode   = ti_ads7950_update_scan_mode,
0404 };
0405
0406 static void ti_ads7950_set(struct gpio_chip *chip, unsigned int offset,
0407                int value)
0408 {
0409     struct ti_ads7950_state *st = gpiochip_get_data(chip);
0410
0411     mutex_lock(&st->slock);
0412
0413     if (value)
0414         st->cmd_settings_bitmask |= BIT(offset);
0415     else
0416         st->cmd_settings_bitmask &= ~BIT(offset);
0417
0418     st->single_tx = TI_ADS7950_MAN_CMD_SETTINGS(st);
0419     spi_sync(st->spi, &st->scan_single_msg);
0420
0421     mutex_unlock(&st->slock);
0422 }
0423
0424 static int ti_ads7950_get(struct gpio_chip *chip, unsigned int offset)
0425 {
0426     struct ti_ads7950_state *st = gpiochip_get_data(chip);
0427     int ret;
0428
0429     mutex_lock(&st->slock);
0430
0431     /* If set as output, return the output */
0432     if (st->gpio_cmd_settings_bitmask & BIT(offset)) {
0433         ret = st->cmd_settings_bitmask & BIT(offset);
0434         goto out;
0435     }
0436
0437     /* GPIO data bit sets SDO bits 12-15 to GPIO input */
0438     st->cmd_settings_bitmask |= TI_ADS7950_CR_GPIO_DATA;
0439     st->single_tx = TI_ADS7950_MAN_CMD_SETTINGS(st);
0440     ret = spi_sync(st->spi, &st->scan_single_msg);
0441     if (ret)
0442         goto out;
0443
0444     ret = ((st->single_rx >> 12) & BIT(offset)) ? 1 : 0;
0445
0446     /* Revert back to original settings */
0447     st->cmd_settings_bitmask &= ~TI_ADS7950_CR_GPIO_DATA;
0448     st->single_tx = TI_ADS7950_MAN_CMD_SETTINGS(st);
0449     ret = spi_sync(st->spi, &st->scan_single_msg);
0450     if (ret)
0451         goto out;
0452
0453 out:
0454     mutex_unlock(&st->slock);
0455
0456     return ret;
0457 }
0458
0459 static int ti_ads7950_get_direction(struct gpio_chip *chip,
0460                     unsigned int offset)
0461 {
0462     struct ti_ads7950_state *st = gpiochip_get_data(chip);
0463
0464     /* Bitmask is inverted from GPIO framework 0=input/1=output */
0465     return !(st->gpio_cmd_settings_bitmask & BIT(offset));
0466 }
0467
0468 static int _ti_ads7950_set_direction(struct gpio_chip *chip, int offset,
0469                      int input)
0470 {
0471     struct ti_ads7950_state *st = gpiochip_get_data(chip);
0472     int ret = 0;
0473
0474     mutex_lock(&st->slock);
0475
0476     /* Only change direction if needed */
0477     if (input && (st->gpio_cmd_settings_bitmask & BIT(offset)))
0478         st->gpio_cmd_settings_bitmask &= ~BIT(offset);
0479     else if (!input && !(st->gpio_cmd_settings_bitmask & BIT(offset)))
0480         st->gpio_cmd_settings_bitmask |= BIT(offset);
0481     else
0482         goto out;
0483
0484     st->single_tx = TI_ADS7950_GPIO_CMD_SETTINGS(st);
0485     ret = spi_sync(st->spi, &st->scan_single_msg);
0486
0487 out:
0488     mutex_unlock(&st->slock);
0489
0490     return ret;
0491 }
0492
0493 static int ti_ads7950_direction_input(struct gpio_chip *chip,
0494                       unsigned int offset)
0495 {
0496     return _ti_ads7950_set_direction(chip, offset, 1);
0497 }
0498
0499 static int ti_ads7950_direction_output(struct gpio_chip *chip,
0500                        unsigned int offset, int value)
0501 {
0502     ti_ads7950_set(chip, offset, value);
0503
0504     return _ti_ads7950_set_direction(chip, offset, 0);
0505 }
0506
0507 static int ti_ads7950_init_hw(struct ti_ads7950_state *st)
0508 {
0509     int ret = 0;
0510
0511     mutex_lock(&st->slock);
0512
0513     /* Settings for Manual/Auto1/Auto2 commands */
0514     /* Default to 5v ref */
0515     st->cmd_settings_bitmask = TI_ADS7950_CR_RANGE_5V;
0516     st->single_tx = TI_ADS7950_MAN_CMD_SETTINGS(st);
0517     ret = spi_sync(st->spi, &st->scan_single_msg);
0518     if (ret)
0519         goto out;
0520
0521     /* Settings for GPIO command */
0522     st->gpio_cmd_settings_bitmask = 0x0;
0523     st->single_tx = TI_ADS7950_GPIO_CMD_SETTINGS(st);
0524     ret = spi_sync(st->spi, &st->scan_single_msg);
0525
0526 out:
0527     mutex_unlock(&st->slock);
0528
0529     return ret;
0530 }
0531
0532 static int ti_ads7950_probe(struct spi_device *spi)
0533 {
0534     struct ti_ads7950_state *st;
0535     struct iio_dev *indio_dev;
0536     const struct ti_ads7950_chip_info *info;
0537     int ret;
0538
0539     spi->bits_per_word = 16;
0540     spi->mode |= SPI_CS_WORD;
0541     ret = spi_setup(spi);
0542     if (ret < 0) {
0543         dev_err(&spi->dev, "Error in spi setup\n");
0544         return ret;
0545     }
0546
0547     indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
0548     if (!indio_dev)
0549         return -ENOMEM;
0550
0551     st = iio_priv(indio_dev);
0552
0553     spi_set_drvdata(spi, indio_dev);
0554
0555     st->spi = spi;
0556
0557     info = &ti_ads7950_chip_info[spi_get_device_id(spi)->driver_data];
0558
0559     indio_dev->name = spi_get_device_id(spi)->name;
0560     indio_dev->modes = INDIO_DIRECT_MODE;
0561     indio_dev->channels = info->channels;
0562     indio_dev->num_channels = info->num_channels;
0563     indio_dev->info = &ti_ads7950_info;
0564
0565     /* build spi ring message */
0566     spi_message_init(&st->ring_msg);
0567
0568     st->ring_xfer.tx_buf = &st->tx_buf[0];
0569     st->ring_xfer.rx_buf = &st->rx_buf[0];
0570     /* len will be set later */
0571
0572     spi_message_add_tail(&st->ring_xfer, &st->ring_msg);
0573
0574     /*
0575      * Setup default message. The sample is read at the end of the first
0576      * transfer, then it takes one full cycle to convert the sample and one
0577      * more cycle to send the value. The conversion process is driven by
0578      * the SPI clock, which is why we have 3 transfers. The middle one is
0579      * just dummy data sent while the chip is converting the sample that
0580      * was read at the end of the first transfer.
0581      */
0582
0583     st->scan_single_xfer[0].tx_buf = &st->single_tx;
0584     st->scan_single_xfer[0].len = 2;
0585     st->scan_single_xfer[0].cs_change = 1;
0586     st->scan_single_xfer[1].tx_buf = &st->single_tx;
0587     st->scan_single_xfer[1].len = 2;
0588     st->scan_single_xfer[1].cs_change = 1;
0589     st->scan_single_xfer[2].rx_buf = &st->single_rx;
0590     st->scan_single_xfer[2].len = 2;
0591
0592     spi_message_init_with_transfers(&st->scan_single_msg,
0593                     st->scan_single_xfer, 3);
0594
0595     /* Use hard coded value for reference voltage in ACPI case */
0596     if (ACPI_COMPANION(&spi->dev))
0597         st->vref_mv = TI_ADS7950_VA_MV_ACPI_DEFAULT;
0598
0599     mutex_init(&st->slock);
0600
0601     st->reg = devm_regulator_get(&spi->dev, "vref");
0602     if (IS_ERR(st->reg)) {
0603         ret = dev_err_probe(&spi->dev, PTR_ERR(st->reg),
0604                      "Failed to get regulator \"vref\"\n");
0605         goto error_destroy_mutex;
0606     }
0607
0608     ret = regulator_enable(st->reg);
0609     if (ret) {
0610         dev_err(&spi->dev, "Failed to enable regulator \"vref\"\n");
0611         goto error_destroy_mutex;
0612     }
0613
0614     ret = iio_triggered_buffer_setup(indio_dev, NULL,
0615                      &ti_ads7950_trigger_handler, NULL);
0616     if (ret) {
0617         dev_err(&spi->dev, "Failed to setup triggered buffer\n");
0618         goto error_disable_reg;
0619     }
0620
0621     ret = ti_ads7950_init_hw(st);
0622     if (ret) {
0623         dev_err(&spi->dev, "Failed to init adc chip\n");
0624         goto error_cleanup_ring;
0625     }
0626
0627     ret = iio_device_register(indio_dev);
0628     if (ret) {
0629         dev_err(&spi->dev, "Failed to register iio device\n");
0630         goto error_cleanup_ring;
0631     }
0632
0633     /* Add GPIO chip */
0634     st->chip.label = dev_name(&st->spi->dev);
0635     st->chip.parent = &st->spi->dev;
0636     st->chip.owner = THIS_MODULE;
0637     st->chip.base = -1;
0638     st->chip.ngpio = TI_ADS7950_NUM_GPIOS;
0639     st->chip.get_direction = ti_ads7950_get_direction;
0640     st->chip.direction_input = ti_ads7950_direction_input;
0641     st->chip.direction_output = ti_ads7950_direction_output;
0642     st->chip.get = ti_ads7950_get;
0643     st->chip.set = ti_ads7950_set;
0644
0645     ret = gpiochip_add_data(&st->chip, st);
0646     if (ret) {
0647         dev_err(&spi->dev, "Failed to init GPIOs\n");
0648         goto error_iio_device;
0649     }
0650
0651     return 0;
0652
0653 error_iio_device:
0654     iio_device_unregister(indio_dev);
0655 error_cleanup_ring:
0656     iio_triggered_buffer_cleanup(indio_dev);
0657 error_disable_reg:
0658     regulator_disable(st->reg);
0659 error_destroy_mutex:
0660     mutex_destroy(&st->slock);
0661
0662     return ret;
0663 }
0664
0665 static void ti_ads7950_remove(struct spi_device *spi)
0666 {
0667     struct iio_dev *indio_dev = spi_get_drvdata(spi);
0668     struct ti_ads7950_state *st = iio_priv(indio_dev);
0669
0670     gpiochip_remove(&st->chip);
0671     iio_device_unregister(indio_dev);
0672     iio_triggered_buffer_cleanup(indio_dev);
0673     regulator_disable(st->reg);
0674     mutex_destroy(&st->slock);
0675 }
0676
0677 static const struct spi_device_id ti_ads7950_id[] = {
0678     { "ads7950", TI_ADS7950 },
0679     { "ads7951", TI_ADS7951 },
0680     { "ads7952", TI_ADS7952 },
0681     { "ads7953", TI_ADS7953 },
0682     { "ads7954", TI_ADS7954 },
0683     { "ads7955", TI_ADS7955 },
0684     { "ads7956", TI_ADS7956 },
0685     { "ads7957", TI_ADS7957 },
0686     { "ads7958", TI_ADS7958 },
0687     { "ads7959", TI_ADS7959 },
0688     { "ads7960", TI_ADS7960 },
0689     { "ads7961", TI_ADS7961 },
0690     { }
0691 };
0692 MODULE_DEVICE_TABLE(spi, ti_ads7950_id);
0693
0694 static const struct of_device_id ads7950_of_table[] = {
0695     { .compatible = "ti,ads7950", .data = &ti_ads7950_chip_info[TI_ADS7950] },
0696     { .compatible = "ti,ads7951", .data = &ti_ads7950_chip_info[TI_ADS7951] },
0697     { .compatible = "ti,ads7952", .data = &ti_ads7950_chip_info[TI_ADS7952] },
0698     { .compatible = "ti,ads7953", .data = &ti_ads7950_chip_info[TI_ADS7953] },
0699     { .compatible = "ti,ads7954", .data = &ti_ads7950_chip_info[TI_ADS7954] },
0700     { .compatible = "ti,ads7955", .data = &ti_ads7950_chip_info[TI_ADS7955] },
0701     { .compatible = "ti,ads7956", .data = &ti_ads7950_chip_info[TI_ADS7956] },
0702     { .compatible = "ti,ads7957", .data = &ti_ads7950_chip_info[TI_ADS7957] },
0703     { .compatible = "ti,ads7958", .data = &ti_ads7950_chip_info[TI_ADS7958] },
0704     { .compatible = "ti,ads7959", .data = &ti_ads7950_chip_info[TI_ADS7959] },
0705     { .compatible = "ti,ads7960", .data = &ti_ads7950_chip_info[TI_ADS7960] },
0706     { .compatible = "ti,ads7961", .data = &ti_ads7950_chip_info[TI_ADS7961] },
0707     { },
0708 };
0709 MODULE_DEVICE_TABLE(of, ads7950_of_table);
0710
0711 static struct spi_driver ti_ads7950_driver = {
0712     .driver = {
0713         .name   = "ads7950",
0714         .of_match_table = ads7950_of_table,
0715     },
0716     .probe      = ti_ads7950_probe,
0717     .remove     = ti_ads7950_remove,
0718     .id_table   = ti_ads7950_id,
0719 };
0720 module_spi_driver(ti_ads7950_driver);
0721
0722 MODULE_AUTHOR("David Lechner <david@lechnology.com>");
0723 MODULE_DESCRIPTION("TI TI_ADS7950 ADC");
0724 MODULE_LICENSE("GPL v2");