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0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Texas Instruments ADS131E0x 4-, 6- and 8-Channel ADCs
0004  *
0005  * Copyright (c) 2020 AVL DiTEST GmbH
0006  *   Tomislav Denis <tomislav.denis@avl.com>
0007  *
0008  * Datasheet: https://www.ti.com/lit/ds/symlink/ads131e08.pdf
0009  */
0010 
0011 #include <linux/bitfield.h>
0012 #include <linux/clk.h>
0013 #include <linux/delay.h>
0014 #include <linux/module.h>
0015 
0016 #include <linux/iio/buffer.h>
0017 #include <linux/iio/iio.h>
0018 #include <linux/iio/sysfs.h>
0019 #include <linux/iio/trigger.h>
0020 #include <linux/iio/trigger_consumer.h>
0021 #include <linux/iio/triggered_buffer.h>
0022 
0023 #include <linux/regulator/consumer.h>
0024 #include <linux/spi/spi.h>
0025 
0026 #include <asm/unaligned.h>
0027 
0028 /* Commands */
0029 #define ADS131E08_CMD_RESET     0x06
0030 #define ADS131E08_CMD_START     0x08
0031 #define ADS131E08_CMD_STOP      0x0A
0032 #define ADS131E08_CMD_OFFSETCAL     0x1A
0033 #define ADS131E08_CMD_SDATAC        0x11
0034 #define ADS131E08_CMD_RDATA     0x12
0035 #define ADS131E08_CMD_RREG(r)       (BIT(5) | (r & GENMASK(4, 0)))
0036 #define ADS131E08_CMD_WREG(r)       (BIT(6) | (r & GENMASK(4, 0)))
0037 
0038 /* Registers */
0039 #define ADS131E08_ADR_CFG1R     0x01
0040 #define ADS131E08_ADR_CFG3R     0x03
0041 #define ADS131E08_ADR_CH0R      0x05
0042 
0043 /* Configuration register 1 */
0044 #define ADS131E08_CFG1R_DR_MASK     GENMASK(2, 0)
0045 
0046 /* Configuration register 3 */
0047 #define ADS131E08_CFG3R_PDB_REFBUF_MASK BIT(7)
0048 #define ADS131E08_CFG3R_VREF_4V_MASK    BIT(5)
0049 
0050 /* Channel settings register */
0051 #define ADS131E08_CHR_GAIN_MASK     GENMASK(6, 4)
0052 #define ADS131E08_CHR_MUX_MASK      GENMASK(2, 0)
0053 #define ADS131E08_CHR_PWD_MASK      BIT(7)
0054 
0055 /* ADC  misc */
0056 #define ADS131E08_DEFAULT_DATA_RATE 1
0057 #define ADS131E08_DEFAULT_PGA_GAIN  1
0058 #define ADS131E08_DEFAULT_MUX       0
0059 
0060 #define ADS131E08_VREF_2V4_mV       2400
0061 #define ADS131E08_VREF_4V_mV        4000
0062 
0063 #define ADS131E08_WAIT_RESET_CYCLES 18
0064 #define ADS131E08_WAIT_SDECODE_CYCLES   4
0065 #define ADS131E08_WAIT_OFFSETCAL_MS 153
0066 #define ADS131E08_MAX_SETTLING_TIME_MS  6
0067 
0068 #define ADS131E08_NUM_STATUS_BYTES  3
0069 #define ADS131E08_NUM_DATA_BYTES_MAX    24
0070 #define ADS131E08_NUM_DATA_BYTES(dr)    (((dr) >= 32) ? 2 : 3)
0071 #define ADS131E08_NUM_DATA_BITS(dr) (ADS131E08_NUM_DATA_BYTES(dr) * 8)
0072 #define ADS131E08_NUM_STORAGE_BYTES 4
0073 
0074 enum ads131e08_ids {
0075     ads131e04,
0076     ads131e06,
0077     ads131e08,
0078 };
0079 
0080 struct ads131e08_info {
0081     unsigned int max_channels;
0082     const char *name;
0083 };
0084 
0085 struct ads131e08_channel_config {
0086     unsigned int pga_gain;
0087     unsigned int mux;
0088 };
0089 
0090 struct ads131e08_state {
0091     const struct ads131e08_info *info;
0092     struct spi_device *spi;
0093     struct iio_trigger *trig;
0094     struct clk *adc_clk;
0095     struct regulator *vref_reg;
0096     struct ads131e08_channel_config *channel_config;
0097     unsigned int data_rate;
0098     unsigned int vref_mv;
0099     unsigned int sdecode_delay_us;
0100     unsigned int reset_delay_us;
0101     unsigned int readback_len;
0102     struct completion completion;
0103     struct {
0104         u8 data[ADS131E08_NUM_DATA_BYTES_MAX];
0105         s64 ts __aligned(8);
0106     } tmp_buf;
0107 
0108     u8 tx_buf[3] __aligned(IIO_DMA_MINALIGN);
0109     /*
0110      * Add extra one padding byte to be able to access the last channel
0111      * value using u32 pointer
0112      */
0113     u8 rx_buf[ADS131E08_NUM_STATUS_BYTES +
0114         ADS131E08_NUM_DATA_BYTES_MAX + 1];
0115 };
0116 
0117 static const struct ads131e08_info ads131e08_info_tbl[] = {
0118     [ads131e04] = {
0119         .max_channels = 4,
0120         .name = "ads131e04",
0121     },
0122     [ads131e06] = {
0123         .max_channels = 6,
0124         .name = "ads131e06",
0125     },
0126     [ads131e08] = {
0127         .max_channels = 8,
0128         .name = "ads131e08",
0129     },
0130 };
0131 
0132 struct ads131e08_data_rate_desc {
0133     unsigned int rate;  /* data rate in kSPS */
0134     u8 reg;             /* reg value */
0135 };
0136 
0137 static const struct ads131e08_data_rate_desc ads131e08_data_rate_tbl[] = {
0138     { .rate = 64,   .reg = 0x00 },
0139     { .rate = 32,   .reg = 0x01 },
0140     { .rate = 16,   .reg = 0x02 },
0141     { .rate = 8,    .reg = 0x03 },
0142     { .rate = 4,    .reg = 0x04 },
0143     { .rate = 2,    .reg = 0x05 },
0144     { .rate = 1,    .reg = 0x06 },
0145 };
0146 
0147 struct ads131e08_pga_gain_desc {
0148     unsigned int gain;  /* PGA gain value */
0149     u8 reg;             /* field value */
0150 };
0151 
0152 static const struct ads131e08_pga_gain_desc ads131e08_pga_gain_tbl[] = {
0153     { .gain = 1,   .reg = 0x01 },
0154     { .gain = 2,   .reg = 0x02 },
0155     { .gain = 4,   .reg = 0x04 },
0156     { .gain = 8,   .reg = 0x05 },
0157     { .gain = 12,  .reg = 0x06 },
0158 };
0159 
0160 static const u8 ads131e08_valid_channel_mux_values[] = { 0, 1, 3, 4 };
0161 
0162 static int ads131e08_exec_cmd(struct ads131e08_state *st, u8 cmd)
0163 {
0164     int ret;
0165 
0166     ret = spi_write_then_read(st->spi, &cmd, 1, NULL, 0);
0167     if (ret)
0168         dev_err(&st->spi->dev, "Exec cmd(%02x) failed\n", cmd);
0169 
0170     return ret;
0171 }
0172 
0173 static int ads131e08_read_reg(struct ads131e08_state *st, u8 reg)
0174 {
0175     int ret;
0176     struct spi_transfer transfer[] = {
0177         {
0178             .tx_buf = &st->tx_buf,
0179             .len = 2,
0180             .delay = {
0181                 .value = st->sdecode_delay_us,
0182                 .unit = SPI_DELAY_UNIT_USECS,
0183             },
0184         }, {
0185             .rx_buf = &st->rx_buf,
0186             .len = 1,
0187         },
0188     };
0189 
0190     st->tx_buf[0] = ADS131E08_CMD_RREG(reg);
0191     st->tx_buf[1] = 0;
0192 
0193     ret = spi_sync_transfer(st->spi, transfer, ARRAY_SIZE(transfer));
0194     if (ret) {
0195         dev_err(&st->spi->dev, "Read register failed\n");
0196         return ret;
0197     }
0198 
0199     return st->rx_buf[0];
0200 }
0201 
0202 static int ads131e08_write_reg(struct ads131e08_state *st, u8 reg, u8 value)
0203 {
0204     int ret;
0205     struct spi_transfer transfer[] = {
0206         {
0207             .tx_buf = &st->tx_buf,
0208             .len = 3,
0209             .delay = {
0210                 .value = st->sdecode_delay_us,
0211                 .unit = SPI_DELAY_UNIT_USECS,
0212             },
0213         }
0214     };
0215 
0216     st->tx_buf[0] = ADS131E08_CMD_WREG(reg);
0217     st->tx_buf[1] = 0;
0218     st->tx_buf[2] = value;
0219 
0220     ret = spi_sync_transfer(st->spi, transfer, ARRAY_SIZE(transfer));
0221     if (ret)
0222         dev_err(&st->spi->dev, "Write register failed\n");
0223 
0224     return ret;
0225 }
0226 
0227 static int ads131e08_read_data(struct ads131e08_state *st, int rx_len)
0228 {
0229     int ret;
0230     struct spi_transfer transfer[] = {
0231         {
0232             .tx_buf = &st->tx_buf,
0233             .len = 1,
0234         }, {
0235             .rx_buf = &st->rx_buf,
0236             .len = rx_len,
0237         },
0238     };
0239 
0240     st->tx_buf[0] = ADS131E08_CMD_RDATA;
0241 
0242     ret = spi_sync_transfer(st->spi, transfer, ARRAY_SIZE(transfer));
0243     if (ret)
0244         dev_err(&st->spi->dev, "Read data failed\n");
0245 
0246     return ret;
0247 }
0248 
0249 static int ads131e08_set_data_rate(struct ads131e08_state *st, int data_rate)
0250 {
0251     int i, reg, ret;
0252 
0253     for (i = 0; i < ARRAY_SIZE(ads131e08_data_rate_tbl); i++) {
0254         if (ads131e08_data_rate_tbl[i].rate == data_rate)
0255             break;
0256     }
0257 
0258     if (i == ARRAY_SIZE(ads131e08_data_rate_tbl)) {
0259         dev_err(&st->spi->dev, "invalid data rate value\n");
0260         return -EINVAL;
0261     }
0262 
0263     reg = ads131e08_read_reg(st, ADS131E08_ADR_CFG1R);
0264     if (reg < 0)
0265         return reg;
0266 
0267     reg &= ~ADS131E08_CFG1R_DR_MASK;
0268     reg |= FIELD_PREP(ADS131E08_CFG1R_DR_MASK,
0269         ads131e08_data_rate_tbl[i].reg);
0270 
0271     ret = ads131e08_write_reg(st, ADS131E08_ADR_CFG1R, reg);
0272     if (ret)
0273         return ret;
0274 
0275     st->data_rate = data_rate;
0276     st->readback_len = ADS131E08_NUM_STATUS_BYTES +
0277         ADS131E08_NUM_DATA_BYTES(st->data_rate) *
0278         st->info->max_channels;
0279 
0280     return 0;
0281 }
0282 
0283 static int ads131e08_pga_gain_to_field_value(struct ads131e08_state *st,
0284     unsigned int pga_gain)
0285 {
0286     int i;
0287 
0288     for (i = 0; i < ARRAY_SIZE(ads131e08_pga_gain_tbl); i++) {
0289         if (ads131e08_pga_gain_tbl[i].gain == pga_gain)
0290             break;
0291     }
0292 
0293     if (i == ARRAY_SIZE(ads131e08_pga_gain_tbl)) {
0294         dev_err(&st->spi->dev, "invalid PGA gain value\n");
0295         return -EINVAL;
0296     }
0297 
0298     return ads131e08_pga_gain_tbl[i].reg;
0299 }
0300 
0301 static int ads131e08_set_pga_gain(struct ads131e08_state *st,
0302     unsigned int channel, unsigned int pga_gain)
0303 {
0304     int field_value, reg;
0305 
0306     field_value = ads131e08_pga_gain_to_field_value(st, pga_gain);
0307     if (field_value < 0)
0308         return field_value;
0309 
0310     reg = ads131e08_read_reg(st, ADS131E08_ADR_CH0R + channel);
0311     if (reg < 0)
0312         return reg;
0313 
0314     reg &= ~ADS131E08_CHR_GAIN_MASK;
0315     reg |= FIELD_PREP(ADS131E08_CHR_GAIN_MASK, field_value);
0316 
0317     return ads131e08_write_reg(st, ADS131E08_ADR_CH0R + channel, reg);
0318 }
0319 
0320 static int ads131e08_validate_channel_mux(struct ads131e08_state *st,
0321     unsigned int mux)
0322 {
0323     int i;
0324 
0325     for (i = 0; i < ARRAY_SIZE(ads131e08_valid_channel_mux_values); i++) {
0326         if (ads131e08_valid_channel_mux_values[i] == mux)
0327             break;
0328     }
0329 
0330     if (i == ARRAY_SIZE(ads131e08_valid_channel_mux_values)) {
0331         dev_err(&st->spi->dev, "invalid channel mux value\n");
0332         return -EINVAL;
0333     }
0334 
0335     return 0;
0336 }
0337 
0338 static int ads131e08_set_channel_mux(struct ads131e08_state *st,
0339     unsigned int channel, unsigned int mux)
0340 {
0341     int reg;
0342 
0343     reg = ads131e08_read_reg(st, ADS131E08_ADR_CH0R + channel);
0344     if (reg < 0)
0345         return reg;
0346 
0347     reg &= ~ADS131E08_CHR_MUX_MASK;
0348     reg |= FIELD_PREP(ADS131E08_CHR_MUX_MASK, mux);
0349 
0350     return ads131e08_write_reg(st, ADS131E08_ADR_CH0R + channel, reg);
0351 }
0352 
0353 static int ads131e08_power_down_channel(struct ads131e08_state *st,
0354     unsigned int channel, bool value)
0355 {
0356     int reg;
0357 
0358     reg = ads131e08_read_reg(st, ADS131E08_ADR_CH0R + channel);
0359     if (reg < 0)
0360         return reg;
0361 
0362     reg &= ~ADS131E08_CHR_PWD_MASK;
0363     reg |= FIELD_PREP(ADS131E08_CHR_PWD_MASK, value);
0364 
0365     return ads131e08_write_reg(st, ADS131E08_ADR_CH0R + channel, reg);
0366 }
0367 
0368 static int ads131e08_config_reference_voltage(struct ads131e08_state *st)
0369 {
0370     int reg;
0371 
0372     reg = ads131e08_read_reg(st, ADS131E08_ADR_CFG3R);
0373     if (reg < 0)
0374         return reg;
0375 
0376     reg &= ~ADS131E08_CFG3R_PDB_REFBUF_MASK;
0377     if (!st->vref_reg) {
0378         reg |= FIELD_PREP(ADS131E08_CFG3R_PDB_REFBUF_MASK, 1);
0379         reg &= ~ADS131E08_CFG3R_VREF_4V_MASK;
0380         reg |= FIELD_PREP(ADS131E08_CFG3R_VREF_4V_MASK,
0381             st->vref_mv == ADS131E08_VREF_4V_mV);
0382     }
0383 
0384     return ads131e08_write_reg(st, ADS131E08_ADR_CFG3R, reg);
0385 }
0386 
0387 static int ads131e08_initial_config(struct iio_dev *indio_dev)
0388 {
0389     const struct iio_chan_spec *channel = indio_dev->channels;
0390     struct ads131e08_state *st = iio_priv(indio_dev);
0391     unsigned long active_channels = 0;
0392     int ret, i;
0393 
0394     ret = ads131e08_exec_cmd(st, ADS131E08_CMD_RESET);
0395     if (ret)
0396         return ret;
0397 
0398     udelay(st->reset_delay_us);
0399 
0400     /* Disable read data in continuous mode (enabled by default) */
0401     ret = ads131e08_exec_cmd(st, ADS131E08_CMD_SDATAC);
0402     if (ret)
0403         return ret;
0404 
0405     ret = ads131e08_set_data_rate(st, ADS131E08_DEFAULT_DATA_RATE);
0406     if (ret)
0407         return ret;
0408 
0409     ret = ads131e08_config_reference_voltage(st);
0410     if (ret)
0411         return ret;
0412 
0413     for (i = 0;  i < indio_dev->num_channels; i++) {
0414         ret = ads131e08_set_pga_gain(st, channel->channel,
0415             st->channel_config[i].pga_gain);
0416         if (ret)
0417             return ret;
0418 
0419         ret = ads131e08_set_channel_mux(st, channel->channel,
0420             st->channel_config[i].mux);
0421         if (ret)
0422             return ret;
0423 
0424         active_channels |= BIT(channel->channel);
0425         channel++;
0426     }
0427 
0428     /* Power down unused channels */
0429     for_each_clear_bit(i, &active_channels, st->info->max_channels) {
0430         ret = ads131e08_power_down_channel(st, i, true);
0431         if (ret)
0432             return ret;
0433     }
0434 
0435     /* Request channel offset calibration */
0436     ret = ads131e08_exec_cmd(st, ADS131E08_CMD_OFFSETCAL);
0437     if (ret)
0438         return ret;
0439 
0440     /*
0441      * Channel offset calibration is triggered with the first START
0442      * command. Since calibration takes more time than settling operation,
0443      * this causes timeout error when command START is sent first
0444      * time (e.g. first call of the ads131e08_read_direct method).
0445      * To avoid this problem offset calibration is triggered here.
0446      */
0447     ret = ads131e08_exec_cmd(st, ADS131E08_CMD_START);
0448     if (ret)
0449         return ret;
0450 
0451     msleep(ADS131E08_WAIT_OFFSETCAL_MS);
0452 
0453     return ads131e08_exec_cmd(st, ADS131E08_CMD_STOP);
0454 }
0455 
0456 static int ads131e08_pool_data(struct ads131e08_state *st)
0457 {
0458     unsigned long timeout;
0459     int ret;
0460 
0461     reinit_completion(&st->completion);
0462 
0463     ret = ads131e08_exec_cmd(st, ADS131E08_CMD_START);
0464     if (ret)
0465         return ret;
0466 
0467     timeout = msecs_to_jiffies(ADS131E08_MAX_SETTLING_TIME_MS);
0468     ret = wait_for_completion_timeout(&st->completion, timeout);
0469     if (!ret)
0470         return -ETIMEDOUT;
0471 
0472     ret = ads131e08_read_data(st, st->readback_len);
0473     if (ret)
0474         return ret;
0475 
0476     return ads131e08_exec_cmd(st, ADS131E08_CMD_STOP);
0477 }
0478 
0479 static int ads131e08_read_direct(struct iio_dev *indio_dev,
0480     struct iio_chan_spec const *channel, int *value)
0481 {
0482     struct ads131e08_state *st = iio_priv(indio_dev);
0483     u8 num_bits, *src;
0484     int ret;
0485 
0486     ret = ads131e08_pool_data(st);
0487     if (ret)
0488         return ret;
0489 
0490     src = st->rx_buf + ADS131E08_NUM_STATUS_BYTES +
0491         channel->channel * ADS131E08_NUM_DATA_BYTES(st->data_rate);
0492 
0493     num_bits = ADS131E08_NUM_DATA_BITS(st->data_rate);
0494     *value = sign_extend32(get_unaligned_be32(src) >> (32 - num_bits), num_bits - 1);
0495 
0496     return 0;
0497 }
0498 
0499 static int ads131e08_read_raw(struct iio_dev *indio_dev,
0500     struct iio_chan_spec const *channel, int *value,
0501     int *value2, long mask)
0502 {
0503     struct ads131e08_state *st = iio_priv(indio_dev);
0504     int ret;
0505 
0506     switch (mask) {
0507     case IIO_CHAN_INFO_RAW:
0508         ret = iio_device_claim_direct_mode(indio_dev);
0509         if (ret)
0510             return ret;
0511 
0512         ret = ads131e08_read_direct(indio_dev, channel, value);
0513         iio_device_release_direct_mode(indio_dev);
0514         if (ret)
0515             return ret;
0516 
0517         return IIO_VAL_INT;
0518 
0519     case IIO_CHAN_INFO_SCALE:
0520         if (st->vref_reg) {
0521             ret = regulator_get_voltage(st->vref_reg);
0522             if (ret < 0)
0523                 return ret;
0524 
0525             *value = ret / 1000;
0526         } else {
0527             *value = st->vref_mv;
0528         }
0529 
0530         *value /= st->channel_config[channel->address].pga_gain;
0531         *value2 = ADS131E08_NUM_DATA_BITS(st->data_rate) - 1;
0532 
0533         return IIO_VAL_FRACTIONAL_LOG2;
0534 
0535     case IIO_CHAN_INFO_SAMP_FREQ:
0536         *value = st->data_rate;
0537 
0538         return IIO_VAL_INT;
0539 
0540     default:
0541         return -EINVAL;
0542     }
0543 }
0544 
0545 static int ads131e08_write_raw(struct iio_dev *indio_dev,
0546     struct iio_chan_spec const *channel, int value,
0547     int value2, long mask)
0548 {
0549     struct ads131e08_state *st = iio_priv(indio_dev);
0550     int ret;
0551 
0552     switch (mask) {
0553     case IIO_CHAN_INFO_SAMP_FREQ:
0554         ret = iio_device_claim_direct_mode(indio_dev);
0555         if (ret)
0556             return ret;
0557 
0558         ret = ads131e08_set_data_rate(st, value);
0559         iio_device_release_direct_mode(indio_dev);
0560         return ret;
0561 
0562     default:
0563         return -EINVAL;
0564     }
0565 }
0566 
0567 static IIO_CONST_ATTR_SAMP_FREQ_AVAIL("1 2 4 8 16 32 64");
0568 
0569 static struct attribute *ads131e08_attributes[] = {
0570     &iio_const_attr_sampling_frequency_available.dev_attr.attr,
0571     NULL
0572 };
0573 
0574 static const struct attribute_group ads131e08_attribute_group = {
0575     .attrs = ads131e08_attributes,
0576 };
0577 
0578 static int ads131e08_debugfs_reg_access(struct iio_dev *indio_dev,
0579     unsigned int reg, unsigned int writeval, unsigned int *readval)
0580 {
0581     struct ads131e08_state *st = iio_priv(indio_dev);
0582 
0583     if (readval) {
0584         int ret = ads131e08_read_reg(st, reg);
0585         *readval = ret;
0586         return ret;
0587     }
0588 
0589     return ads131e08_write_reg(st, reg, writeval);
0590 }
0591 
0592 static const struct iio_info ads131e08_iio_info = {
0593     .read_raw = ads131e08_read_raw,
0594     .write_raw = ads131e08_write_raw,
0595     .attrs = &ads131e08_attribute_group,
0596     .debugfs_reg_access = &ads131e08_debugfs_reg_access,
0597 };
0598 
0599 static int ads131e08_set_trigger_state(struct iio_trigger *trig, bool state)
0600 {
0601     struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
0602     struct ads131e08_state *st = iio_priv(indio_dev);
0603     u8 cmd = state ? ADS131E08_CMD_START : ADS131E08_CMD_STOP;
0604 
0605     return ads131e08_exec_cmd(st, cmd);
0606 }
0607 
0608 static const struct iio_trigger_ops ads131e08_trigger_ops = {
0609     .set_trigger_state = &ads131e08_set_trigger_state,
0610     .validate_device = &iio_trigger_validate_own_device,
0611 };
0612 
0613 static irqreturn_t ads131e08_trigger_handler(int irq, void *private)
0614 {
0615     struct iio_poll_func *pf = private;
0616     struct iio_dev *indio_dev = pf->indio_dev;
0617     struct ads131e08_state *st = iio_priv(indio_dev);
0618     unsigned int chn, i = 0;
0619     u8 *src, *dest;
0620     int ret;
0621 
0622     /*
0623      * The number of data bits per channel depends on the data rate.
0624      * For 32 and 64 ksps data rates, number of data bits per channel
0625      * is 16. This case is not compliant with used (fixed) scan element
0626      * type (be:s24/32>>8). So we use a little tweak to pack properly
0627      * 16 bits of data into the buffer.
0628      */
0629     unsigned int num_bytes = ADS131E08_NUM_DATA_BYTES(st->data_rate);
0630     u8 tweek_offset = num_bytes == 2 ? 1 : 0;
0631 
0632     if (iio_trigger_using_own(indio_dev))
0633         ret = ads131e08_read_data(st, st->readback_len);
0634     else
0635         ret = ads131e08_pool_data(st);
0636 
0637     if (ret)
0638         goto out;
0639 
0640     for_each_set_bit(chn, indio_dev->active_scan_mask, indio_dev->masklength) {
0641         src = st->rx_buf + ADS131E08_NUM_STATUS_BYTES + chn * num_bytes;
0642         dest = st->tmp_buf.data + i * ADS131E08_NUM_STORAGE_BYTES;
0643 
0644         /*
0645          * Tweek offset is 0:
0646          * +---+---+---+---+
0647          * |D0 |D1 |D2 | X | (3 data bytes)
0648          * +---+---+---+---+
0649          *  a+0 a+1 a+2 a+3
0650          *
0651          * Tweek offset is 1:
0652          * +---+---+---+---+
0653          * |P0 |D0 |D1 | X | (one padding byte and 2 data bytes)
0654          * +---+---+---+---+
0655          *  a+0 a+1 a+2 a+3
0656          */
0657         memcpy(dest + tweek_offset, src, num_bytes);
0658 
0659         /*
0660          * Data conversion from 16 bits of data to 24 bits of data
0661          * is done by sign extension (properly filling padding byte).
0662          */
0663         if (tweek_offset)
0664             *dest = *src & BIT(7) ? 0xff : 0x00;
0665 
0666         i++;
0667     }
0668 
0669     iio_push_to_buffers_with_timestamp(indio_dev, st->tmp_buf.data,
0670         iio_get_time_ns(indio_dev));
0671 
0672 out:
0673     iio_trigger_notify_done(indio_dev->trig);
0674 
0675     return IRQ_HANDLED;
0676 }
0677 
0678 static irqreturn_t ads131e08_interrupt(int irq, void *private)
0679 {
0680     struct iio_dev *indio_dev = private;
0681     struct ads131e08_state *st = iio_priv(indio_dev);
0682 
0683     if (iio_buffer_enabled(indio_dev) && iio_trigger_using_own(indio_dev))
0684         iio_trigger_poll(st->trig);
0685     else
0686         complete(&st->completion);
0687 
0688     return IRQ_HANDLED;
0689 }
0690 
0691 static int ads131e08_alloc_channels(struct iio_dev *indio_dev)
0692 {
0693     struct ads131e08_state *st = iio_priv(indio_dev);
0694     struct ads131e08_channel_config *channel_config;
0695     struct device *dev = &st->spi->dev;
0696     struct iio_chan_spec *channels;
0697     struct fwnode_handle *node;
0698     unsigned int channel, tmp;
0699     int num_channels, i, ret;
0700 
0701     ret = device_property_read_u32(dev, "ti,vref-internal", &tmp);
0702     if (ret)
0703         tmp = 0;
0704 
0705     switch (tmp) {
0706     case 0:
0707         st->vref_mv = ADS131E08_VREF_2V4_mV;
0708         break;
0709     case 1:
0710         st->vref_mv = ADS131E08_VREF_4V_mV;
0711         break;
0712     default:
0713         dev_err(&st->spi->dev, "invalid internal voltage reference\n");
0714         return -EINVAL;
0715     }
0716 
0717     num_channels = device_get_child_node_count(dev);
0718     if (num_channels == 0) {
0719         dev_err(&st->spi->dev, "no channel children\n");
0720         return -ENODEV;
0721     }
0722 
0723     if (num_channels > st->info->max_channels) {
0724         dev_err(&st->spi->dev, "num of channel children out of range\n");
0725         return -EINVAL;
0726     }
0727 
0728     channels = devm_kcalloc(&st->spi->dev, num_channels,
0729         sizeof(*channels), GFP_KERNEL);
0730     if (!channels)
0731         return -ENOMEM;
0732 
0733     channel_config = devm_kcalloc(&st->spi->dev, num_channels,
0734         sizeof(*channel_config), GFP_KERNEL);
0735     if (!channel_config)
0736         return -ENOMEM;
0737 
0738     i = 0;
0739     device_for_each_child_node(dev, node) {
0740         ret = fwnode_property_read_u32(node, "reg", &channel);
0741         if (ret)
0742             goto err_child_out;
0743 
0744         ret = fwnode_property_read_u32(node, "ti,gain", &tmp);
0745         if (ret) {
0746             channel_config[i].pga_gain = ADS131E08_DEFAULT_PGA_GAIN;
0747         } else {
0748             ret = ads131e08_pga_gain_to_field_value(st, tmp);
0749             if (ret < 0)
0750                 goto err_child_out;
0751 
0752             channel_config[i].pga_gain = tmp;
0753         }
0754 
0755         ret = fwnode_property_read_u32(node, "ti,mux", &tmp);
0756         if (ret) {
0757             channel_config[i].mux = ADS131E08_DEFAULT_MUX;
0758         } else {
0759             ret = ads131e08_validate_channel_mux(st, tmp);
0760             if (ret)
0761                 goto err_child_out;
0762 
0763             channel_config[i].mux = tmp;
0764         }
0765 
0766         channels[i].type = IIO_VOLTAGE;
0767         channels[i].indexed = 1;
0768         channels[i].channel = channel;
0769         channels[i].address = i;
0770         channels[i].info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
0771                         BIT(IIO_CHAN_INFO_SCALE);
0772         channels[i].info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SAMP_FREQ);
0773         channels[i].scan_index = channel;
0774         channels[i].scan_type.sign = 's';
0775         channels[i].scan_type.realbits = 24;
0776         channels[i].scan_type.storagebits = 32;
0777         channels[i].scan_type.shift = 8;
0778         channels[i].scan_type.endianness = IIO_BE;
0779         i++;
0780     }
0781 
0782     indio_dev->channels = channels;
0783     indio_dev->num_channels = num_channels;
0784     st->channel_config = channel_config;
0785 
0786     return 0;
0787 
0788 err_child_out:
0789     fwnode_handle_put(node);
0790     return ret;
0791 }
0792 
0793 static void ads131e08_regulator_disable(void *data)
0794 {
0795     struct ads131e08_state *st = data;
0796 
0797     regulator_disable(st->vref_reg);
0798 }
0799 
0800 static void ads131e08_clk_disable(void *data)
0801 {
0802     struct ads131e08_state *st = data;
0803 
0804     clk_disable_unprepare(st->adc_clk);
0805 }
0806 
0807 static int ads131e08_probe(struct spi_device *spi)
0808 {
0809     const struct ads131e08_info *info;
0810     struct ads131e08_state *st;
0811     struct iio_dev *indio_dev;
0812     unsigned long adc_clk_hz;
0813     unsigned long adc_clk_ns;
0814     int ret;
0815 
0816     info = device_get_match_data(&spi->dev);
0817     if (!info) {
0818         dev_err(&spi->dev, "failed to get match data\n");
0819         return -ENODEV;
0820     }
0821 
0822     indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
0823     if (!indio_dev) {
0824         dev_err(&spi->dev, "failed to allocate IIO device\n");
0825         return -ENOMEM;
0826     }
0827 
0828     st = iio_priv(indio_dev);
0829     st->info = info;
0830     st->spi = spi;
0831 
0832     ret = ads131e08_alloc_channels(indio_dev);
0833     if (ret)
0834         return ret;
0835 
0836     indio_dev->name = st->info->name;
0837     indio_dev->info = &ads131e08_iio_info;
0838     indio_dev->modes = INDIO_DIRECT_MODE;
0839 
0840     init_completion(&st->completion);
0841 
0842     if (spi->irq) {
0843         ret = devm_request_irq(&spi->dev, spi->irq,
0844             ads131e08_interrupt,
0845             IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
0846             spi->dev.driver->name, indio_dev);
0847         if (ret)
0848             return dev_err_probe(&spi->dev, ret,
0849                          "request irq failed\n");
0850     } else {
0851         dev_err(&spi->dev, "data ready IRQ missing\n");
0852         return -ENODEV;
0853     }
0854 
0855     st->trig = devm_iio_trigger_alloc(&spi->dev, "%s-dev%d",
0856         indio_dev->name, iio_device_id(indio_dev));
0857     if (!st->trig) {
0858         dev_err(&spi->dev, "failed to allocate IIO trigger\n");
0859         return -ENOMEM;
0860     }
0861 
0862     st->trig->ops = &ads131e08_trigger_ops;
0863     st->trig->dev.parent = &spi->dev;
0864     iio_trigger_set_drvdata(st->trig, indio_dev);
0865     ret = devm_iio_trigger_register(&spi->dev, st->trig);
0866     if (ret) {
0867         dev_err(&spi->dev, "failed to register IIO trigger\n");
0868         return -ENOMEM;
0869     }
0870 
0871     indio_dev->trig = iio_trigger_get(st->trig);
0872 
0873     ret = devm_iio_triggered_buffer_setup(&spi->dev, indio_dev,
0874         NULL, &ads131e08_trigger_handler, NULL);
0875     if (ret) {
0876         dev_err(&spi->dev, "failed to setup IIO buffer\n");
0877         return ret;
0878     }
0879 
0880     st->vref_reg = devm_regulator_get_optional(&spi->dev, "vref");
0881     if (!IS_ERR(st->vref_reg)) {
0882         ret = regulator_enable(st->vref_reg);
0883         if (ret) {
0884             dev_err(&spi->dev,
0885                 "failed to enable external vref supply\n");
0886             return ret;
0887         }
0888 
0889         ret = devm_add_action_or_reset(&spi->dev, ads131e08_regulator_disable, st);
0890         if (ret)
0891             return ret;
0892     } else {
0893         if (PTR_ERR(st->vref_reg) != -ENODEV)
0894             return PTR_ERR(st->vref_reg);
0895 
0896         st->vref_reg = NULL;
0897     }
0898 
0899     st->adc_clk = devm_clk_get(&spi->dev, "adc-clk");
0900     if (IS_ERR(st->adc_clk))
0901         return dev_err_probe(&spi->dev, PTR_ERR(st->adc_clk),
0902                      "failed to get the ADC clock\n");
0903 
0904     ret = clk_prepare_enable(st->adc_clk);
0905     if (ret) {
0906         dev_err(&spi->dev, "failed to prepare/enable the ADC clock\n");
0907         return ret;
0908     }
0909 
0910     ret = devm_add_action_or_reset(&spi->dev, ads131e08_clk_disable, st);
0911     if (ret)
0912         return ret;
0913 
0914     adc_clk_hz = clk_get_rate(st->adc_clk);
0915     if (!adc_clk_hz) {
0916         dev_err(&spi->dev, "failed to get the ADC clock rate\n");
0917         return  -EINVAL;
0918     }
0919 
0920     adc_clk_ns = NSEC_PER_SEC / adc_clk_hz;
0921     st->sdecode_delay_us = DIV_ROUND_UP(
0922         ADS131E08_WAIT_SDECODE_CYCLES * adc_clk_ns, NSEC_PER_USEC);
0923     st->reset_delay_us = DIV_ROUND_UP(
0924         ADS131E08_WAIT_RESET_CYCLES * adc_clk_ns, NSEC_PER_USEC);
0925 
0926     ret = ads131e08_initial_config(indio_dev);
0927     if (ret) {
0928         dev_err(&spi->dev, "initial configuration failed\n");
0929         return ret;
0930     }
0931 
0932     return devm_iio_device_register(&spi->dev, indio_dev);
0933 }
0934 
0935 static const struct of_device_id ads131e08_of_match[] = {
0936     { .compatible = "ti,ads131e04",
0937       .data = &ads131e08_info_tbl[ads131e04], },
0938     { .compatible = "ti,ads131e06",
0939       .data = &ads131e08_info_tbl[ads131e06], },
0940     { .compatible = "ti,ads131e08",
0941       .data = &ads131e08_info_tbl[ads131e08], },
0942     {}
0943 };
0944 MODULE_DEVICE_TABLE(of, ads131e08_of_match);
0945 
0946 static struct spi_driver ads131e08_driver = {
0947     .driver = {
0948         .name = "ads131e08",
0949         .of_match_table = ads131e08_of_match,
0950     },
0951     .probe = ads131e08_probe,
0952 };
0953 module_spi_driver(ads131e08_driver);
0954 
0955 MODULE_AUTHOR("Tomislav Denis <tomislav.denis@avl.com>");
0956 MODULE_DESCRIPTION("Driver for ADS131E0x ADC family");
0957 MODULE_LICENSE("GPL v2");
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