iio/adc/ti-ads124s08.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /* TI ADS124S0X chip family driver
0003  * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/
0004  */
0005
0006 #include <linux/err.h>
0007 #include <linux/delay.h>
0008 #include <linux/device.h>
0009 #include <linux/kernel.h>
0010 #include <linux/module.h>
0011 #include <linux/mod_devicetable.h>
0012 #include <linux/slab.h>
0013 #include <linux/sysfs.h>
0014
0015 #include <linux/gpio/consumer.h>
0016 #include <linux/spi/spi.h>
0017
0018 #include <linux/iio/iio.h>
0019 #include <linux/iio/buffer.h>
0020 #include <linux/iio/trigger_consumer.h>
0021 #include <linux/iio/triggered_buffer.h>
0022 #include <linux/iio/sysfs.h>
0023
0024 #include <asm/unaligned.h>
0025
0026 /* Commands */
0027 #define ADS124S08_CMD_NOP   0x00
0028 #define ADS124S08_CMD_WAKEUP    0x02
0029 #define ADS124S08_CMD_PWRDWN    0x04
0030 #define ADS124S08_CMD_RESET 0x06
0031 #define ADS124S08_CMD_START 0x08
0032 #define ADS124S08_CMD_STOP  0x0a
0033 #define ADS124S08_CMD_SYOCAL    0x16
0034 #define ADS124S08_CMD_SYGCAL    0x17
0035 #define ADS124S08_CMD_SFOCAL    0x19
0036 #define ADS124S08_CMD_RDATA 0x12
0037 #define ADS124S08_CMD_RREG  0x20
0038 #define ADS124S08_CMD_WREG  0x40
0039
0040 /* Registers */
0041 #define ADS124S08_ID_REG    0x00
0042 #define ADS124S08_STATUS    0x01
0043 #define ADS124S08_INPUT_MUX 0x02
0044 #define ADS124S08_PGA       0x03
0045 #define ADS124S08_DATA_RATE 0x04
0046 #define ADS124S08_REF       0x05
0047 #define ADS124S08_IDACMAG   0x06
0048 #define ADS124S08_IDACMUX   0x07
0049 #define ADS124S08_VBIAS     0x08
0050 #define ADS124S08_SYS       0x09
0051 #define ADS124S08_OFCAL0    0x0a
0052 #define ADS124S08_OFCAL1    0x0b
0053 #define ADS124S08_OFCAL2    0x0c
0054 #define ADS124S08_FSCAL0    0x0d
0055 #define ADS124S08_FSCAL1    0x0e
0056 #define ADS124S08_FSCAL2    0x0f
0057 #define ADS124S08_GPIODAT   0x10
0058 #define ADS124S08_GPIOCON   0x11
0059
0060 /* ADS124S0x common channels */
0061 #define ADS124S08_AIN0      0x00
0062 #define ADS124S08_AIN1      0x01
0063 #define ADS124S08_AIN2      0x02
0064 #define ADS124S08_AIN3      0x03
0065 #define ADS124S08_AIN4      0x04
0066 #define ADS124S08_AIN5      0x05
0067 #define ADS124S08_AINCOM    0x0c
0068 /* ADS124S08 only channels */
0069 #define ADS124S08_AIN6      0x06
0070 #define ADS124S08_AIN7      0x07
0071 #define ADS124S08_AIN8      0x08
0072 #define ADS124S08_AIN9      0x09
0073 #define ADS124S08_AIN10     0x0a
0074 #define ADS124S08_AIN11     0x0b
0075 #define ADS124S08_MAX_CHANNELS  12
0076
0077 #define ADS124S08_POS_MUX_SHIFT 0x04
0078 #define ADS124S08_INT_REF       0x09
0079
0080 #define ADS124S08_START_REG_MASK    0x1f
0081 #define ADS124S08_NUM_BYTES_MASK    0x1f
0082
0083 #define ADS124S08_START_CONV    0x01
0084 #define ADS124S08_STOP_CONV 0x00
0085
0086 enum ads124s_id {
0087     ADS124S08_ID,
0088     ADS124S06_ID,
0089 };
0090
0091 struct ads124s_chip_info {
0092     const struct iio_chan_spec *channels;
0093     unsigned int num_channels;
0094 };
0095
0096 struct ads124s_private {
0097     const struct ads124s_chip_info  *chip_info;
0098     struct gpio_desc *reset_gpio;
0099     struct spi_device *spi;
0100     struct mutex lock;
0101     /*
0102      * Used to correctly align data.
0103      * Ensure timestamp is naturally aligned.
0104      * Note that the full buffer length may not be needed if not
0105      * all channels are enabled, as long as the alignment of the
0106      * timestamp is maintained.
0107      */
0108     u32 buffer[ADS124S08_MAX_CHANNELS + sizeof(s64)/sizeof(u32)] __aligned(8);
0109     u8 data[5] __aligned(IIO_DMA_MINALIGN);
0110 };
0111
0112 #define ADS124S08_CHAN(index)                   \
0113 {                               \
0114     .type = IIO_VOLTAGE,                    \
0115     .indexed = 1,                       \
0116     .channel = index,                   \
0117     .info_mask_separate = BIT(IIO_CHAN_INFO_RAW),       \
0118     .scan_index = index,                    \
0119     .scan_type = {                      \
0120         .sign = 'u',                    \
0121         .realbits = 32,                 \
0122         .storagebits = 32,              \
0123     },                          \
0124 }
0125
0126 static const struct iio_chan_spec ads124s06_channels[] = {
0127     ADS124S08_CHAN(0),
0128     ADS124S08_CHAN(1),
0129     ADS124S08_CHAN(2),
0130     ADS124S08_CHAN(3),
0131     ADS124S08_CHAN(4),
0132     ADS124S08_CHAN(5),
0133 };
0134
0135 static const struct iio_chan_spec ads124s08_channels[] = {
0136     ADS124S08_CHAN(0),
0137     ADS124S08_CHAN(1),
0138     ADS124S08_CHAN(2),
0139     ADS124S08_CHAN(3),
0140     ADS124S08_CHAN(4),
0141     ADS124S08_CHAN(5),
0142     ADS124S08_CHAN(6),
0143     ADS124S08_CHAN(7),
0144     ADS124S08_CHAN(8),
0145     ADS124S08_CHAN(9),
0146     ADS124S08_CHAN(10),
0147     ADS124S08_CHAN(11),
0148 };
0149
0150 static const struct ads124s_chip_info ads124s_chip_info_tbl[] = {
0151     [ADS124S08_ID] = {
0152         .channels = ads124s08_channels,
0153         .num_channels = ARRAY_SIZE(ads124s08_channels),
0154     },
0155     [ADS124S06_ID] = {
0156         .channels = ads124s06_channels,
0157         .num_channels = ARRAY_SIZE(ads124s06_channels),
0158     },
0159 };
0160
0161 static int ads124s_write_cmd(struct iio_dev *indio_dev, u8 command)
0162 {
0163     struct ads124s_private *priv = iio_priv(indio_dev);
0164
0165     priv->data[0] = command;
0166
0167     return spi_write(priv->spi, &priv->data[0], 1);
0168 }
0169
0170 static int ads124s_write_reg(struct iio_dev *indio_dev, u8 reg, u8 data)
0171 {
0172     struct ads124s_private *priv = iio_priv(indio_dev);
0173
0174     priv->data[0] = ADS124S08_CMD_WREG | reg;
0175     priv->data[1] = 0x0;
0176     priv->data[2] = data;
0177
0178     return spi_write(priv->spi, &priv->data[0], 3);
0179 }
0180
0181 static int ads124s_reset(struct iio_dev *indio_dev)
0182 {
0183     struct ads124s_private *priv = iio_priv(indio_dev);
0184
0185     if (priv->reset_gpio) {
0186         gpiod_set_value(priv->reset_gpio, 0);
0187         udelay(200);
0188         gpiod_set_value(priv->reset_gpio, 1);
0189     } else {
0190         return ads124s_write_cmd(indio_dev, ADS124S08_CMD_RESET);
0191     }
0192
0193     return 0;
0194 };
0195
0196 static int ads124s_read(struct iio_dev *indio_dev)
0197 {
0198     struct ads124s_private *priv = iio_priv(indio_dev);
0199     int ret;
0200     struct spi_transfer t[] = {
0201         {
0202             .tx_buf = &priv->data[0],
0203             .len = 4,
0204             .cs_change = 1,
0205         }, {
0206             .tx_buf = &priv->data[1],
0207             .rx_buf = &priv->data[1],
0208             .len = 4,
0209         },
0210     };
0211
0212     priv->data[0] = ADS124S08_CMD_RDATA;
0213     memset(&priv->data[1], ADS124S08_CMD_NOP, sizeof(priv->data) - 1);
0214
0215     ret = spi_sync_transfer(priv->spi, t, ARRAY_SIZE(t));
0216     if (ret < 0)
0217         return ret;
0218
0219     return get_unaligned_be24(&priv->data[2]);
0220 }
0221
0222 static int ads124s_read_raw(struct iio_dev *indio_dev,
0223                 struct iio_chan_spec const *chan,
0224                 int *val, int *val2, long m)
0225 {
0226     struct ads124s_private *priv = iio_priv(indio_dev);
0227     int ret;
0228
0229     mutex_lock(&priv->lock);
0230     switch (m) {
0231     case IIO_CHAN_INFO_RAW:
0232         ret = ads124s_write_reg(indio_dev, ADS124S08_INPUT_MUX,
0233                     chan->channel);
0234         if (ret) {
0235             dev_err(&priv->spi->dev, "Set ADC CH failed\n");
0236             goto out;
0237         }
0238
0239         ret = ads124s_write_cmd(indio_dev, ADS124S08_START_CONV);
0240         if (ret) {
0241             dev_err(&priv->spi->dev, "Start conversions failed\n");
0242             goto out;
0243         }
0244
0245         ret = ads124s_read(indio_dev);
0246         if (ret < 0) {
0247             dev_err(&priv->spi->dev, "Read ADC failed\n");
0248             goto out;
0249         }
0250
0251         *val = ret;
0252
0253         ret = ads124s_write_cmd(indio_dev, ADS124S08_STOP_CONV);
0254         if (ret) {
0255             dev_err(&priv->spi->dev, "Stop conversions failed\n");
0256             goto out;
0257         }
0258
0259         ret = IIO_VAL_INT;
0260         break;
0261     default:
0262         ret = -EINVAL;
0263         break;
0264     }
0265 out:
0266     mutex_unlock(&priv->lock);
0267     return ret;
0268 }
0269
0270 static const struct iio_info ads124s_info = {
0271     .read_raw = &ads124s_read_raw,
0272 };
0273
0274 static irqreturn_t ads124s_trigger_handler(int irq, void *p)
0275 {
0276     struct iio_poll_func *pf = p;
0277     struct iio_dev *indio_dev = pf->indio_dev;
0278     struct ads124s_private *priv = iio_priv(indio_dev);
0279     int scan_index, j = 0;
0280     int ret;
0281
0282     for_each_set_bit(scan_index, indio_dev->active_scan_mask,
0283              indio_dev->masklength) {
0284         ret = ads124s_write_reg(indio_dev, ADS124S08_INPUT_MUX,
0285                     scan_index);
0286         if (ret)
0287             dev_err(&priv->spi->dev, "Set ADC CH failed\n");
0288
0289         ret = ads124s_write_cmd(indio_dev, ADS124S08_START_CONV);
0290         if (ret)
0291             dev_err(&priv->spi->dev, "Start ADC conversions failed\n");
0292
0293         priv->buffer[j] = ads124s_read(indio_dev);
0294         ret = ads124s_write_cmd(indio_dev, ADS124S08_STOP_CONV);
0295         if (ret)
0296             dev_err(&priv->spi->dev, "Stop ADC conversions failed\n");
0297
0298         j++;
0299     }
0300
0301     iio_push_to_buffers_with_timestamp(indio_dev, priv->buffer,
0302             pf->timestamp);
0303
0304     iio_trigger_notify_done(indio_dev->trig);
0305
0306     return IRQ_HANDLED;
0307 }
0308
0309 static int ads124s_probe(struct spi_device *spi)
0310 {
0311     struct ads124s_private *ads124s_priv;
0312     struct iio_dev *indio_dev;
0313     const struct spi_device_id *spi_id = spi_get_device_id(spi);
0314     int ret;
0315
0316     indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*ads124s_priv));
0317     if (indio_dev == NULL)
0318         return -ENOMEM;
0319
0320     ads124s_priv = iio_priv(indio_dev);
0321
0322     ads124s_priv->reset_gpio = devm_gpiod_get_optional(&spi->dev,
0323                            "reset", GPIOD_OUT_LOW);
0324     if (IS_ERR(ads124s_priv->reset_gpio))
0325         dev_info(&spi->dev, "Reset GPIO not defined\n");
0326
0327     ads124s_priv->chip_info = &ads124s_chip_info_tbl[spi_id->driver_data];
0328
0329     ads124s_priv->spi = spi;
0330
0331     indio_dev->name = spi_id->name;
0332     indio_dev->modes = INDIO_DIRECT_MODE;
0333     indio_dev->channels = ads124s_priv->chip_info->channels;
0334     indio_dev->num_channels = ads124s_priv->chip_info->num_channels;
0335     indio_dev->info = &ads124s_info;
0336
0337     mutex_init(&ads124s_priv->lock);
0338
0339     ret = devm_iio_triggered_buffer_setup(&spi->dev, indio_dev, NULL,
0340                           ads124s_trigger_handler, NULL);
0341     if (ret) {
0342         dev_err(&spi->dev, "iio triggered buffer setup failed\n");
0343         return ret;
0344     }
0345
0346     ads124s_reset(indio_dev);
0347
0348     return devm_iio_device_register(&spi->dev, indio_dev);
0349 }
0350
0351 static const struct spi_device_id ads124s_id[] = {
0352     { "ads124s06", ADS124S06_ID },
0353     { "ads124s08", ADS124S08_ID },
0354     { }
0355 };
0356 MODULE_DEVICE_TABLE(spi, ads124s_id);
0357
0358 static const struct of_device_id ads124s_of_table[] = {
0359     { .compatible = "ti,ads124s06" },
0360     { .compatible = "ti,ads124s08" },
0361     { },
0362 };
0363 MODULE_DEVICE_TABLE(of, ads124s_of_table);
0364
0365 static struct spi_driver ads124s_driver = {
0366     .driver = {
0367         .name   = "ads124s08",
0368         .of_match_table = ads124s_of_table,
0369     },
0370     .probe      = ads124s_probe,
0371     .id_table   = ads124s_id,
0372 };
0373 module_spi_driver(ads124s_driver);
0374
0375 MODULE_AUTHOR("Dan Murphy <dmuprhy@ti.com>");
0376 MODULE_DESCRIPTION("TI TI_ADS12S0X ADC");
0377 MODULE_LICENSE("GPL v2");