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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * ADS1015 - Texas Instruments Analog-to-Digital Converter
0004  *
0005  * Copyright (c) 2016, Intel Corporation.
0006  *
0007  * IIO driver for ADS1015 ADC 7-bit I2C slave address:
0008  *  * 0x48 - ADDR connected to Ground
0009  *  * 0x49 - ADDR connected to Vdd
0010  *  * 0x4A - ADDR connected to SDA
0011  *  * 0x4B - ADDR connected to SCL
0012  */
0013 
0014 #include <linux/module.h>
0015 #include <linux/init.h>
0016 #include <linux/irq.h>
0017 #include <linux/i2c.h>
0018 #include <linux/property.h>
0019 #include <linux/regmap.h>
0020 #include <linux/pm_runtime.h>
0021 #include <linux/mutex.h>
0022 #include <linux/delay.h>
0023 
0024 #include <linux/iio/iio.h>
0025 #include <linux/iio/types.h>
0026 #include <linux/iio/sysfs.h>
0027 #include <linux/iio/events.h>
0028 #include <linux/iio/buffer.h>
0029 #include <linux/iio/triggered_buffer.h>
0030 #include <linux/iio/trigger_consumer.h>
0031 
0032 #define ADS1015_DRV_NAME "ads1015"
0033 
0034 #define ADS1015_CHANNELS 8
0035 
0036 #define ADS1015_CONV_REG    0x00
0037 #define ADS1015_CFG_REG     0x01
0038 #define ADS1015_LO_THRESH_REG   0x02
0039 #define ADS1015_HI_THRESH_REG   0x03
0040 
0041 #define ADS1015_CFG_COMP_QUE_SHIFT  0
0042 #define ADS1015_CFG_COMP_LAT_SHIFT  2
0043 #define ADS1015_CFG_COMP_POL_SHIFT  3
0044 #define ADS1015_CFG_COMP_MODE_SHIFT 4
0045 #define ADS1015_CFG_DR_SHIFT    5
0046 #define ADS1015_CFG_MOD_SHIFT   8
0047 #define ADS1015_CFG_PGA_SHIFT   9
0048 #define ADS1015_CFG_MUX_SHIFT   12
0049 
0050 #define ADS1015_CFG_COMP_QUE_MASK   GENMASK(1, 0)
0051 #define ADS1015_CFG_COMP_LAT_MASK   BIT(2)
0052 #define ADS1015_CFG_COMP_POL_MASK   BIT(3)
0053 #define ADS1015_CFG_COMP_MODE_MASK  BIT(4)
0054 #define ADS1015_CFG_DR_MASK GENMASK(7, 5)
0055 #define ADS1015_CFG_MOD_MASK    BIT(8)
0056 #define ADS1015_CFG_PGA_MASK    GENMASK(11, 9)
0057 #define ADS1015_CFG_MUX_MASK    GENMASK(14, 12)
0058 
0059 /* Comparator queue and disable field */
0060 #define ADS1015_CFG_COMP_DISABLE    3
0061 
0062 /* Comparator polarity field */
0063 #define ADS1015_CFG_COMP_POL_LOW    0
0064 #define ADS1015_CFG_COMP_POL_HIGH   1
0065 
0066 /* Comparator mode field */
0067 #define ADS1015_CFG_COMP_MODE_TRAD  0
0068 #define ADS1015_CFG_COMP_MODE_WINDOW    1
0069 
0070 /* device operating modes */
0071 #define ADS1015_CONTINUOUS  0
0072 #define ADS1015_SINGLESHOT  1
0073 
0074 #define ADS1015_SLEEP_DELAY_MS      2000
0075 #define ADS1015_DEFAULT_PGA     2
0076 #define ADS1015_DEFAULT_DATA_RATE   4
0077 #define ADS1015_DEFAULT_CHAN        0
0078 
0079 struct ads1015_chip_data {
0080     struct iio_chan_spec const  *channels;
0081     int             num_channels;
0082     const struct iio_info       *info;
0083     const int           *data_rate;
0084     const int           data_rate_len;
0085     const int           *scale;
0086     const int           scale_len;
0087     bool                has_comparator;
0088 };
0089 
0090 enum ads1015_channels {
0091     ADS1015_AIN0_AIN1 = 0,
0092     ADS1015_AIN0_AIN3,
0093     ADS1015_AIN1_AIN3,
0094     ADS1015_AIN2_AIN3,
0095     ADS1015_AIN0,
0096     ADS1015_AIN1,
0097     ADS1015_AIN2,
0098     ADS1015_AIN3,
0099     ADS1015_TIMESTAMP,
0100 };
0101 
0102 static const int ads1015_data_rate[] = {
0103     128, 250, 490, 920, 1600, 2400, 3300, 3300
0104 };
0105 
0106 static const int ads1115_data_rate[] = {
0107     8, 16, 32, 64, 128, 250, 475, 860
0108 };
0109 
0110 /*
0111  * Translation from PGA bits to full-scale positive and negative input voltage
0112  * range in mV
0113  */
0114 static const int ads1015_fullscale_range[] = {
0115     6144, 4096, 2048, 1024, 512, 256, 256, 256
0116 };
0117 
0118 static const int ads1015_scale[] = {    /* 12bit ADC */
0119     256, 11,
0120     512, 11,
0121     1024, 11,
0122     2048, 11,
0123     4096, 11,
0124     6144, 11
0125 };
0126 
0127 static const int ads1115_scale[] = {    /* 16bit ADC */
0128     256, 15,
0129     512, 15,
0130     1024, 15,
0131     2048, 15,
0132     4096, 15,
0133     6144, 15
0134 };
0135 
0136 /*
0137  * Translation from COMP_QUE field value to the number of successive readings
0138  * exceed the threshold values before an interrupt is generated
0139  */
0140 static const int ads1015_comp_queue[] = { 1, 2, 4 };
0141 
0142 static const struct iio_event_spec ads1015_events[] = {
0143     {
0144         .type = IIO_EV_TYPE_THRESH,
0145         .dir = IIO_EV_DIR_RISING,
0146         .mask_separate = BIT(IIO_EV_INFO_VALUE) |
0147                 BIT(IIO_EV_INFO_ENABLE),
0148     }, {
0149         .type = IIO_EV_TYPE_THRESH,
0150         .dir = IIO_EV_DIR_FALLING,
0151         .mask_separate = BIT(IIO_EV_INFO_VALUE),
0152     }, {
0153         .type = IIO_EV_TYPE_THRESH,
0154         .dir = IIO_EV_DIR_EITHER,
0155         .mask_separate = BIT(IIO_EV_INFO_ENABLE) |
0156                 BIT(IIO_EV_INFO_PERIOD),
0157     },
0158 };
0159 
0160 /*
0161  * Compile-time check whether _fitbits can accommodate up to _testbits
0162  * bits. Returns _fitbits on success, fails to compile otherwise.
0163  *
0164  * The test works such that it multiplies constant _fitbits by constant
0165  * double-negation of size of a non-empty structure, i.e. it multiplies
0166  * constant _fitbits by constant 1 in each successful compilation case.
0167  * The non-empty structure may contain C11 _Static_assert(), make use of
0168  * this and place the kernel variant of static assert in there, so that
0169  * it performs the compile-time check for _testbits <= _fitbits. Note
0170  * that it is not possible to directly use static_assert in compound
0171  * statements, hence this convoluted construct.
0172  */
0173 #define FIT_CHECK(_testbits, _fitbits)                  \
0174     (                               \
0175         (_fitbits) *                        \
0176         !!sizeof(struct {                   \
0177             static_assert((_testbits) <= (_fitbits));   \
0178             int pad;                    \
0179         })                          \
0180     )
0181 
0182 #define ADS1015_V_CHAN(_chan, _addr, _realbits, _shift, _event_spec, _num_event_specs) { \
0183     .type = IIO_VOLTAGE,                    \
0184     .indexed = 1,                       \
0185     .address = _addr,                   \
0186     .channel = _chan,                   \
0187     .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |      \
0188                 BIT(IIO_CHAN_INFO_SCALE) |  \
0189                 BIT(IIO_CHAN_INFO_SAMP_FREQ),   \
0190     .info_mask_shared_by_all_available =            \
0191                 BIT(IIO_CHAN_INFO_SCALE) |  \
0192                 BIT(IIO_CHAN_INFO_SAMP_FREQ),   \
0193     .scan_index = _addr,                    \
0194     .scan_type = {                      \
0195         .sign = 's',                    \
0196         .realbits = (_realbits),            \
0197         .storagebits = FIT_CHECK((_realbits) + (_shift), 16),   \
0198         .shift = (_shift),              \
0199         .endianness = IIO_CPU,              \
0200     },                          \
0201     .event_spec = (_event_spec),                \
0202     .num_event_specs = (_num_event_specs),          \
0203     .datasheet_name = "AIN"#_chan,              \
0204 }
0205 
0206 #define ADS1015_V_DIFF_CHAN(_chan, _chan2, _addr, _realbits, _shift, _event_spec, _num_event_specs) { \
0207     .type = IIO_VOLTAGE,                    \
0208     .differential = 1,                  \
0209     .indexed = 1,                       \
0210     .address = _addr,                   \
0211     .channel = _chan,                   \
0212     .channel2 = _chan2,                 \
0213     .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |      \
0214                 BIT(IIO_CHAN_INFO_SCALE) |  \
0215                 BIT(IIO_CHAN_INFO_SAMP_FREQ),   \
0216     .info_mask_shared_by_all_available =            \
0217                 BIT(IIO_CHAN_INFO_SCALE) |  \
0218                 BIT(IIO_CHAN_INFO_SAMP_FREQ),   \
0219     .scan_index = _addr,                    \
0220     .scan_type = {                      \
0221         .sign = 's',                    \
0222         .realbits = (_realbits),            \
0223         .storagebits = FIT_CHECK((_realbits) + (_shift), 16),   \
0224         .shift = (_shift),              \
0225         .endianness = IIO_CPU,              \
0226     },                          \
0227     .event_spec = (_event_spec),                \
0228     .num_event_specs = (_num_event_specs),          \
0229     .datasheet_name = "AIN"#_chan"-AIN"#_chan2,     \
0230 }
0231 
0232 struct ads1015_channel_data {
0233     bool enabled;
0234     unsigned int pga;
0235     unsigned int data_rate;
0236 };
0237 
0238 struct ads1015_thresh_data {
0239     unsigned int comp_queue;
0240     int high_thresh;
0241     int low_thresh;
0242 };
0243 
0244 struct ads1015_data {
0245     struct regmap *regmap;
0246     /*
0247      * Protects ADC ops, e.g: concurrent sysfs/buffered
0248      * data reads, configuration updates
0249      */
0250     struct mutex lock;
0251     struct ads1015_channel_data channel_data[ADS1015_CHANNELS];
0252 
0253     unsigned int event_channel;
0254     unsigned int comp_mode;
0255     struct ads1015_thresh_data thresh_data[ADS1015_CHANNELS];
0256 
0257     const struct ads1015_chip_data *chip;
0258     /*
0259      * Set to true when the ADC is switched to the continuous-conversion
0260      * mode and exits from a power-down state.  This flag is used to avoid
0261      * getting the stale result from the conversion register.
0262      */
0263     bool conv_invalid;
0264 };
0265 
0266 static bool ads1015_event_channel_enabled(struct ads1015_data *data)
0267 {
0268     return (data->event_channel != ADS1015_CHANNELS);
0269 }
0270 
0271 static void ads1015_event_channel_enable(struct ads1015_data *data, int chan,
0272                      int comp_mode)
0273 {
0274     WARN_ON(ads1015_event_channel_enabled(data));
0275 
0276     data->event_channel = chan;
0277     data->comp_mode = comp_mode;
0278 }
0279 
0280 static void ads1015_event_channel_disable(struct ads1015_data *data, int chan)
0281 {
0282     data->event_channel = ADS1015_CHANNELS;
0283 }
0284 
0285 static const struct regmap_range ads1015_writeable_ranges[] = {
0286     regmap_reg_range(ADS1015_CFG_REG, ADS1015_HI_THRESH_REG),
0287 };
0288 
0289 static const struct regmap_access_table ads1015_writeable_table = {
0290     .yes_ranges = ads1015_writeable_ranges,
0291     .n_yes_ranges = ARRAY_SIZE(ads1015_writeable_ranges),
0292 };
0293 
0294 static const struct regmap_config ads1015_regmap_config = {
0295     .reg_bits = 8,
0296     .val_bits = 16,
0297     .max_register = ADS1015_HI_THRESH_REG,
0298     .wr_table = &ads1015_writeable_table,
0299 };
0300 
0301 static const struct regmap_range tla2024_writeable_ranges[] = {
0302     regmap_reg_range(ADS1015_CFG_REG, ADS1015_CFG_REG),
0303 };
0304 
0305 static const struct regmap_access_table tla2024_writeable_table = {
0306     .yes_ranges = tla2024_writeable_ranges,
0307     .n_yes_ranges = ARRAY_SIZE(tla2024_writeable_ranges),
0308 };
0309 
0310 static const struct regmap_config tla2024_regmap_config = {
0311     .reg_bits = 8,
0312     .val_bits = 16,
0313     .max_register = ADS1015_CFG_REG,
0314     .wr_table = &tla2024_writeable_table,
0315 };
0316 
0317 static const struct iio_chan_spec ads1015_channels[] = {
0318     ADS1015_V_DIFF_CHAN(0, 1, ADS1015_AIN0_AIN1, 12, 4,
0319                 ads1015_events, ARRAY_SIZE(ads1015_events)),
0320     ADS1015_V_DIFF_CHAN(0, 3, ADS1015_AIN0_AIN3, 12, 4,
0321                 ads1015_events, ARRAY_SIZE(ads1015_events)),
0322     ADS1015_V_DIFF_CHAN(1, 3, ADS1015_AIN1_AIN3, 12, 4,
0323                 ads1015_events, ARRAY_SIZE(ads1015_events)),
0324     ADS1015_V_DIFF_CHAN(2, 3, ADS1015_AIN2_AIN3, 12, 4,
0325                 ads1015_events, ARRAY_SIZE(ads1015_events)),
0326     ADS1015_V_CHAN(0, ADS1015_AIN0, 12, 4,
0327                ads1015_events, ARRAY_SIZE(ads1015_events)),
0328     ADS1015_V_CHAN(1, ADS1015_AIN1, 12, 4,
0329                ads1015_events, ARRAY_SIZE(ads1015_events)),
0330     ADS1015_V_CHAN(2, ADS1015_AIN2, 12, 4,
0331                ads1015_events, ARRAY_SIZE(ads1015_events)),
0332     ADS1015_V_CHAN(3, ADS1015_AIN3, 12, 4,
0333                ads1015_events, ARRAY_SIZE(ads1015_events)),
0334     IIO_CHAN_SOFT_TIMESTAMP(ADS1015_TIMESTAMP),
0335 };
0336 
0337 static const struct iio_chan_spec ads1115_channels[] = {
0338     ADS1015_V_DIFF_CHAN(0, 1, ADS1015_AIN0_AIN1, 16, 0,
0339                 ads1015_events, ARRAY_SIZE(ads1015_events)),
0340     ADS1015_V_DIFF_CHAN(0, 3, ADS1015_AIN0_AIN3, 16, 0,
0341                 ads1015_events, ARRAY_SIZE(ads1015_events)),
0342     ADS1015_V_DIFF_CHAN(1, 3, ADS1015_AIN1_AIN3, 16, 0,
0343                 ads1015_events, ARRAY_SIZE(ads1015_events)),
0344     ADS1015_V_DIFF_CHAN(2, 3, ADS1015_AIN2_AIN3, 16, 0,
0345                 ads1015_events, ARRAY_SIZE(ads1015_events)),
0346     ADS1015_V_CHAN(0, ADS1015_AIN0, 16, 0,
0347                ads1015_events, ARRAY_SIZE(ads1015_events)),
0348     ADS1015_V_CHAN(1, ADS1015_AIN1, 16, 0,
0349                ads1015_events, ARRAY_SIZE(ads1015_events)),
0350     ADS1015_V_CHAN(2, ADS1015_AIN2, 16, 0,
0351                ads1015_events, ARRAY_SIZE(ads1015_events)),
0352     ADS1015_V_CHAN(3, ADS1015_AIN3, 16, 0,
0353                ads1015_events, ARRAY_SIZE(ads1015_events)),
0354     IIO_CHAN_SOFT_TIMESTAMP(ADS1015_TIMESTAMP),
0355 };
0356 
0357 static const struct iio_chan_spec tla2024_channels[] = {
0358     ADS1015_V_DIFF_CHAN(0, 1, ADS1015_AIN0_AIN1, 12, 4, NULL, 0),
0359     ADS1015_V_DIFF_CHAN(0, 3, ADS1015_AIN0_AIN3, 12, 4, NULL, 0),
0360     ADS1015_V_DIFF_CHAN(1, 3, ADS1015_AIN1_AIN3, 12, 4, NULL, 0),
0361     ADS1015_V_DIFF_CHAN(2, 3, ADS1015_AIN2_AIN3, 12, 4, NULL, 0),
0362     ADS1015_V_CHAN(0, ADS1015_AIN0, 12, 4, NULL, 0),
0363     ADS1015_V_CHAN(1, ADS1015_AIN1, 12, 4, NULL, 0),
0364     ADS1015_V_CHAN(2, ADS1015_AIN2, 12, 4, NULL, 0),
0365     ADS1015_V_CHAN(3, ADS1015_AIN3, 12, 4, NULL, 0),
0366     IIO_CHAN_SOFT_TIMESTAMP(ADS1015_TIMESTAMP),
0367 };
0368 
0369 
0370 #ifdef CONFIG_PM
0371 static int ads1015_set_power_state(struct ads1015_data *data, bool on)
0372 {
0373     int ret;
0374     struct device *dev = regmap_get_device(data->regmap);
0375 
0376     if (on) {
0377         ret = pm_runtime_resume_and_get(dev);
0378     } else {
0379         pm_runtime_mark_last_busy(dev);
0380         ret = pm_runtime_put_autosuspend(dev);
0381     }
0382 
0383     return ret < 0 ? ret : 0;
0384 }
0385 
0386 #else /* !CONFIG_PM */
0387 
0388 static int ads1015_set_power_state(struct ads1015_data *data, bool on)
0389 {
0390     return 0;
0391 }
0392 
0393 #endif /* !CONFIG_PM */
0394 
0395 static
0396 int ads1015_get_adc_result(struct ads1015_data *data, int chan, int *val)
0397 {
0398     const int *data_rate = data->chip->data_rate;
0399     int ret, pga, dr, dr_old, conv_time;
0400     unsigned int old, mask, cfg;
0401 
0402     if (chan < 0 || chan >= ADS1015_CHANNELS)
0403         return -EINVAL;
0404 
0405     ret = regmap_read(data->regmap, ADS1015_CFG_REG, &old);
0406     if (ret)
0407         return ret;
0408 
0409     pga = data->channel_data[chan].pga;
0410     dr = data->channel_data[chan].data_rate;
0411     mask = ADS1015_CFG_MUX_MASK | ADS1015_CFG_PGA_MASK |
0412         ADS1015_CFG_DR_MASK;
0413     cfg = chan << ADS1015_CFG_MUX_SHIFT | pga << ADS1015_CFG_PGA_SHIFT |
0414         dr << ADS1015_CFG_DR_SHIFT;
0415 
0416     if (ads1015_event_channel_enabled(data)) {
0417         mask |= ADS1015_CFG_COMP_QUE_MASK | ADS1015_CFG_COMP_MODE_MASK;
0418         cfg |= data->thresh_data[chan].comp_queue <<
0419                 ADS1015_CFG_COMP_QUE_SHIFT |
0420             data->comp_mode <<
0421                 ADS1015_CFG_COMP_MODE_SHIFT;
0422     }
0423 
0424     cfg = (old & ~mask) | (cfg & mask);
0425     if (old != cfg) {
0426         ret = regmap_write(data->regmap, ADS1015_CFG_REG, cfg);
0427         if (ret)
0428             return ret;
0429         data->conv_invalid = true;
0430     }
0431     if (data->conv_invalid) {
0432         dr_old = (old & ADS1015_CFG_DR_MASK) >> ADS1015_CFG_DR_SHIFT;
0433         conv_time = DIV_ROUND_UP(USEC_PER_SEC, data_rate[dr_old]);
0434         conv_time += DIV_ROUND_UP(USEC_PER_SEC, data_rate[dr]);
0435         conv_time += conv_time / 10; /* 10% internal clock inaccuracy */
0436         usleep_range(conv_time, conv_time + 1);
0437         data->conv_invalid = false;
0438     }
0439 
0440     return regmap_read(data->regmap, ADS1015_CONV_REG, val);
0441 }
0442 
0443 static irqreturn_t ads1015_trigger_handler(int irq, void *p)
0444 {
0445     struct iio_poll_func *pf = p;
0446     struct iio_dev *indio_dev = pf->indio_dev;
0447     struct ads1015_data *data = iio_priv(indio_dev);
0448     /* Ensure natural alignment of timestamp */
0449     struct {
0450         s16 chan;
0451         s64 timestamp __aligned(8);
0452     } scan;
0453     int chan, ret, res;
0454 
0455     memset(&scan, 0, sizeof(scan));
0456 
0457     mutex_lock(&data->lock);
0458     chan = find_first_bit(indio_dev->active_scan_mask,
0459                   indio_dev->masklength);
0460     ret = ads1015_get_adc_result(data, chan, &res);
0461     if (ret < 0) {
0462         mutex_unlock(&data->lock);
0463         goto err;
0464     }
0465 
0466     scan.chan = res;
0467     mutex_unlock(&data->lock);
0468 
0469     iio_push_to_buffers_with_timestamp(indio_dev, &scan,
0470                        iio_get_time_ns(indio_dev));
0471 
0472 err:
0473     iio_trigger_notify_done(indio_dev->trig);
0474 
0475     return IRQ_HANDLED;
0476 }
0477 
0478 static int ads1015_set_scale(struct ads1015_data *data,
0479                  struct iio_chan_spec const *chan,
0480                  int scale, int uscale)
0481 {
0482     int i;
0483     int fullscale = div_s64((scale * 1000000LL + uscale) <<
0484                 (chan->scan_type.realbits - 1), 1000000);
0485 
0486     for (i = 0; i < ARRAY_SIZE(ads1015_fullscale_range); i++) {
0487         if (ads1015_fullscale_range[i] == fullscale) {
0488             data->channel_data[chan->address].pga = i;
0489             return 0;
0490         }
0491     }
0492 
0493     return -EINVAL;
0494 }
0495 
0496 static int ads1015_set_data_rate(struct ads1015_data *data, int chan, int rate)
0497 {
0498     int i;
0499 
0500     for (i = 0; i < data->chip->data_rate_len; i++) {
0501         if (data->chip->data_rate[i] == rate) {
0502             data->channel_data[chan].data_rate = i;
0503             return 0;
0504         }
0505     }
0506 
0507     return -EINVAL;
0508 }
0509 
0510 static int ads1015_read_avail(struct iio_dev *indio_dev,
0511                   struct iio_chan_spec const *chan,
0512                   const int **vals, int *type, int *length,
0513                   long mask)
0514 {
0515     struct ads1015_data *data = iio_priv(indio_dev);
0516 
0517     if (chan->type != IIO_VOLTAGE)
0518         return -EINVAL;
0519 
0520     switch (mask) {
0521     case IIO_CHAN_INFO_SCALE:
0522         *type = IIO_VAL_FRACTIONAL_LOG2;
0523         *vals =  data->chip->scale;
0524         *length = data->chip->scale_len;
0525         return IIO_AVAIL_LIST;
0526     case IIO_CHAN_INFO_SAMP_FREQ:
0527         *type = IIO_VAL_INT;
0528         *vals = data->chip->data_rate;
0529         *length = data->chip->data_rate_len;
0530         return IIO_AVAIL_LIST;
0531     default:
0532         return -EINVAL;
0533     }
0534 }
0535 
0536 static int ads1015_read_raw(struct iio_dev *indio_dev,
0537                 struct iio_chan_spec const *chan, int *val,
0538                 int *val2, long mask)
0539 {
0540     int ret, idx;
0541     struct ads1015_data *data = iio_priv(indio_dev);
0542 
0543     mutex_lock(&data->lock);
0544     switch (mask) {
0545     case IIO_CHAN_INFO_RAW:
0546         ret = iio_device_claim_direct_mode(indio_dev);
0547         if (ret)
0548             break;
0549 
0550         if (ads1015_event_channel_enabled(data) &&
0551                 data->event_channel != chan->address) {
0552             ret = -EBUSY;
0553             goto release_direct;
0554         }
0555 
0556         ret = ads1015_set_power_state(data, true);
0557         if (ret < 0)
0558             goto release_direct;
0559 
0560         ret = ads1015_get_adc_result(data, chan->address, val);
0561         if (ret < 0) {
0562             ads1015_set_power_state(data, false);
0563             goto release_direct;
0564         }
0565 
0566         *val = sign_extend32(*val >> chan->scan_type.shift,
0567                      chan->scan_type.realbits - 1);
0568 
0569         ret = ads1015_set_power_state(data, false);
0570         if (ret < 0)
0571             goto release_direct;
0572 
0573         ret = IIO_VAL_INT;
0574 release_direct:
0575         iio_device_release_direct_mode(indio_dev);
0576         break;
0577     case IIO_CHAN_INFO_SCALE:
0578         idx = data->channel_data[chan->address].pga;
0579         *val = ads1015_fullscale_range[idx];
0580         *val2 = chan->scan_type.realbits - 1;
0581         ret = IIO_VAL_FRACTIONAL_LOG2;
0582         break;
0583     case IIO_CHAN_INFO_SAMP_FREQ:
0584         idx = data->channel_data[chan->address].data_rate;
0585         *val = data->chip->data_rate[idx];
0586         ret = IIO_VAL_INT;
0587         break;
0588     default:
0589         ret = -EINVAL;
0590         break;
0591     }
0592     mutex_unlock(&data->lock);
0593 
0594     return ret;
0595 }
0596 
0597 static int ads1015_write_raw(struct iio_dev *indio_dev,
0598                  struct iio_chan_spec const *chan, int val,
0599                  int val2, long mask)
0600 {
0601     struct ads1015_data *data = iio_priv(indio_dev);
0602     int ret;
0603 
0604     mutex_lock(&data->lock);
0605     switch (mask) {
0606     case IIO_CHAN_INFO_SCALE:
0607         ret = ads1015_set_scale(data, chan, val, val2);
0608         break;
0609     case IIO_CHAN_INFO_SAMP_FREQ:
0610         ret = ads1015_set_data_rate(data, chan->address, val);
0611         break;
0612     default:
0613         ret = -EINVAL;
0614         break;
0615     }
0616     mutex_unlock(&data->lock);
0617 
0618     return ret;
0619 }
0620 
0621 static int ads1015_read_event(struct iio_dev *indio_dev,
0622     const struct iio_chan_spec *chan, enum iio_event_type type,
0623     enum iio_event_direction dir, enum iio_event_info info, int *val,
0624     int *val2)
0625 {
0626     struct ads1015_data *data = iio_priv(indio_dev);
0627     int ret;
0628     unsigned int comp_queue;
0629     int period;
0630     int dr;
0631 
0632     mutex_lock(&data->lock);
0633 
0634     switch (info) {
0635     case IIO_EV_INFO_VALUE:
0636         *val = (dir == IIO_EV_DIR_RISING) ?
0637             data->thresh_data[chan->address].high_thresh :
0638             data->thresh_data[chan->address].low_thresh;
0639         ret = IIO_VAL_INT;
0640         break;
0641     case IIO_EV_INFO_PERIOD:
0642         dr = data->channel_data[chan->address].data_rate;
0643         comp_queue = data->thresh_data[chan->address].comp_queue;
0644         period = ads1015_comp_queue[comp_queue] *
0645             USEC_PER_SEC / data->chip->data_rate[dr];
0646 
0647         *val = period / USEC_PER_SEC;
0648         *val2 = period % USEC_PER_SEC;
0649         ret = IIO_VAL_INT_PLUS_MICRO;
0650         break;
0651     default:
0652         ret = -EINVAL;
0653         break;
0654     }
0655 
0656     mutex_unlock(&data->lock);
0657 
0658     return ret;
0659 }
0660 
0661 static int ads1015_write_event(struct iio_dev *indio_dev,
0662     const struct iio_chan_spec *chan, enum iio_event_type type,
0663     enum iio_event_direction dir, enum iio_event_info info, int val,
0664     int val2)
0665 {
0666     struct ads1015_data *data = iio_priv(indio_dev);
0667     const int *data_rate = data->chip->data_rate;
0668     int realbits = chan->scan_type.realbits;
0669     int ret = 0;
0670     long long period;
0671     int i;
0672     int dr;
0673 
0674     mutex_lock(&data->lock);
0675 
0676     switch (info) {
0677     case IIO_EV_INFO_VALUE:
0678         if (val >= 1 << (realbits - 1) || val < -1 << (realbits - 1)) {
0679             ret = -EINVAL;
0680             break;
0681         }
0682         if (dir == IIO_EV_DIR_RISING)
0683             data->thresh_data[chan->address].high_thresh = val;
0684         else
0685             data->thresh_data[chan->address].low_thresh = val;
0686         break;
0687     case IIO_EV_INFO_PERIOD:
0688         dr = data->channel_data[chan->address].data_rate;
0689         period = val * USEC_PER_SEC + val2;
0690 
0691         for (i = 0; i < ARRAY_SIZE(ads1015_comp_queue) - 1; i++) {
0692             if (period <= ads1015_comp_queue[i] *
0693                     USEC_PER_SEC / data_rate[dr])
0694                 break;
0695         }
0696         data->thresh_data[chan->address].comp_queue = i;
0697         break;
0698     default:
0699         ret = -EINVAL;
0700         break;
0701     }
0702 
0703     mutex_unlock(&data->lock);
0704 
0705     return ret;
0706 }
0707 
0708 static int ads1015_read_event_config(struct iio_dev *indio_dev,
0709     const struct iio_chan_spec *chan, enum iio_event_type type,
0710     enum iio_event_direction dir)
0711 {
0712     struct ads1015_data *data = iio_priv(indio_dev);
0713     int ret = 0;
0714 
0715     mutex_lock(&data->lock);
0716     if (data->event_channel == chan->address) {
0717         switch (dir) {
0718         case IIO_EV_DIR_RISING:
0719             ret = 1;
0720             break;
0721         case IIO_EV_DIR_EITHER:
0722             ret = (data->comp_mode == ADS1015_CFG_COMP_MODE_WINDOW);
0723             break;
0724         default:
0725             ret = -EINVAL;
0726             break;
0727         }
0728     }
0729     mutex_unlock(&data->lock);
0730 
0731     return ret;
0732 }
0733 
0734 static int ads1015_enable_event_config(struct ads1015_data *data,
0735     const struct iio_chan_spec *chan, int comp_mode)
0736 {
0737     int low_thresh = data->thresh_data[chan->address].low_thresh;
0738     int high_thresh = data->thresh_data[chan->address].high_thresh;
0739     int ret;
0740     unsigned int val;
0741 
0742     if (ads1015_event_channel_enabled(data)) {
0743         if (data->event_channel != chan->address ||
0744             (data->comp_mode == ADS1015_CFG_COMP_MODE_TRAD &&
0745                 comp_mode == ADS1015_CFG_COMP_MODE_WINDOW))
0746             return -EBUSY;
0747 
0748         return 0;
0749     }
0750 
0751     if (comp_mode == ADS1015_CFG_COMP_MODE_TRAD) {
0752         low_thresh = max(-1 << (chan->scan_type.realbits - 1),
0753                 high_thresh - 1);
0754     }
0755     ret = regmap_write(data->regmap, ADS1015_LO_THRESH_REG,
0756             low_thresh << chan->scan_type.shift);
0757     if (ret)
0758         return ret;
0759 
0760     ret = regmap_write(data->regmap, ADS1015_HI_THRESH_REG,
0761             high_thresh << chan->scan_type.shift);
0762     if (ret)
0763         return ret;
0764 
0765     ret = ads1015_set_power_state(data, true);
0766     if (ret < 0)
0767         return ret;
0768 
0769     ads1015_event_channel_enable(data, chan->address, comp_mode);
0770 
0771     ret = ads1015_get_adc_result(data, chan->address, &val);
0772     if (ret) {
0773         ads1015_event_channel_disable(data, chan->address);
0774         ads1015_set_power_state(data, false);
0775     }
0776 
0777     return ret;
0778 }
0779 
0780 static int ads1015_disable_event_config(struct ads1015_data *data,
0781     const struct iio_chan_spec *chan, int comp_mode)
0782 {
0783     int ret;
0784 
0785     if (!ads1015_event_channel_enabled(data))
0786         return 0;
0787 
0788     if (data->event_channel != chan->address)
0789         return 0;
0790 
0791     if (data->comp_mode == ADS1015_CFG_COMP_MODE_TRAD &&
0792             comp_mode == ADS1015_CFG_COMP_MODE_WINDOW)
0793         return 0;
0794 
0795     ret = regmap_update_bits(data->regmap, ADS1015_CFG_REG,
0796                 ADS1015_CFG_COMP_QUE_MASK,
0797                 ADS1015_CFG_COMP_DISABLE <<
0798                     ADS1015_CFG_COMP_QUE_SHIFT);
0799     if (ret)
0800         return ret;
0801 
0802     ads1015_event_channel_disable(data, chan->address);
0803 
0804     return ads1015_set_power_state(data, false);
0805 }
0806 
0807 static int ads1015_write_event_config(struct iio_dev *indio_dev,
0808     const struct iio_chan_spec *chan, enum iio_event_type type,
0809     enum iio_event_direction dir, int state)
0810 {
0811     struct ads1015_data *data = iio_priv(indio_dev);
0812     int ret;
0813     int comp_mode = (dir == IIO_EV_DIR_EITHER) ?
0814         ADS1015_CFG_COMP_MODE_WINDOW : ADS1015_CFG_COMP_MODE_TRAD;
0815 
0816     mutex_lock(&data->lock);
0817 
0818     /* Prevent from enabling both buffer and event at a time */
0819     ret = iio_device_claim_direct_mode(indio_dev);
0820     if (ret) {
0821         mutex_unlock(&data->lock);
0822         return ret;
0823     }
0824 
0825     if (state)
0826         ret = ads1015_enable_event_config(data, chan, comp_mode);
0827     else
0828         ret = ads1015_disable_event_config(data, chan, comp_mode);
0829 
0830     iio_device_release_direct_mode(indio_dev);
0831     mutex_unlock(&data->lock);
0832 
0833     return ret;
0834 }
0835 
0836 static irqreturn_t ads1015_event_handler(int irq, void *priv)
0837 {
0838     struct iio_dev *indio_dev = priv;
0839     struct ads1015_data *data = iio_priv(indio_dev);
0840     int val;
0841     int ret;
0842 
0843     /* Clear the latched ALERT/RDY pin */
0844     ret = regmap_read(data->regmap, ADS1015_CONV_REG, &val);
0845     if (ret)
0846         return IRQ_HANDLED;
0847 
0848     if (ads1015_event_channel_enabled(data)) {
0849         enum iio_event_direction dir;
0850         u64 code;
0851 
0852         dir = data->comp_mode == ADS1015_CFG_COMP_MODE_TRAD ?
0853                     IIO_EV_DIR_RISING : IIO_EV_DIR_EITHER;
0854         code = IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, data->event_channel,
0855                     IIO_EV_TYPE_THRESH, dir);
0856         iio_push_event(indio_dev, code, iio_get_time_ns(indio_dev));
0857     }
0858 
0859     return IRQ_HANDLED;
0860 }
0861 
0862 static int ads1015_buffer_preenable(struct iio_dev *indio_dev)
0863 {
0864     struct ads1015_data *data = iio_priv(indio_dev);
0865 
0866     /* Prevent from enabling both buffer and event at a time */
0867     if (ads1015_event_channel_enabled(data))
0868         return -EBUSY;
0869 
0870     return ads1015_set_power_state(iio_priv(indio_dev), true);
0871 }
0872 
0873 static int ads1015_buffer_postdisable(struct iio_dev *indio_dev)
0874 {
0875     return ads1015_set_power_state(iio_priv(indio_dev), false);
0876 }
0877 
0878 static const struct iio_buffer_setup_ops ads1015_buffer_setup_ops = {
0879     .preenable  = ads1015_buffer_preenable,
0880     .postdisable    = ads1015_buffer_postdisable,
0881     .validate_scan_mask = &iio_validate_scan_mask_onehot,
0882 };
0883 
0884 static const struct iio_info ads1015_info = {
0885     .read_avail = ads1015_read_avail,
0886     .read_raw   = ads1015_read_raw,
0887     .write_raw  = ads1015_write_raw,
0888     .read_event_value = ads1015_read_event,
0889     .write_event_value = ads1015_write_event,
0890     .read_event_config = ads1015_read_event_config,
0891     .write_event_config = ads1015_write_event_config,
0892 };
0893 
0894 static const struct iio_info tla2024_info = {
0895     .read_avail = ads1015_read_avail,
0896     .read_raw   = ads1015_read_raw,
0897     .write_raw  = ads1015_write_raw,
0898 };
0899 
0900 static int ads1015_client_get_channels_config(struct i2c_client *client)
0901 {
0902     struct iio_dev *indio_dev = i2c_get_clientdata(client);
0903     struct ads1015_data *data = iio_priv(indio_dev);
0904     struct device *dev = &client->dev;
0905     struct fwnode_handle *node;
0906     int i = -1;
0907 
0908     device_for_each_child_node(dev, node) {
0909         u32 pval;
0910         unsigned int channel;
0911         unsigned int pga = ADS1015_DEFAULT_PGA;
0912         unsigned int data_rate = ADS1015_DEFAULT_DATA_RATE;
0913 
0914         if (fwnode_property_read_u32(node, "reg", &pval)) {
0915             dev_err(dev, "invalid reg on %pfw\n", node);
0916             continue;
0917         }
0918 
0919         channel = pval;
0920         if (channel >= ADS1015_CHANNELS) {
0921             dev_err(dev, "invalid channel index %d on %pfw\n",
0922                 channel, node);
0923             continue;
0924         }
0925 
0926         if (!fwnode_property_read_u32(node, "ti,gain", &pval)) {
0927             pga = pval;
0928             if (pga > 6) {
0929                 dev_err(dev, "invalid gain on %pfw\n", node);
0930                 fwnode_handle_put(node);
0931                 return -EINVAL;
0932             }
0933         }
0934 
0935         if (!fwnode_property_read_u32(node, "ti,datarate", &pval)) {
0936             data_rate = pval;
0937             if (data_rate > 7) {
0938                 dev_err(dev, "invalid data_rate on %pfw\n", node);
0939                 fwnode_handle_put(node);
0940                 return -EINVAL;
0941             }
0942         }
0943 
0944         data->channel_data[channel].pga = pga;
0945         data->channel_data[channel].data_rate = data_rate;
0946 
0947         i++;
0948     }
0949 
0950     return i < 0 ? -EINVAL : 0;
0951 }
0952 
0953 static void ads1015_get_channels_config(struct i2c_client *client)
0954 {
0955     unsigned int k;
0956 
0957     struct iio_dev *indio_dev = i2c_get_clientdata(client);
0958     struct ads1015_data *data = iio_priv(indio_dev);
0959 
0960     if (!ads1015_client_get_channels_config(client))
0961         return;
0962 
0963     /* fallback on default configuration */
0964     for (k = 0; k < ADS1015_CHANNELS; ++k) {
0965         data->channel_data[k].pga = ADS1015_DEFAULT_PGA;
0966         data->channel_data[k].data_rate = ADS1015_DEFAULT_DATA_RATE;
0967     }
0968 }
0969 
0970 static int ads1015_set_conv_mode(struct ads1015_data *data, int mode)
0971 {
0972     return regmap_update_bits(data->regmap, ADS1015_CFG_REG,
0973                   ADS1015_CFG_MOD_MASK,
0974                   mode << ADS1015_CFG_MOD_SHIFT);
0975 }
0976 
0977 static int ads1015_probe(struct i2c_client *client,
0978              const struct i2c_device_id *id)
0979 {
0980     const struct ads1015_chip_data *chip;
0981     struct iio_dev *indio_dev;
0982     struct ads1015_data *data;
0983     int ret;
0984     int i;
0985 
0986     chip = device_get_match_data(&client->dev);
0987     if (!chip)
0988         chip = (const struct ads1015_chip_data *)id->driver_data;
0989     if (!chip)
0990         return dev_err_probe(&client->dev, -EINVAL, "Unknown chip\n");
0991 
0992     indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
0993     if (!indio_dev)
0994         return -ENOMEM;
0995 
0996     data = iio_priv(indio_dev);
0997     i2c_set_clientdata(client, indio_dev);
0998 
0999     mutex_init(&data->lock);
1000 
1001     indio_dev->name = ADS1015_DRV_NAME;
1002     indio_dev->modes = INDIO_DIRECT_MODE;
1003 
1004     indio_dev->channels = chip->channels;
1005     indio_dev->num_channels = chip->num_channels;
1006     indio_dev->info = chip->info;
1007     data->chip = chip;
1008     data->event_channel = ADS1015_CHANNELS;
1009 
1010     /*
1011      * Set default lower and upper threshold to min and max value
1012      * respectively.
1013      */
1014     for (i = 0; i < ADS1015_CHANNELS; i++) {
1015         int realbits = indio_dev->channels[i].scan_type.realbits;
1016 
1017         data->thresh_data[i].low_thresh = -1 << (realbits - 1);
1018         data->thresh_data[i].high_thresh = (1 << (realbits - 1)) - 1;
1019     }
1020 
1021     /* we need to keep this ABI the same as used by hwmon ADS1015 driver */
1022     ads1015_get_channels_config(client);
1023 
1024     data->regmap = devm_regmap_init_i2c(client, chip->has_comparator ?
1025                         &ads1015_regmap_config :
1026                         &tla2024_regmap_config);
1027     if (IS_ERR(data->regmap)) {
1028         dev_err(&client->dev, "Failed to allocate register map\n");
1029         return PTR_ERR(data->regmap);
1030     }
1031 
1032     ret = devm_iio_triggered_buffer_setup(&client->dev, indio_dev, NULL,
1033                           ads1015_trigger_handler,
1034                           &ads1015_buffer_setup_ops);
1035     if (ret < 0) {
1036         dev_err(&client->dev, "iio triggered buffer setup failed\n");
1037         return ret;
1038     }
1039 
1040     if (client->irq && chip->has_comparator) {
1041         unsigned long irq_trig =
1042             irqd_get_trigger_type(irq_get_irq_data(client->irq));
1043         unsigned int cfg_comp_mask = ADS1015_CFG_COMP_QUE_MASK |
1044             ADS1015_CFG_COMP_LAT_MASK | ADS1015_CFG_COMP_POL_MASK;
1045         unsigned int cfg_comp =
1046             ADS1015_CFG_COMP_DISABLE << ADS1015_CFG_COMP_QUE_SHIFT |
1047             1 << ADS1015_CFG_COMP_LAT_SHIFT;
1048 
1049         switch (irq_trig) {
1050         case IRQF_TRIGGER_LOW:
1051             cfg_comp |= ADS1015_CFG_COMP_POL_LOW <<
1052                     ADS1015_CFG_COMP_POL_SHIFT;
1053             break;
1054         case IRQF_TRIGGER_HIGH:
1055             cfg_comp |= ADS1015_CFG_COMP_POL_HIGH <<
1056                     ADS1015_CFG_COMP_POL_SHIFT;
1057             break;
1058         default:
1059             return -EINVAL;
1060         }
1061 
1062         ret = regmap_update_bits(data->regmap, ADS1015_CFG_REG,
1063                     cfg_comp_mask, cfg_comp);
1064         if (ret)
1065             return ret;
1066 
1067         ret = devm_request_threaded_irq(&client->dev, client->irq,
1068                         NULL, ads1015_event_handler,
1069                         irq_trig | IRQF_ONESHOT,
1070                         client->name, indio_dev);
1071         if (ret)
1072             return ret;
1073     }
1074 
1075     ret = ads1015_set_conv_mode(data, ADS1015_CONTINUOUS);
1076     if (ret)
1077         return ret;
1078 
1079     data->conv_invalid = true;
1080 
1081     ret = pm_runtime_set_active(&client->dev);
1082     if (ret)
1083         return ret;
1084     pm_runtime_set_autosuspend_delay(&client->dev, ADS1015_SLEEP_DELAY_MS);
1085     pm_runtime_use_autosuspend(&client->dev);
1086     pm_runtime_enable(&client->dev);
1087 
1088     ret = iio_device_register(indio_dev);
1089     if (ret < 0) {
1090         dev_err(&client->dev, "Failed to register IIO device\n");
1091         return ret;
1092     }
1093 
1094     return 0;
1095 }
1096 
1097 static int ads1015_remove(struct i2c_client *client)
1098 {
1099     struct iio_dev *indio_dev = i2c_get_clientdata(client);
1100     struct ads1015_data *data = iio_priv(indio_dev);
1101     int ret;
1102 
1103     iio_device_unregister(indio_dev);
1104 
1105     pm_runtime_disable(&client->dev);
1106     pm_runtime_set_suspended(&client->dev);
1107 
1108     /* power down single shot mode */
1109     ret = ads1015_set_conv_mode(data, ADS1015_SINGLESHOT);
1110     if (ret)
1111         dev_warn(&client->dev, "Failed to power down (%pe)\n",
1112              ERR_PTR(ret));
1113 
1114     return 0;
1115 }
1116 
1117 #ifdef CONFIG_PM
1118 static int ads1015_runtime_suspend(struct device *dev)
1119 {
1120     struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
1121     struct ads1015_data *data = iio_priv(indio_dev);
1122 
1123     return ads1015_set_conv_mode(data, ADS1015_SINGLESHOT);
1124 }
1125 
1126 static int ads1015_runtime_resume(struct device *dev)
1127 {
1128     struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
1129     struct ads1015_data *data = iio_priv(indio_dev);
1130     int ret;
1131 
1132     ret = ads1015_set_conv_mode(data, ADS1015_CONTINUOUS);
1133     if (!ret)
1134         data->conv_invalid = true;
1135 
1136     return ret;
1137 }
1138 #endif
1139 
1140 static const struct dev_pm_ops ads1015_pm_ops = {
1141     SET_RUNTIME_PM_OPS(ads1015_runtime_suspend,
1142                ads1015_runtime_resume, NULL)
1143 };
1144 
1145 static const struct ads1015_chip_data ads1015_data = {
1146     .channels   = ads1015_channels,
1147     .num_channels   = ARRAY_SIZE(ads1015_channels),
1148     .info       = &ads1015_info,
1149     .data_rate  = ads1015_data_rate,
1150     .data_rate_len  = ARRAY_SIZE(ads1015_data_rate),
1151     .scale      = ads1015_scale,
1152     .scale_len  = ARRAY_SIZE(ads1015_scale),
1153     .has_comparator = true,
1154 };
1155 
1156 static const struct ads1015_chip_data ads1115_data = {
1157     .channels   = ads1115_channels,
1158     .num_channels   = ARRAY_SIZE(ads1115_channels),
1159     .info       = &ads1015_info,
1160     .data_rate  = ads1115_data_rate,
1161     .data_rate_len  = ARRAY_SIZE(ads1115_data_rate),
1162     .scale      = ads1115_scale,
1163     .scale_len  = ARRAY_SIZE(ads1115_scale),
1164     .has_comparator = true,
1165 };
1166 
1167 static const struct ads1015_chip_data tla2024_data = {
1168     .channels   = tla2024_channels,
1169     .num_channels   = ARRAY_SIZE(tla2024_channels),
1170     .info       = &tla2024_info,
1171     .data_rate  = ads1015_data_rate,
1172     .data_rate_len  = ARRAY_SIZE(ads1015_data_rate),
1173     .scale      = ads1015_scale,
1174     .scale_len  = ARRAY_SIZE(ads1015_scale),
1175     .has_comparator = false,
1176 };
1177 
1178 static const struct i2c_device_id ads1015_id[] = {
1179     { "ads1015", (kernel_ulong_t)&ads1015_data },
1180     { "ads1115", (kernel_ulong_t)&ads1115_data },
1181     { "tla2024", (kernel_ulong_t)&tla2024_data },
1182     {}
1183 };
1184 MODULE_DEVICE_TABLE(i2c, ads1015_id);
1185 
1186 static const struct of_device_id ads1015_of_match[] = {
1187     { .compatible = "ti,ads1015", .data = &ads1015_data },
1188     { .compatible = "ti,ads1115", .data = &ads1115_data },
1189     { .compatible = "ti,tla2024", .data = &tla2024_data },
1190     {}
1191 };
1192 MODULE_DEVICE_TABLE(of, ads1015_of_match);
1193 
1194 static struct i2c_driver ads1015_driver = {
1195     .driver = {
1196         .name = ADS1015_DRV_NAME,
1197         .of_match_table = ads1015_of_match,
1198         .pm = &ads1015_pm_ops,
1199     },
1200     .probe      = ads1015_probe,
1201     .remove     = ads1015_remove,
1202     .id_table   = ads1015_id,
1203 };
1204 
1205 module_i2c_driver(ads1015_driver);
1206 
1207 MODULE_AUTHOR("Daniel Baluta <daniel.baluta@intel.com>");
1208 MODULE_DESCRIPTION("Texas Instruments ADS1015 ADC driver");
1209 MODULE_LICENSE("GPL v2");
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