iio/adc/stx104.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * IIO driver for the Apex Embedded Systems STX104
0004  * Copyright (C) 2016 William Breathitt Gray
0005  */
0006 #include <linux/bitops.h>
0007 #include <linux/device.h>
0008 #include <linux/errno.h>
0009 #include <linux/gpio/driver.h>
0010 #include <linux/iio/iio.h>
0011 #include <linux/iio/types.h>
0012 #include <linux/io.h>
0013 #include <linux/ioport.h>
0014 #include <linux/isa.h>
0015 #include <linux/kernel.h>
0016 #include <linux/module.h>
0017 #include <linux/moduleparam.h>
0018 #include <linux/spinlock.h>
0019 #include <linux/types.h>
0020
0021 #define STX104_OUT_CHAN(chan) {             \
0022     .type = IIO_VOLTAGE,                \
0023     .channel = chan,                \
0024     .info_mask_separate = BIT(IIO_CHAN_INFO_RAW),   \
0025     .indexed = 1,                   \
0026     .output = 1                 \
0027 }
0028 #define STX104_IN_CHAN(chan, diff) {                    \
0029     .type = IIO_VOLTAGE,                        \
0030     .channel = chan,                        \
0031     .channel2 = chan,                       \
0032     .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_HARDWAREGAIN) |   \
0033         BIT(IIO_CHAN_INFO_OFFSET) | BIT(IIO_CHAN_INFO_SCALE),   \
0034     .info_mask_separate = BIT(IIO_CHAN_INFO_RAW),           \
0035     .indexed = 1,                           \
0036     .differential = diff                        \
0037 }
0038
0039 #define STX104_NUM_OUT_CHAN 2
0040
0041 #define STX104_EXTENT 16
0042
0043 static unsigned int base[max_num_isa_dev(STX104_EXTENT)];
0044 static unsigned int num_stx104;
0045 module_param_hw_array(base, uint, ioport, &num_stx104, 0);
0046 MODULE_PARM_DESC(base, "Apex Embedded Systems STX104 base addresses");
0047
0048 /**
0049  * struct stx104_reg - device register structure
0050  * @ssr_ad: Software Strobe Register and ADC Data
0051  * @achan:  ADC Channel
0052  * @dio:    Digital I/O
0053  * @dac:    DAC Channels
0054  * @cir_asr:    Clear Interrupts and ADC Status
0055  * @acr:    ADC Control
0056  * @pccr_fsh:   Pacer Clock Control and FIFO Status MSB
0057  * @acfg:   ADC Configuration
0058  */
0059 struct stx104_reg {
0060     u16 ssr_ad;
0061     u8 achan;
0062     u8 dio;
0063     u16 dac[2];
0064     u8 cir_asr;
0065     u8 acr;
0066     u8 pccr_fsh;
0067     u8 acfg;
0068 };
0069
0070 /**
0071  * struct stx104_iio - IIO device private data structure
0072  * @chan_out_states:    channels' output states
0073  * @reg:        I/O address offset for the device registers
0074  */
0075 struct stx104_iio {
0076     unsigned int chan_out_states[STX104_NUM_OUT_CHAN];
0077     struct stx104_reg __iomem *reg;
0078 };
0079
0080 /**
0081  * struct stx104_gpio - GPIO device private data structure
0082  * @chip:   instance of the gpio_chip
0083  * @lock:   synchronization lock to prevent I/O race conditions
0084  * @base:   base port address of the GPIO device
0085  * @out_state:  output bits state
0086  */
0087 struct stx104_gpio {
0088     struct gpio_chip chip;
0089     spinlock_t lock;
0090     u8 __iomem *base;
0091     unsigned int out_state;
0092 };
0093
0094 static int stx104_read_raw(struct iio_dev *indio_dev,
0095     struct iio_chan_spec const *chan, int *val, int *val2, long mask)
0096 {
0097     struct stx104_iio *const priv = iio_priv(indio_dev);
0098     struct stx104_reg __iomem *const reg = priv->reg;
0099     unsigned int adc_config;
0100     int adbu;
0101     int gain;
0102
0103     switch (mask) {
0104     case IIO_CHAN_INFO_HARDWAREGAIN:
0105         /* get gain configuration */
0106         adc_config = ioread8(&reg->acfg);
0107         gain = adc_config & 0x3;
0108
0109         *val = 1 << gain;
0110         return IIO_VAL_INT;
0111     case IIO_CHAN_INFO_RAW:
0112         if (chan->output) {
0113             *val = priv->chan_out_states[chan->channel];
0114             return IIO_VAL_INT;
0115         }
0116
0117         /* select ADC channel */
0118         iowrite8(chan->channel | (chan->channel << 4), &reg->achan);
0119
0120         /* trigger ADC sample capture by writing to the 8-bit
0121          * Software Strobe Register and wait for completion
0122          */
0123         iowrite8(0, &reg->ssr_ad);
0124         while (ioread8(&reg->cir_asr) & BIT(7));
0125
0126         *val = ioread16(&reg->ssr_ad);
0127         return IIO_VAL_INT;
0128     case IIO_CHAN_INFO_OFFSET:
0129         /* get ADC bipolar/unipolar configuration */
0130         adc_config = ioread8(&reg->acfg);
0131         adbu = !(adc_config & BIT(2));
0132
0133         *val = -32768 * adbu;
0134         return IIO_VAL_INT;
0135     case IIO_CHAN_INFO_SCALE:
0136         /* get ADC bipolar/unipolar and gain configuration */
0137         adc_config = ioread8(&reg->acfg);
0138         adbu = !(adc_config & BIT(2));
0139         gain = adc_config & 0x3;
0140
0141         *val = 5;
0142         *val2 = 15 - adbu + gain;
0143         return IIO_VAL_FRACTIONAL_LOG2;
0144     }
0145
0146     return -EINVAL;
0147 }
0148
0149 static int stx104_write_raw(struct iio_dev *indio_dev,
0150     struct iio_chan_spec const *chan, int val, int val2, long mask)
0151 {
0152     struct stx104_iio *const priv = iio_priv(indio_dev);
0153
0154     switch (mask) {
0155     case IIO_CHAN_INFO_HARDWAREGAIN:
0156         /* Only four gain states (x1, x2, x4, x8) */
0157         switch (val) {
0158         case 1:
0159             iowrite8(0, &priv->reg->acfg);
0160             break;
0161         case 2:
0162             iowrite8(1, &priv->reg->acfg);
0163             break;
0164         case 4:
0165             iowrite8(2, &priv->reg->acfg);
0166             break;
0167         case 8:
0168             iowrite8(3, &priv->reg->acfg);
0169             break;
0170         default:
0171             return -EINVAL;
0172         }
0173
0174         return 0;
0175     case IIO_CHAN_INFO_RAW:
0176         if (chan->output) {
0177             /* DAC can only accept up to a 16-bit value */
0178             if ((unsigned int)val > 65535)
0179                 return -EINVAL;
0180
0181             priv->chan_out_states[chan->channel] = val;
0182             iowrite16(val, &priv->reg->dac[chan->channel]);
0183
0184             return 0;
0185         }
0186         return -EINVAL;
0187     }
0188
0189     return -EINVAL;
0190 }
0191
0192 static const struct iio_info stx104_info = {
0193     .read_raw = stx104_read_raw,
0194     .write_raw = stx104_write_raw
0195 };
0196
0197 /* single-ended input channels configuration */
0198 static const struct iio_chan_spec stx104_channels_sing[] = {
0199     STX104_OUT_CHAN(0), STX104_OUT_CHAN(1),
0200     STX104_IN_CHAN(0, 0), STX104_IN_CHAN(1, 0), STX104_IN_CHAN(2, 0),
0201     STX104_IN_CHAN(3, 0), STX104_IN_CHAN(4, 0), STX104_IN_CHAN(5, 0),
0202     STX104_IN_CHAN(6, 0), STX104_IN_CHAN(7, 0), STX104_IN_CHAN(8, 0),
0203     STX104_IN_CHAN(9, 0), STX104_IN_CHAN(10, 0), STX104_IN_CHAN(11, 0),
0204     STX104_IN_CHAN(12, 0), STX104_IN_CHAN(13, 0), STX104_IN_CHAN(14, 0),
0205     STX104_IN_CHAN(15, 0)
0206 };
0207 /* differential input channels configuration */
0208 static const struct iio_chan_spec stx104_channels_diff[] = {
0209     STX104_OUT_CHAN(0), STX104_OUT_CHAN(1),
0210     STX104_IN_CHAN(0, 1), STX104_IN_CHAN(1, 1), STX104_IN_CHAN(2, 1),
0211     STX104_IN_CHAN(3, 1), STX104_IN_CHAN(4, 1), STX104_IN_CHAN(5, 1),
0212     STX104_IN_CHAN(6, 1), STX104_IN_CHAN(7, 1)
0213 };
0214
0215 static int stx104_gpio_get_direction(struct gpio_chip *chip,
0216     unsigned int offset)
0217 {
0218     /* GPIO 0-3 are input only, while the rest are output only */
0219     if (offset < 4)
0220         return 1;
0221
0222     return 0;
0223 }
0224
0225 static int stx104_gpio_direction_input(struct gpio_chip *chip,
0226     unsigned int offset)
0227 {
0228     if (offset >= 4)
0229         return -EINVAL;
0230
0231     return 0;
0232 }
0233
0234 static int stx104_gpio_direction_output(struct gpio_chip *chip,
0235     unsigned int offset, int value)
0236 {
0237     if (offset < 4)
0238         return -EINVAL;
0239
0240     chip->set(chip, offset, value);
0241     return 0;
0242 }
0243
0244 static int stx104_gpio_get(struct gpio_chip *chip, unsigned int offset)
0245 {
0246     struct stx104_gpio *const stx104gpio = gpiochip_get_data(chip);
0247
0248     if (offset >= 4)
0249         return -EINVAL;
0250
0251     return !!(ioread8(stx104gpio->base) & BIT(offset));
0252 }
0253
0254 static int stx104_gpio_get_multiple(struct gpio_chip *chip, unsigned long *mask,
0255     unsigned long *bits)
0256 {
0257     struct stx104_gpio *const stx104gpio = gpiochip_get_data(chip);
0258
0259     *bits = ioread8(stx104gpio->base);
0260
0261     return 0;
0262 }
0263
0264 static void stx104_gpio_set(struct gpio_chip *chip, unsigned int offset,
0265     int value)
0266 {
0267     struct stx104_gpio *const stx104gpio = gpiochip_get_data(chip);
0268     const unsigned int mask = BIT(offset) >> 4;
0269     unsigned long flags;
0270
0271     if (offset < 4)
0272         return;
0273
0274     spin_lock_irqsave(&stx104gpio->lock, flags);
0275
0276     if (value)
0277         stx104gpio->out_state |= mask;
0278     else
0279         stx104gpio->out_state &= ~mask;
0280
0281     iowrite8(stx104gpio->out_state, stx104gpio->base);
0282
0283     spin_unlock_irqrestore(&stx104gpio->lock, flags);
0284 }
0285
0286 #define STX104_NGPIO 8
0287 static const char *stx104_names[STX104_NGPIO] = {
0288     "DIN0", "DIN1", "DIN2", "DIN3", "DOUT0", "DOUT1", "DOUT2", "DOUT3"
0289 };
0290
0291 static void stx104_gpio_set_multiple(struct gpio_chip *chip,
0292     unsigned long *mask, unsigned long *bits)
0293 {
0294     struct stx104_gpio *const stx104gpio = gpiochip_get_data(chip);
0295     unsigned long flags;
0296
0297     /* verify masked GPIO are output */
0298     if (!(*mask & 0xF0))
0299         return;
0300
0301     *mask >>= 4;
0302     *bits >>= 4;
0303
0304     spin_lock_irqsave(&stx104gpio->lock, flags);
0305
0306     stx104gpio->out_state &= ~*mask;
0307     stx104gpio->out_state |= *mask & *bits;
0308     iowrite8(stx104gpio->out_state, stx104gpio->base);
0309
0310     spin_unlock_irqrestore(&stx104gpio->lock, flags);
0311 }
0312
0313 static int stx104_probe(struct device *dev, unsigned int id)
0314 {
0315     struct iio_dev *indio_dev;
0316     struct stx104_iio *priv;
0317     struct stx104_gpio *stx104gpio;
0318     int err;
0319
0320     indio_dev = devm_iio_device_alloc(dev, sizeof(*priv));
0321     if (!indio_dev)
0322         return -ENOMEM;
0323
0324     stx104gpio = devm_kzalloc(dev, sizeof(*stx104gpio), GFP_KERNEL);
0325     if (!stx104gpio)
0326         return -ENOMEM;
0327
0328     if (!devm_request_region(dev, base[id], STX104_EXTENT,
0329         dev_name(dev))) {
0330         dev_err(dev, "Unable to lock port addresses (0x%X-0x%X)\n",
0331             base[id], base[id] + STX104_EXTENT);
0332         return -EBUSY;
0333     }
0334
0335     priv = iio_priv(indio_dev);
0336     priv->reg = devm_ioport_map(dev, base[id], STX104_EXTENT);
0337     if (!priv->reg)
0338         return -ENOMEM;
0339
0340     indio_dev->info = &stx104_info;
0341     indio_dev->modes = INDIO_DIRECT_MODE;
0342
0343     /* determine if differential inputs */
0344     if (ioread8(&priv->reg->cir_asr) & BIT(5)) {
0345         indio_dev->num_channels = ARRAY_SIZE(stx104_channels_diff);
0346         indio_dev->channels = stx104_channels_diff;
0347     } else {
0348         indio_dev->num_channels = ARRAY_SIZE(stx104_channels_sing);
0349         indio_dev->channels = stx104_channels_sing;
0350     }
0351
0352     indio_dev->name = dev_name(dev);
0353
0354     /* configure device for software trigger operation */
0355     iowrite8(0, &priv->reg->acr);
0356
0357     /* initialize gain setting to x1 */
0358     iowrite8(0, &priv->reg->acfg);
0359
0360     /* initialize DAC output to 0V */
0361     iowrite16(0, &priv->reg->dac[0]);
0362     iowrite16(0, &priv->reg->dac[1]);
0363
0364     stx104gpio->chip.label = dev_name(dev);
0365     stx104gpio->chip.parent = dev;
0366     stx104gpio->chip.owner = THIS_MODULE;
0367     stx104gpio->chip.base = -1;
0368     stx104gpio->chip.ngpio = STX104_NGPIO;
0369     stx104gpio->chip.names = stx104_names;
0370     stx104gpio->chip.get_direction = stx104_gpio_get_direction;
0371     stx104gpio->chip.direction_input = stx104_gpio_direction_input;
0372     stx104gpio->chip.direction_output = stx104_gpio_direction_output;
0373     stx104gpio->chip.get = stx104_gpio_get;
0374     stx104gpio->chip.get_multiple = stx104_gpio_get_multiple;
0375     stx104gpio->chip.set = stx104_gpio_set;
0376     stx104gpio->chip.set_multiple = stx104_gpio_set_multiple;
0377     stx104gpio->base = &priv->reg->dio;
0378     stx104gpio->out_state = 0x0;
0379
0380     spin_lock_init(&stx104gpio->lock);
0381
0382     err = devm_gpiochip_add_data(dev, &stx104gpio->chip, stx104gpio);
0383     if (err) {
0384         dev_err(dev, "GPIO registering failed (%d)\n", err);
0385         return err;
0386     }
0387
0388     return devm_iio_device_register(dev, indio_dev);
0389 }
0390
0391 static struct isa_driver stx104_driver = {
0392     .probe = stx104_probe,
0393     .driver = {
0394         .name = "stx104"
0395     },
0396 };
0397
0398 module_isa_driver(stx104_driver, num_stx104);
0399
0400 MODULE_AUTHOR("William Breathitt Gray <vilhelm.gray@gmail.com>");
0401 MODULE_DESCRIPTION("Apex Embedded Systems STX104 IIO driver");
0402 MODULE_LICENSE("GPL v2");