iio/adc/stmpe-adc.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  *  STMicroelectronics STMPE811 IIO ADC Driver
0004  *
0005  *  4 channel, 10/12-bit ADC
0006  *
0007  *  Copyright (C) 2013-2018 Toradex AG <stefan.agner@toradex.com>
0008  */
0009
0010 #include <linux/completion.h>
0011 #include <linux/err.h>
0012 #include <linux/iio/iio.h>
0013 #include <linux/interrupt.h>
0014 #include <linux/kernel.h>
0015 #include <linux/mfd/stmpe.h>
0016 #include <linux/module.h>
0017 #include <linux/of_platform.h>
0018 #include <linux/platform_device.h>
0019 #include <linux/device.h>
0020
0021 #define STMPE_REG_INT_STA       0x0B
0022 #define STMPE_REG_ADC_INT_EN        0x0E
0023 #define STMPE_REG_ADC_INT_STA       0x0F
0024
0025 #define STMPE_REG_ADC_CTRL1     0x20
0026 #define STMPE_REG_ADC_CTRL2     0x21
0027 #define STMPE_REG_ADC_CAPT      0x22
0028 #define STMPE_REG_ADC_DATA_CH(channel)  (0x30 + 2 * (channel))
0029
0030 #define STMPE_REG_TEMP_CTRL     0x60
0031 #define STMPE_TEMP_CTRL_ENABLE      BIT(0)
0032 #define STMPE_TEMP_CTRL_ACQ     BIT(1)
0033 #define STMPE_TEMP_CTRL_THRES_EN    BIT(3)
0034 #define STMPE_START_ONE_TEMP_CONV   (STMPE_TEMP_CTRL_ENABLE | \
0035                     STMPE_TEMP_CTRL_ACQ | \
0036                     STMPE_TEMP_CTRL_THRES_EN)
0037 #define STMPE_REG_TEMP_DATA     0x61
0038 #define STMPE_REG_TEMP_TH       0x63
0039 #define STMPE_ADC_LAST_NR       7
0040 #define STMPE_TEMP_CHANNEL      (STMPE_ADC_LAST_NR + 1)
0041
0042 #define STMPE_ADC_CH(channel)       ((1 << (channel)) & 0xff)
0043
0044 #define STMPE_ADC_TIMEOUT       msecs_to_jiffies(1000)
0045
0046 struct stmpe_adc {
0047     struct stmpe *stmpe;
0048     struct clk *clk;
0049     struct device *dev;
0050     struct mutex lock;
0051
0052     /* We are allocating plus one for the temperature channel */
0053     struct iio_chan_spec stmpe_adc_iio_channels[STMPE_ADC_LAST_NR + 2];
0054
0055     struct completion completion;
0056
0057     u8 channel;
0058     u32 value;
0059 };
0060
0061 static int stmpe_read_voltage(struct stmpe_adc *info,
0062         struct iio_chan_spec const *chan, int *val)
0063 {
0064     unsigned long ret;
0065
0066     mutex_lock(&info->lock);
0067
0068     reinit_completion(&info->completion);
0069
0070     info->channel = (u8)chan->channel;
0071
0072     if (info->channel > STMPE_ADC_LAST_NR) {
0073         mutex_unlock(&info->lock);
0074         return -EINVAL;
0075     }
0076
0077     stmpe_reg_write(info->stmpe, STMPE_REG_ADC_CAPT,
0078             STMPE_ADC_CH(info->channel));
0079
0080     ret = wait_for_completion_timeout(&info->completion, STMPE_ADC_TIMEOUT);
0081
0082     if (ret == 0) {
0083         stmpe_reg_write(info->stmpe, STMPE_REG_ADC_INT_STA,
0084                 STMPE_ADC_CH(info->channel));
0085         mutex_unlock(&info->lock);
0086         return -ETIMEDOUT;
0087     }
0088
0089     *val = info->value;
0090
0091     mutex_unlock(&info->lock);
0092
0093     return 0;
0094 }
0095
0096 static int stmpe_read_temp(struct stmpe_adc *info,
0097         struct iio_chan_spec const *chan, int *val)
0098 {
0099     unsigned long ret;
0100
0101     mutex_lock(&info->lock);
0102
0103     reinit_completion(&info->completion);
0104
0105     info->channel = (u8)chan->channel;
0106
0107     if (info->channel != STMPE_TEMP_CHANNEL) {
0108         mutex_unlock(&info->lock);
0109         return -EINVAL;
0110     }
0111
0112     stmpe_reg_write(info->stmpe, STMPE_REG_TEMP_CTRL,
0113             STMPE_START_ONE_TEMP_CONV);
0114
0115     ret = wait_for_completion_timeout(&info->completion, STMPE_ADC_TIMEOUT);
0116
0117     if (ret == 0) {
0118         mutex_unlock(&info->lock);
0119         return -ETIMEDOUT;
0120     }
0121
0122     /*
0123      * absolute temp = +V3.3 * value /7.51 [K]
0124      * scale to [milli °C]
0125      */
0126     *val = ((449960l * info->value) / 1024l) - 273150;
0127
0128     mutex_unlock(&info->lock);
0129
0130     return 0;
0131 }
0132
0133 static int stmpe_read_raw(struct iio_dev *indio_dev,
0134               struct iio_chan_spec const *chan,
0135               int *val,
0136               int *val2,
0137               long mask)
0138 {
0139     struct stmpe_adc *info = iio_priv(indio_dev);
0140     long ret;
0141
0142     switch (mask) {
0143     case IIO_CHAN_INFO_RAW:
0144     case IIO_CHAN_INFO_PROCESSED:
0145
0146         switch (chan->type) {
0147         case IIO_VOLTAGE:
0148             ret = stmpe_read_voltage(info, chan, val);
0149             break;
0150
0151         case IIO_TEMP:
0152             ret = stmpe_read_temp(info, chan, val);
0153             break;
0154         default:
0155             return -EINVAL;
0156         }
0157
0158         if (ret < 0)
0159             return ret;
0160
0161         return IIO_VAL_INT;
0162
0163     case IIO_CHAN_INFO_SCALE:
0164         *val = 3300;
0165         *val2 = info->stmpe->mod_12b ? 12 : 10;
0166         return IIO_VAL_FRACTIONAL_LOG2;
0167
0168     default:
0169         break;
0170     }
0171
0172     return -EINVAL;
0173 }
0174
0175 static irqreturn_t stmpe_adc_isr(int irq, void *dev_id)
0176 {
0177     struct stmpe_adc *info = (struct stmpe_adc *)dev_id;
0178     __be16 data;
0179
0180     if (info->channel <= STMPE_ADC_LAST_NR) {
0181         int int_sta;
0182
0183         int_sta = stmpe_reg_read(info->stmpe, STMPE_REG_ADC_INT_STA);
0184
0185         /* Is the interrupt relevant */
0186         if (!(int_sta & STMPE_ADC_CH(info->channel)))
0187             return IRQ_NONE;
0188
0189         /* Read value */
0190         stmpe_block_read(info->stmpe,
0191             STMPE_REG_ADC_DATA_CH(info->channel), 2, (u8 *) &data);
0192
0193         stmpe_reg_write(info->stmpe, STMPE_REG_ADC_INT_STA, int_sta);
0194     } else if (info->channel == STMPE_TEMP_CHANNEL) {
0195         /* Read value */
0196         stmpe_block_read(info->stmpe, STMPE_REG_TEMP_DATA, 2,
0197                 (u8 *) &data);
0198     } else {
0199         return IRQ_NONE;
0200     }
0201
0202     info->value = (u32) be16_to_cpu(data);
0203     complete(&info->completion);
0204
0205     return IRQ_HANDLED;
0206 }
0207
0208 static const struct iio_info stmpe_adc_iio_info = {
0209     .read_raw = &stmpe_read_raw,
0210 };
0211
0212 static void stmpe_adc_voltage_chan(struct iio_chan_spec *ics, int chan)
0213 {
0214     ics->type = IIO_VOLTAGE;
0215     ics->info_mask_separate = BIT(IIO_CHAN_INFO_RAW);
0216     ics->info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE);
0217     ics->indexed = 1;
0218     ics->channel = chan;
0219 }
0220
0221 static void stmpe_adc_temp_chan(struct iio_chan_spec *ics, int chan)
0222 {
0223     ics->type = IIO_TEMP;
0224     ics->info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED);
0225     ics->indexed = 1;
0226     ics->channel = chan;
0227 }
0228
0229 static int stmpe_adc_init_hw(struct stmpe_adc *adc)
0230 {
0231     int ret;
0232     struct stmpe *stmpe = adc->stmpe;
0233
0234     ret = stmpe_enable(stmpe, STMPE_BLOCK_ADC);
0235     if (ret) {
0236         dev_err(stmpe->dev, "Could not enable clock for ADC\n");
0237         return ret;
0238     }
0239
0240     ret = stmpe811_adc_common_init(stmpe);
0241     if (ret) {
0242         stmpe_disable(stmpe, STMPE_BLOCK_ADC);
0243         return ret;
0244     }
0245
0246     /* use temp irq for each conversion completion */
0247     stmpe_reg_write(stmpe, STMPE_REG_TEMP_TH, 0);
0248     stmpe_reg_write(stmpe, STMPE_REG_TEMP_TH + 1, 0);
0249
0250     return 0;
0251 }
0252
0253 static int stmpe_adc_probe(struct platform_device *pdev)
0254 {
0255     struct iio_dev *indio_dev;
0256     struct stmpe_adc *info;
0257     struct device_node *np;
0258     u32 norequest_mask = 0;
0259     unsigned long bits;
0260     int irq_temp, irq_adc;
0261     int num_chan = 0;
0262     int i = 0;
0263     int ret;
0264
0265     irq_adc = platform_get_irq_byname(pdev, "STMPE_ADC");
0266     if (irq_adc < 0)
0267         return irq_adc;
0268
0269     indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(struct stmpe_adc));
0270     if (!indio_dev) {
0271         dev_err(&pdev->dev, "failed allocating iio device\n");
0272         return -ENOMEM;
0273     }
0274
0275     info = iio_priv(indio_dev);
0276     mutex_init(&info->lock);
0277
0278     init_completion(&info->completion);
0279     ret = devm_request_threaded_irq(&pdev->dev, irq_adc, NULL,
0280                     stmpe_adc_isr, IRQF_ONESHOT,
0281                     "stmpe-adc", info);
0282     if (ret < 0) {
0283         dev_err(&pdev->dev, "failed requesting irq, irq = %d\n",
0284                 irq_adc);
0285         return ret;
0286     }
0287
0288     irq_temp = platform_get_irq_byname(pdev, "STMPE_TEMP_SENS");
0289     if (irq_temp >= 0) {
0290         ret = devm_request_threaded_irq(&pdev->dev, irq_temp, NULL,
0291                         stmpe_adc_isr, IRQF_ONESHOT,
0292                         "stmpe-adc", info);
0293         if (ret < 0)
0294             dev_warn(&pdev->dev, "failed requesting irq for"
0295                  " temp sensor, irq = %d\n", irq_temp);
0296     }
0297
0298     platform_set_drvdata(pdev, indio_dev);
0299
0300     indio_dev->name     = dev_name(&pdev->dev);
0301     indio_dev->info     = &stmpe_adc_iio_info;
0302     indio_dev->modes    = INDIO_DIRECT_MODE;
0303
0304     info->stmpe = dev_get_drvdata(pdev->dev.parent);
0305
0306     np = pdev->dev.of_node;
0307
0308     if (!np)
0309         dev_err(&pdev->dev, "no device tree node found\n");
0310
0311     of_property_read_u32(np, "st,norequest-mask", &norequest_mask);
0312
0313     bits = norequest_mask;
0314     for_each_clear_bit(i, &bits, (STMPE_ADC_LAST_NR + 1)) {
0315         stmpe_adc_voltage_chan(&info->stmpe_adc_iio_channels[num_chan], i);
0316         num_chan++;
0317     }
0318     stmpe_adc_temp_chan(&info->stmpe_adc_iio_channels[num_chan], i);
0319     num_chan++;
0320     indio_dev->channels = info->stmpe_adc_iio_channels;
0321     indio_dev->num_channels = num_chan;
0322
0323     ret = stmpe_adc_init_hw(info);
0324     if (ret)
0325         return ret;
0326
0327     stmpe_reg_write(info->stmpe, STMPE_REG_ADC_INT_EN,
0328             ~(norequest_mask & 0xFF));
0329
0330     stmpe_reg_write(info->stmpe, STMPE_REG_ADC_INT_STA,
0331             ~(norequest_mask & 0xFF));
0332
0333     return devm_iio_device_register(&pdev->dev, indio_dev);
0334 }
0335
0336 static int stmpe_adc_resume(struct device *dev)
0337 {
0338     struct iio_dev *indio_dev = dev_get_drvdata(dev);
0339     struct stmpe_adc *info = iio_priv(indio_dev);
0340
0341     stmpe_adc_init_hw(info);
0342
0343     return 0;
0344 }
0345
0346 static DEFINE_SIMPLE_DEV_PM_OPS(stmpe_adc_pm_ops, NULL, stmpe_adc_resume);
0347
0348 static const struct of_device_id stmpe_adc_ids[] = {
0349     { .compatible = "st,stmpe-adc", },
0350     { },
0351 };
0352 MODULE_DEVICE_TABLE(of, stmpe_adc_ids);
0353
0354 static struct platform_driver stmpe_adc_driver = {
0355     .probe      = stmpe_adc_probe,
0356     .driver     = {
0357         .name   = "stmpe-adc",
0358         .pm = pm_sleep_ptr(&stmpe_adc_pm_ops),
0359         .of_match_table = stmpe_adc_ids,
0360     },
0361 };
0362 module_platform_driver(stmpe_adc_driver);
0363
0364 MODULE_AUTHOR("Stefan Agner <stefan.agner@toradex.com>");
0365 MODULE_DESCRIPTION("STMPEXXX ADC driver");
0366 MODULE_LICENSE("GPL v2");
0367 MODULE_ALIAS("platform:stmpe-adc");