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0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * This file is part of STM32 DFSDM driver
0004  *
0005  * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
0006  * Author(s): Arnaud Pouliquen <arnaud.pouliquen@st.com>.
0007  */
0008 
0009 #ifndef MDF_STM32_DFSDM__H
0010 #define MDF_STM32_DFSDM__H
0011 
0012 #include <linux/bitfield.h>
0013 
0014 /*
0015  * STM32 DFSDM - global register map
0016  * ________________________________________________________
0017  * | Offset |                 Registers block             |
0018  * --------------------------------------------------------
0019  * | 0x000  |      CHANNEL 0 + COMMON CHANNEL FIELDS      |
0020  * --------------------------------------------------------
0021  * | 0x020  |                CHANNEL 1                    |
0022  * --------------------------------------------------------
0023  * | ...    |                .....                        |
0024  * --------------------------------------------------------
0025  * | 0x0E0  |                CHANNEL 7                    |
0026  * --------------------------------------------------------
0027  * | 0x100  |      FILTER  0 + COMMON  FILTER FIELDs      |
0028  * --------------------------------------------------------
0029  * | 0x200  |                FILTER  1                    |
0030  * --------------------------------------------------------
0031  * | 0x300  |                FILTER  2                    |
0032  * --------------------------------------------------------
0033  * | 0x400  |                FILTER  3                    |
0034  * --------------------------------------------------------
0035  */
0036 
0037 /*
0038  * Channels register definitions
0039  */
0040 #define DFSDM_CHCFGR1(y)  ((y) * 0x20 + 0x00)
0041 #define DFSDM_CHCFGR2(y)  ((y) * 0x20 + 0x04)
0042 #define DFSDM_AWSCDR(y)   ((y) * 0x20 + 0x08)
0043 #define DFSDM_CHWDATR(y)  ((y) * 0x20 + 0x0C)
0044 #define DFSDM_CHDATINR(y) ((y) * 0x20 + 0x10)
0045 
0046 /* CHCFGR1: Channel configuration register 1 */
0047 #define DFSDM_CHCFGR1_SITP_MASK     GENMASK(1, 0)
0048 #define DFSDM_CHCFGR1_SITP(v)       FIELD_PREP(DFSDM_CHCFGR1_SITP_MASK, v)
0049 #define DFSDM_CHCFGR1_SPICKSEL_MASK GENMASK(3, 2)
0050 #define DFSDM_CHCFGR1_SPICKSEL(v)   FIELD_PREP(DFSDM_CHCFGR1_SPICKSEL_MASK, v)
0051 #define DFSDM_CHCFGR1_SCDEN_MASK    BIT(5)
0052 #define DFSDM_CHCFGR1_SCDEN(v)      FIELD_PREP(DFSDM_CHCFGR1_SCDEN_MASK, v)
0053 #define DFSDM_CHCFGR1_CKABEN_MASK   BIT(6)
0054 #define DFSDM_CHCFGR1_CKABEN(v)     FIELD_PREP(DFSDM_CHCFGR1_CKABEN_MASK, v)
0055 #define DFSDM_CHCFGR1_CHEN_MASK     BIT(7)
0056 #define DFSDM_CHCFGR1_CHEN(v)       FIELD_PREP(DFSDM_CHCFGR1_CHEN_MASK, v)
0057 #define DFSDM_CHCFGR1_CHINSEL_MASK  BIT(8)
0058 #define DFSDM_CHCFGR1_CHINSEL(v)    FIELD_PREP(DFSDM_CHCFGR1_CHINSEL_MASK, v)
0059 #define DFSDM_CHCFGR1_DATMPX_MASK   GENMASK(13, 12)
0060 #define DFSDM_CHCFGR1_DATMPX(v)     FIELD_PREP(DFSDM_CHCFGR1_DATMPX_MASK, v)
0061 #define DFSDM_CHCFGR1_DATPACK_MASK  GENMASK(15, 14)
0062 #define DFSDM_CHCFGR1_DATPACK(v)    FIELD_PREP(DFSDM_CHCFGR1_DATPACK_MASK, v)
0063 #define DFSDM_CHCFGR1_CKOUTDIV_MASK GENMASK(23, 16)
0064 #define DFSDM_CHCFGR1_CKOUTDIV(v)   FIELD_PREP(DFSDM_CHCFGR1_CKOUTDIV_MASK, v)
0065 #define DFSDM_CHCFGR1_CKOUTSRC_MASK BIT(30)
0066 #define DFSDM_CHCFGR1_CKOUTSRC(v)   FIELD_PREP(DFSDM_CHCFGR1_CKOUTSRC_MASK, v)
0067 #define DFSDM_CHCFGR1_DFSDMEN_MASK  BIT(31)
0068 #define DFSDM_CHCFGR1_DFSDMEN(v)    FIELD_PREP(DFSDM_CHCFGR1_DFSDMEN_MASK, v)
0069 
0070 /* CHCFGR2: Channel configuration register 2 */
0071 #define DFSDM_CHCFGR2_DTRBS_MASK    GENMASK(7, 3)
0072 #define DFSDM_CHCFGR2_DTRBS(v)      FIELD_PREP(DFSDM_CHCFGR2_DTRBS_MASK, v)
0073 #define DFSDM_CHCFGR2_OFFSET_MASK   GENMASK(31, 8)
0074 #define DFSDM_CHCFGR2_OFFSET(v)     FIELD_PREP(DFSDM_CHCFGR2_OFFSET_MASK, v)
0075 
0076 /* AWSCDR: Channel analog watchdog and short circuit detector */
0077 #define DFSDM_AWSCDR_SCDT_MASK    GENMASK(7, 0)
0078 #define DFSDM_AWSCDR_SCDT(v)      FIELD_PREP(DFSDM_AWSCDR_SCDT_MASK, v)
0079 #define DFSDM_AWSCDR_BKSCD_MASK   GENMASK(15, 12)
0080 #define DFSDM_AWSCDR_BKSCD(v)     FIELD_PREP(DFSDM_AWSCDR_BKSCD_MASK, v)
0081 #define DFSDM_AWSCDR_AWFOSR_MASK  GENMASK(20, 16)
0082 #define DFSDM_AWSCDR_AWFOSR(v)    FIELD_PREP(DFSDM_AWSCDR_AWFOSR_MASK, v)
0083 #define DFSDM_AWSCDR_AWFORD_MASK  GENMASK(23, 22)
0084 #define DFSDM_AWSCDR_AWFORD(v)    FIELD_PREP(DFSDM_AWSCDR_AWFORD_MASK, v)
0085 
0086 /*
0087  * Filters register definitions
0088  */
0089 #define DFSDM_FILTER_BASE_ADR       0x100
0090 #define DFSDM_FILTER_REG_MASK       0x7F
0091 #define DFSDM_FILTER_X_BASE_ADR(x)  ((x) * 0x80 + DFSDM_FILTER_BASE_ADR)
0092 
0093 #define DFSDM_CR1(x)     (DFSDM_FILTER_X_BASE_ADR(x)  + 0x00)
0094 #define DFSDM_CR2(x)     (DFSDM_FILTER_X_BASE_ADR(x)  + 0x04)
0095 #define DFSDM_ISR(x)     (DFSDM_FILTER_X_BASE_ADR(x)  + 0x08)
0096 #define DFSDM_ICR(x)     (DFSDM_FILTER_X_BASE_ADR(x)  + 0x0C)
0097 #define DFSDM_JCHGR(x)   (DFSDM_FILTER_X_BASE_ADR(x)  + 0x10)
0098 #define DFSDM_FCR(x)     (DFSDM_FILTER_X_BASE_ADR(x)  + 0x14)
0099 #define DFSDM_JDATAR(x)  (DFSDM_FILTER_X_BASE_ADR(x)  + 0x18)
0100 #define DFSDM_RDATAR(x)  (DFSDM_FILTER_X_BASE_ADR(x)  + 0x1C)
0101 #define DFSDM_AWHTR(x)   (DFSDM_FILTER_X_BASE_ADR(x)  + 0x20)
0102 #define DFSDM_AWLTR(x)   (DFSDM_FILTER_X_BASE_ADR(x)  + 0x24)
0103 #define DFSDM_AWSR(x)    (DFSDM_FILTER_X_BASE_ADR(x)  + 0x28)
0104 #define DFSDM_AWCFR(x)   (DFSDM_FILTER_X_BASE_ADR(x)  + 0x2C)
0105 #define DFSDM_EXMAX(x)   (DFSDM_FILTER_X_BASE_ADR(x)  + 0x30)
0106 #define DFSDM_EXMIN(x)   (DFSDM_FILTER_X_BASE_ADR(x)  + 0x34)
0107 #define DFSDM_CNVTIMR(x) (DFSDM_FILTER_X_BASE_ADR(x)  + 0x38)
0108 
0109 /* CR1 Control register 1 */
0110 #define DFSDM_CR1_DFEN_MASK BIT(0)
0111 #define DFSDM_CR1_DFEN(v)   FIELD_PREP(DFSDM_CR1_DFEN_MASK, v)
0112 #define DFSDM_CR1_JSWSTART_MASK BIT(1)
0113 #define DFSDM_CR1_JSWSTART(v)   FIELD_PREP(DFSDM_CR1_JSWSTART_MASK, v)
0114 #define DFSDM_CR1_JSYNC_MASK    BIT(3)
0115 #define DFSDM_CR1_JSYNC(v)  FIELD_PREP(DFSDM_CR1_JSYNC_MASK, v)
0116 #define DFSDM_CR1_JSCAN_MASK    BIT(4)
0117 #define DFSDM_CR1_JSCAN(v)  FIELD_PREP(DFSDM_CR1_JSCAN_MASK, v)
0118 #define DFSDM_CR1_JDMAEN_MASK   BIT(5)
0119 #define DFSDM_CR1_JDMAEN(v) FIELD_PREP(DFSDM_CR1_JDMAEN_MASK, v)
0120 #define DFSDM_CR1_JEXTSEL_MASK  GENMASK(12, 8)
0121 #define DFSDM_CR1_JEXTSEL(v)    FIELD_PREP(DFSDM_CR1_JEXTSEL_MASK, v)
0122 #define DFSDM_CR1_JEXTEN_MASK   GENMASK(14, 13)
0123 #define DFSDM_CR1_JEXTEN(v) FIELD_PREP(DFSDM_CR1_JEXTEN_MASK, v)
0124 #define DFSDM_CR1_RSWSTART_MASK BIT(17)
0125 #define DFSDM_CR1_RSWSTART(v)   FIELD_PREP(DFSDM_CR1_RSWSTART_MASK, v)
0126 #define DFSDM_CR1_RCONT_MASK    BIT(18)
0127 #define DFSDM_CR1_RCONT(v)  FIELD_PREP(DFSDM_CR1_RCONT_MASK, v)
0128 #define DFSDM_CR1_RSYNC_MASK    BIT(19)
0129 #define DFSDM_CR1_RSYNC(v)  FIELD_PREP(DFSDM_CR1_RSYNC_MASK, v)
0130 #define DFSDM_CR1_RDMAEN_MASK   BIT(21)
0131 #define DFSDM_CR1_RDMAEN(v) FIELD_PREP(DFSDM_CR1_RDMAEN_MASK, v)
0132 #define DFSDM_CR1_RCH_MASK  GENMASK(26, 24)
0133 #define DFSDM_CR1_RCH(v)    FIELD_PREP(DFSDM_CR1_RCH_MASK, v)
0134 #define DFSDM_CR1_FAST_MASK BIT(29)
0135 #define DFSDM_CR1_FAST(v)   FIELD_PREP(DFSDM_CR1_FAST_MASK, v)
0136 #define DFSDM_CR1_AWFSEL_MASK   BIT(30)
0137 #define DFSDM_CR1_AWFSEL(v) FIELD_PREP(DFSDM_CR1_AWFSEL_MASK, v)
0138 
0139 /* CR2: Control register 2 */
0140 #define DFSDM_CR2_IE_MASK   GENMASK(6, 0)
0141 #define DFSDM_CR2_IE(v)     FIELD_PREP(DFSDM_CR2_IE_MASK, v)
0142 #define DFSDM_CR2_JEOCIE_MASK   BIT(0)
0143 #define DFSDM_CR2_JEOCIE(v) FIELD_PREP(DFSDM_CR2_JEOCIE_MASK, v)
0144 #define DFSDM_CR2_REOCIE_MASK   BIT(1)
0145 #define DFSDM_CR2_REOCIE(v) FIELD_PREP(DFSDM_CR2_REOCIE_MASK, v)
0146 #define DFSDM_CR2_JOVRIE_MASK   BIT(2)
0147 #define DFSDM_CR2_JOVRIE(v) FIELD_PREP(DFSDM_CR2_JOVRIE_MASK, v)
0148 #define DFSDM_CR2_ROVRIE_MASK   BIT(3)
0149 #define DFSDM_CR2_ROVRIE(v) FIELD_PREP(DFSDM_CR2_ROVRIE_MASK, v)
0150 #define DFSDM_CR2_AWDIE_MASK    BIT(4)
0151 #define DFSDM_CR2_AWDIE(v)  FIELD_PREP(DFSDM_CR2_AWDIE_MASK, v)
0152 #define DFSDM_CR2_SCDIE_MASK    BIT(5)
0153 #define DFSDM_CR2_SCDIE(v)  FIELD_PREP(DFSDM_CR2_SCDIE_MASK, v)
0154 #define DFSDM_CR2_CKABIE_MASK   BIT(6)
0155 #define DFSDM_CR2_CKABIE(v) FIELD_PREP(DFSDM_CR2_CKABIE_MASK, v)
0156 #define DFSDM_CR2_EXCH_MASK GENMASK(15, 8)
0157 #define DFSDM_CR2_EXCH(v)   FIELD_PREP(DFSDM_CR2_EXCH_MASK, v)
0158 #define DFSDM_CR2_AWDCH_MASK    GENMASK(23, 16)
0159 #define DFSDM_CR2_AWDCH(v)  FIELD_PREP(DFSDM_CR2_AWDCH_MASK, v)
0160 
0161 /* ISR: Interrupt status register */
0162 #define DFSDM_ISR_JEOCF_MASK    BIT(0)
0163 #define DFSDM_ISR_JEOCF(v)  FIELD_PREP(DFSDM_ISR_JEOCF_MASK, v)
0164 #define DFSDM_ISR_REOCF_MASK    BIT(1)
0165 #define DFSDM_ISR_REOCF(v)  FIELD_PREP(DFSDM_ISR_REOCF_MASK, v)
0166 #define DFSDM_ISR_JOVRF_MASK    BIT(2)
0167 #define DFSDM_ISR_JOVRF(v)  FIELD_PREP(DFSDM_ISR_JOVRF_MASK, v)
0168 #define DFSDM_ISR_ROVRF_MASK    BIT(3)
0169 #define DFSDM_ISR_ROVRF(v)  FIELD_PREP(DFSDM_ISR_ROVRF_MASK, v)
0170 #define DFSDM_ISR_AWDF_MASK BIT(4)
0171 #define DFSDM_ISR_AWDF(v)   FIELD_PREP(DFSDM_ISR_AWDF_MASK, v)
0172 #define DFSDM_ISR_JCIP_MASK BIT(13)
0173 #define DFSDM_ISR_JCIP(v)   FIELD_PREP(DFSDM_ISR_JCIP_MASK, v)
0174 #define DFSDM_ISR_RCIP_MASK BIT(14)
0175 #define DFSDM_ISR_RCIP(v)   FIELD_PREP(DFSDM_ISR_RCIP, v)
0176 #define DFSDM_ISR_CKABF_MASK    GENMASK(23, 16)
0177 #define DFSDM_ISR_CKABF(v)  FIELD_PREP(DFSDM_ISR_CKABF_MASK, v)
0178 #define DFSDM_ISR_SCDF_MASK GENMASK(31, 24)
0179 #define DFSDM_ISR_SCDF(v)   FIELD_PREP(DFSDM_ISR_SCDF_MASK, v)
0180 
0181 /* ICR: Interrupt flag clear register */
0182 #define DFSDM_ICR_CLRJOVRF_MASK       BIT(2)
0183 #define DFSDM_ICR_CLRJOVRF(v)         FIELD_PREP(DFSDM_ICR_CLRJOVRF_MASK, v)
0184 #define DFSDM_ICR_CLRROVRF_MASK       BIT(3)
0185 #define DFSDM_ICR_CLRROVRF(v)         FIELD_PREP(DFSDM_ICR_CLRROVRF_MASK, v)
0186 #define DFSDM_ICR_CLRCKABF_MASK       GENMASK(23, 16)
0187 #define DFSDM_ICR_CLRCKABF(v)         FIELD_PREP(DFSDM_ICR_CLRCKABF_MASK, v)
0188 #define DFSDM_ICR_CLRCKABF_CH_MASK(y) BIT(16 + (y))
0189 #define DFSDM_ICR_CLRCKABF_CH(v, y)   \
0190                (((v) << (16 + (y))) & DFSDM_ICR_CLRCKABF_CH_MASK(y))
0191 #define DFSDM_ICR_CLRSCDF_MASK        GENMASK(31, 24)
0192 #define DFSDM_ICR_CLRSCDF(v)          FIELD_PREP(DFSDM_ICR_CLRSCDF_MASK, v)
0193 #define DFSDM_ICR_CLRSCDF_CH_MASK(y)  BIT(24 + (y))
0194 #define DFSDM_ICR_CLRSCDF_CH(v, y)    \
0195                    (((v) << (24 + (y))) & DFSDM_ICR_CLRSCDF_MASK(y))
0196 
0197 /* FCR: Filter control register */
0198 #define DFSDM_FCR_IOSR_MASK GENMASK(7, 0)
0199 #define DFSDM_FCR_IOSR(v)   FIELD_PREP(DFSDM_FCR_IOSR_MASK, v)
0200 #define DFSDM_FCR_FOSR_MASK GENMASK(25, 16)
0201 #define DFSDM_FCR_FOSR(v)   FIELD_PREP(DFSDM_FCR_FOSR_MASK, v)
0202 #define DFSDM_FCR_FORD_MASK GENMASK(31, 29)
0203 #define DFSDM_FCR_FORD(v)   FIELD_PREP(DFSDM_FCR_FORD_MASK, v)
0204 
0205 /* RDATAR: Filter data register for regular channel */
0206 #define DFSDM_DATAR_CH_MASK GENMASK(2, 0)
0207 #define DFSDM_DATAR_DATA_OFFSET 8
0208 #define DFSDM_DATAR_DATA_MASK   GENMASK(31, DFSDM_DATAR_DATA_OFFSET)
0209 
0210 /* AWLTR: Filter analog watchdog low threshold register */
0211 #define DFSDM_AWLTR_BKAWL_MASK  GENMASK(3, 0)
0212 #define DFSDM_AWLTR_BKAWL(v)    FIELD_PREP(DFSDM_AWLTR_BKAWL_MASK, v)
0213 #define DFSDM_AWLTR_AWLT_MASK   GENMASK(31, 8)
0214 #define DFSDM_AWLTR_AWLT(v) FIELD_PREP(DFSDM_AWLTR_AWLT_MASK, v)
0215 
0216 /* AWHTR: Filter analog watchdog low threshold register */
0217 #define DFSDM_AWHTR_BKAWH_MASK  GENMASK(3, 0)
0218 #define DFSDM_AWHTR_BKAWH(v)    FIELD_PREP(DFSDM_AWHTR_BKAWH_MASK, v)
0219 #define DFSDM_AWHTR_AWHT_MASK   GENMASK(31, 8)
0220 #define DFSDM_AWHTR_AWHT(v) FIELD_PREP(DFSDM_AWHTR_AWHT_MASK, v)
0221 
0222 /* AWSR: Filter watchdog status register */
0223 #define DFSDM_AWSR_AWLTF_MASK   GENMASK(7, 0)
0224 #define DFSDM_AWSR_AWLTF(v) FIELD_PREP(DFSDM_AWSR_AWLTF_MASK, v)
0225 #define DFSDM_AWSR_AWHTF_MASK   GENMASK(15, 8)
0226 #define DFSDM_AWSR_AWHTF(v) FIELD_PREP(DFSDM_AWSR_AWHTF_MASK, v)
0227 
0228 /* AWCFR: Filter watchdog status register */
0229 #define DFSDM_AWCFR_AWLTF_MASK  GENMASK(7, 0)
0230 #define DFSDM_AWCFR_AWLTF(v)    FIELD_PREP(DFSDM_AWCFR_AWLTF_MASK, v)
0231 #define DFSDM_AWCFR_AWHTF_MASK  GENMASK(15, 8)
0232 #define DFSDM_AWCFR_AWHTF(v)    FIELD_PREP(DFSDM_AWCFR_AWHTF_MASK, v)
0233 
0234 /* DFSDM filter order  */
0235 enum stm32_dfsdm_sinc_order {
0236     DFSDM_FASTSINC_ORDER, /* FastSinc filter type */
0237     DFSDM_SINC1_ORDER,    /* Sinc 1 filter type */
0238     DFSDM_SINC2_ORDER,    /* Sinc 2 filter type */
0239     DFSDM_SINC3_ORDER,    /* Sinc 3 filter type */
0240     DFSDM_SINC4_ORDER,    /* Sinc 4 filter type (N.A. for watchdog) */
0241     DFSDM_SINC5_ORDER,    /* Sinc 5 filter type (N.A. for watchdog) */
0242     DFSDM_NB_SINC_ORDER,
0243 };
0244 
0245 /**
0246  * struct stm32_dfsdm_filter_osr - DFSDM filter settings linked to oversampling
0247  * @iosr: integrator oversampling
0248  * @fosr: filter oversampling
0249  * @rshift: output sample right shift (hardware shift)
0250  * @lshift: output sample left shift (software shift)
0251  * @res: output sample resolution
0252  * @bits: output sample resolution in bits
0253  * @max: output sample maximum positive value
0254  */
0255 struct stm32_dfsdm_filter_osr {
0256     unsigned int iosr;
0257     unsigned int fosr;
0258     unsigned int rshift;
0259     unsigned int lshift;
0260     u64 res;
0261     u32 bits;
0262     s32 max;
0263 };
0264 
0265 /**
0266  * struct stm32_dfsdm_filter - structure relative to stm32 FDSDM filter
0267  * @ford: filter order
0268  * @flo: filter oversampling data table indexed by fast mode flag
0269  * @sync_mode: filter synchronized with filter 0
0270  * @fast: filter fast mode
0271  */
0272 struct stm32_dfsdm_filter {
0273     enum stm32_dfsdm_sinc_order ford;
0274     struct stm32_dfsdm_filter_osr flo[2];
0275     unsigned int sync_mode;
0276     unsigned int fast;
0277 };
0278 
0279 /**
0280  * struct stm32_dfsdm_channel - structure relative to stm32 FDSDM channel
0281  * @id: id of the channel
0282  * @type: interface type linked to stm32_dfsdm_chan_type
0283  * @src: interface type linked to stm32_dfsdm_chan_src
0284  * @alt_si: alternative serial input interface
0285  */
0286 struct stm32_dfsdm_channel {
0287     unsigned int id;
0288     unsigned int type;
0289     unsigned int src;
0290     unsigned int alt_si;
0291 };
0292 
0293 /**
0294  * struct stm32_dfsdm - stm32 FDSDM driver common data (for all instances)
0295  * @base:   control registers base cpu addr
0296  * @phys_base:  DFSDM IP register physical address
0297  * @regmap: regmap for register read/write
0298  * @fl_list:    filter resources list
0299  * @num_fls:    number of filter resources available
0300  * @ch_list:    channel resources list
0301  * @num_chs:    number of channel resources available
0302  * @spi_master_freq: SPI clock out frequency
0303  */
0304 struct stm32_dfsdm {
0305     void __iomem    *base;
0306     phys_addr_t phys_base;
0307     struct regmap *regmap;
0308     struct stm32_dfsdm_filter *fl_list;
0309     unsigned int num_fls;
0310     struct stm32_dfsdm_channel *ch_list;
0311     unsigned int num_chs;
0312     unsigned int spi_master_freq;
0313 };
0314 
0315 /* DFSDM channel serial spi clock source */
0316 enum stm32_dfsdm_spi_clk_src {
0317     DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL,
0318     DFSDM_CHANNEL_SPI_CLOCK_INTERNAL,
0319     DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_FALLING,
0320     DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_RISING
0321 };
0322 
0323 int stm32_dfsdm_start_dfsdm(struct stm32_dfsdm *dfsdm);
0324 int stm32_dfsdm_stop_dfsdm(struct stm32_dfsdm *dfsdm);
0325 
0326 #endif
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