iio/adc/stm32-dfsdm-core.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * This file is part the core part STM32 DFSDM driver
0004  *
0005  * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
0006  * Author(s): Arnaud Pouliquen <arnaud.pouliquen@st.com> for STMicroelectronics.
0007  */
0008
0009 #include <linux/clk.h>
0010 #include <linux/iio/iio.h>
0011 #include <linux/iio/sysfs.h>
0012 #include <linux/interrupt.h>
0013 #include <linux/module.h>
0014 #include <linux/of_device.h>
0015 #include <linux/pinctrl/consumer.h>
0016 #include <linux/pm_runtime.h>
0017 #include <linux/regmap.h>
0018 #include <linux/slab.h>
0019
0020 #include "stm32-dfsdm.h"
0021
0022 struct stm32_dfsdm_dev_data {
0023     unsigned int num_filters;
0024     unsigned int num_channels;
0025     const struct regmap_config *regmap_cfg;
0026 };
0027
0028 #define STM32H7_DFSDM_NUM_FILTERS   4
0029 #define STM32H7_DFSDM_NUM_CHANNELS  8
0030 #define STM32MP1_DFSDM_NUM_FILTERS  6
0031 #define STM32MP1_DFSDM_NUM_CHANNELS 8
0032
0033 static bool stm32_dfsdm_volatile_reg(struct device *dev, unsigned int reg)
0034 {
0035     if (reg < DFSDM_FILTER_BASE_ADR)
0036         return false;
0037
0038     /*
0039      * Mask is done on register to avoid to list registers of all
0040      * filter instances.
0041      */
0042     switch (reg & DFSDM_FILTER_REG_MASK) {
0043     case DFSDM_CR1(0) & DFSDM_FILTER_REG_MASK:
0044     case DFSDM_ISR(0) & DFSDM_FILTER_REG_MASK:
0045     case DFSDM_JDATAR(0) & DFSDM_FILTER_REG_MASK:
0046     case DFSDM_RDATAR(0) & DFSDM_FILTER_REG_MASK:
0047         return true;
0048     }
0049
0050     return false;
0051 }
0052
0053 static const struct regmap_config stm32h7_dfsdm_regmap_cfg = {
0054     .reg_bits = 32,
0055     .val_bits = 32,
0056     .reg_stride = sizeof(u32),
0057     .max_register = 0x2B8,
0058     .volatile_reg = stm32_dfsdm_volatile_reg,
0059     .fast_io = true,
0060 };
0061
0062 static const struct stm32_dfsdm_dev_data stm32h7_dfsdm_data = {
0063     .num_filters = STM32H7_DFSDM_NUM_FILTERS,
0064     .num_channels = STM32H7_DFSDM_NUM_CHANNELS,
0065     .regmap_cfg = &stm32h7_dfsdm_regmap_cfg,
0066 };
0067
0068 static const struct regmap_config stm32mp1_dfsdm_regmap_cfg = {
0069     .reg_bits = 32,
0070     .val_bits = 32,
0071     .reg_stride = sizeof(u32),
0072     .max_register = 0x7fc,
0073     .volatile_reg = stm32_dfsdm_volatile_reg,
0074     .fast_io = true,
0075 };
0076
0077 static const struct stm32_dfsdm_dev_data stm32mp1_dfsdm_data = {
0078     .num_filters = STM32MP1_DFSDM_NUM_FILTERS,
0079     .num_channels = STM32MP1_DFSDM_NUM_CHANNELS,
0080     .regmap_cfg = &stm32mp1_dfsdm_regmap_cfg,
0081 };
0082
0083 struct dfsdm_priv {
0084     struct platform_device *pdev; /* platform device */
0085
0086     struct stm32_dfsdm dfsdm; /* common data exported for all instances */
0087
0088     unsigned int spi_clk_out_div; /* SPI clkout divider value */
0089     atomic_t n_active_ch;   /* number of current active channels */
0090
0091     struct clk *clk; /* DFSDM clock */
0092     struct clk *aclk; /* audio clock */
0093 };
0094
0095 static inline struct dfsdm_priv *to_stm32_dfsdm_priv(struct stm32_dfsdm *dfsdm)
0096 {
0097     return container_of(dfsdm, struct dfsdm_priv, dfsdm);
0098 }
0099
0100 static int stm32_dfsdm_clk_prepare_enable(struct stm32_dfsdm *dfsdm)
0101 {
0102     struct dfsdm_priv *priv = to_stm32_dfsdm_priv(dfsdm);
0103     int ret;
0104
0105     ret = clk_prepare_enable(priv->clk);
0106     if (ret || !priv->aclk)
0107         return ret;
0108
0109     ret = clk_prepare_enable(priv->aclk);
0110     if (ret)
0111         clk_disable_unprepare(priv->clk);
0112
0113     return ret;
0114 }
0115
0116 static void stm32_dfsdm_clk_disable_unprepare(struct stm32_dfsdm *dfsdm)
0117 {
0118     struct dfsdm_priv *priv = to_stm32_dfsdm_priv(dfsdm);
0119
0120     clk_disable_unprepare(priv->aclk);
0121     clk_disable_unprepare(priv->clk);
0122 }
0123
0124 /**
0125  * stm32_dfsdm_start_dfsdm - start global dfsdm interface.
0126  *
0127  * Enable interface if n_active_ch is not null.
0128  * @dfsdm: Handle used to retrieve dfsdm context.
0129  */
0130 int stm32_dfsdm_start_dfsdm(struct stm32_dfsdm *dfsdm)
0131 {
0132     struct dfsdm_priv *priv = to_stm32_dfsdm_priv(dfsdm);
0133     struct device *dev = &priv->pdev->dev;
0134     unsigned int clk_div = priv->spi_clk_out_div, clk_src;
0135     int ret;
0136
0137     if (atomic_inc_return(&priv->n_active_ch) == 1) {
0138         ret = pm_runtime_resume_and_get(dev);
0139         if (ret < 0)
0140             goto error_ret;
0141
0142         /* select clock source, e.g. 0 for "dfsdm" or 1 for "audio" */
0143         clk_src = priv->aclk ? 1 : 0;
0144         ret = regmap_update_bits(dfsdm->regmap, DFSDM_CHCFGR1(0),
0145                      DFSDM_CHCFGR1_CKOUTSRC_MASK,
0146                      DFSDM_CHCFGR1_CKOUTSRC(clk_src));
0147         if (ret < 0)
0148             goto pm_put;
0149
0150         /* Output the SPI CLKOUT (if clk_div == 0 clock if OFF) */
0151         ret = regmap_update_bits(dfsdm->regmap, DFSDM_CHCFGR1(0),
0152                      DFSDM_CHCFGR1_CKOUTDIV_MASK,
0153                      DFSDM_CHCFGR1_CKOUTDIV(clk_div));
0154         if (ret < 0)
0155             goto pm_put;
0156
0157         /* Global enable of DFSDM interface */
0158         ret = regmap_update_bits(dfsdm->regmap, DFSDM_CHCFGR1(0),
0159                      DFSDM_CHCFGR1_DFSDMEN_MASK,
0160                      DFSDM_CHCFGR1_DFSDMEN(1));
0161         if (ret < 0)
0162             goto pm_put;
0163     }
0164
0165     dev_dbg(dev, "%s: n_active_ch %d\n", __func__,
0166         atomic_read(&priv->n_active_ch));
0167
0168     return 0;
0169
0170 pm_put:
0171     pm_runtime_put_sync(dev);
0172 error_ret:
0173     atomic_dec(&priv->n_active_ch);
0174
0175     return ret;
0176 }
0177 EXPORT_SYMBOL_GPL(stm32_dfsdm_start_dfsdm);
0178
0179 /**
0180  * stm32_dfsdm_stop_dfsdm - stop global DFSDM interface.
0181  *
0182  * Disable interface if n_active_ch is null
0183  * @dfsdm: Handle used to retrieve dfsdm context.
0184  */
0185 int stm32_dfsdm_stop_dfsdm(struct stm32_dfsdm *dfsdm)
0186 {
0187     struct dfsdm_priv *priv = to_stm32_dfsdm_priv(dfsdm);
0188     int ret;
0189
0190     if (atomic_dec_and_test(&priv->n_active_ch)) {
0191         /* Global disable of DFSDM interface */
0192         ret = regmap_update_bits(dfsdm->regmap, DFSDM_CHCFGR1(0),
0193                      DFSDM_CHCFGR1_DFSDMEN_MASK,
0194                      DFSDM_CHCFGR1_DFSDMEN(0));
0195         if (ret < 0)
0196             return ret;
0197
0198         /* Stop SPI CLKOUT */
0199         ret = regmap_update_bits(dfsdm->regmap, DFSDM_CHCFGR1(0),
0200                      DFSDM_CHCFGR1_CKOUTDIV_MASK,
0201                      DFSDM_CHCFGR1_CKOUTDIV(0));
0202         if (ret < 0)
0203             return ret;
0204
0205         pm_runtime_put_sync(&priv->pdev->dev);
0206     }
0207     dev_dbg(&priv->pdev->dev, "%s: n_active_ch %d\n", __func__,
0208         atomic_read(&priv->n_active_ch));
0209
0210     return 0;
0211 }
0212 EXPORT_SYMBOL_GPL(stm32_dfsdm_stop_dfsdm);
0213
0214 static int stm32_dfsdm_parse_of(struct platform_device *pdev,
0215                 struct dfsdm_priv *priv)
0216 {
0217     struct device_node *node = pdev->dev.of_node;
0218     struct resource *res;
0219     unsigned long clk_freq, divider;
0220     unsigned int spi_freq, rem;
0221     int ret;
0222
0223     if (!node)
0224         return -EINVAL;
0225
0226     priv->dfsdm.base = devm_platform_get_and_ioremap_resource(pdev, 0,
0227                             &res);
0228     if (IS_ERR(priv->dfsdm.base))
0229         return PTR_ERR(priv->dfsdm.base);
0230
0231     priv->dfsdm.phys_base = res->start;
0232
0233     /*
0234      * "dfsdm" clock is mandatory for DFSDM peripheral clocking.
0235      * "dfsdm" or "audio" clocks can be used as source clock for
0236      * the SPI clock out signal and internal processing, depending
0237      * on use case.
0238      */
0239     priv->clk = devm_clk_get(&pdev->dev, "dfsdm");
0240     if (IS_ERR(priv->clk))
0241         return dev_err_probe(&pdev->dev, PTR_ERR(priv->clk),
0242                      "Failed to get clock\n");
0243
0244     priv->aclk = devm_clk_get(&pdev->dev, "audio");
0245     if (IS_ERR(priv->aclk))
0246         priv->aclk = NULL;
0247
0248     if (priv->aclk)
0249         clk_freq = clk_get_rate(priv->aclk);
0250     else
0251         clk_freq = clk_get_rate(priv->clk);
0252
0253     /* SPI clock out frequency */
0254     ret = of_property_read_u32(pdev->dev.of_node, "spi-max-frequency",
0255                    &spi_freq);
0256     if (ret < 0) {
0257         /* No SPI master mode */
0258         return 0;
0259     }
0260
0261     divider = div_u64_rem(clk_freq, spi_freq, &rem);
0262     /* Round up divider when ckout isn't precise, not to exceed spi_freq */
0263     if (rem)
0264         divider++;
0265
0266     /* programmable divider is in range of [2:256] */
0267     if (divider < 2 || divider > 256) {
0268         dev_err(&pdev->dev, "spi-max-frequency not achievable\n");
0269         return -EINVAL;
0270     }
0271
0272     /* SPI clock output divider is: divider = CKOUTDIV + 1 */
0273     priv->spi_clk_out_div = divider - 1;
0274     priv->dfsdm.spi_master_freq = clk_freq / (priv->spi_clk_out_div + 1);
0275
0276     if (rem) {
0277         dev_warn(&pdev->dev, "SPI clock not accurate\n");
0278         dev_warn(&pdev->dev, "%ld = %d * %d + %d\n",
0279              clk_freq, spi_freq, priv->spi_clk_out_div + 1, rem);
0280     }
0281
0282     return 0;
0283 };
0284
0285 static const struct of_device_id stm32_dfsdm_of_match[] = {
0286     {
0287         .compatible = "st,stm32h7-dfsdm",
0288         .data = &stm32h7_dfsdm_data,
0289     },
0290     {
0291         .compatible = "st,stm32mp1-dfsdm",
0292         .data = &stm32mp1_dfsdm_data,
0293     },
0294     {}
0295 };
0296 MODULE_DEVICE_TABLE(of, stm32_dfsdm_of_match);
0297
0298 static int stm32_dfsdm_probe(struct platform_device *pdev)
0299 {
0300     struct dfsdm_priv *priv;
0301     const struct stm32_dfsdm_dev_data *dev_data;
0302     struct stm32_dfsdm *dfsdm;
0303     int ret;
0304
0305     priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
0306     if (!priv)
0307         return -ENOMEM;
0308
0309     priv->pdev = pdev;
0310
0311     dev_data = of_device_get_match_data(&pdev->dev);
0312
0313     dfsdm = &priv->dfsdm;
0314     dfsdm->fl_list = devm_kcalloc(&pdev->dev, dev_data->num_filters,
0315                       sizeof(*dfsdm->fl_list), GFP_KERNEL);
0316     if (!dfsdm->fl_list)
0317         return -ENOMEM;
0318
0319     dfsdm->num_fls = dev_data->num_filters;
0320     dfsdm->ch_list = devm_kcalloc(&pdev->dev, dev_data->num_channels,
0321                       sizeof(*dfsdm->ch_list),
0322                       GFP_KERNEL);
0323     if (!dfsdm->ch_list)
0324         return -ENOMEM;
0325     dfsdm->num_chs = dev_data->num_channels;
0326
0327     ret = stm32_dfsdm_parse_of(pdev, priv);
0328     if (ret < 0)
0329         return ret;
0330
0331     dfsdm->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "dfsdm",
0332                           dfsdm->base,
0333                           dev_data->regmap_cfg);
0334     if (IS_ERR(dfsdm->regmap)) {
0335         ret = PTR_ERR(dfsdm->regmap);
0336         dev_err(&pdev->dev, "%s: Failed to allocate regmap: %d\n",
0337             __func__, ret);
0338         return ret;
0339     }
0340
0341     platform_set_drvdata(pdev, dfsdm);
0342
0343     ret = stm32_dfsdm_clk_prepare_enable(dfsdm);
0344     if (ret) {
0345         dev_err(&pdev->dev, "Failed to start clock\n");
0346         return ret;
0347     }
0348
0349     pm_runtime_get_noresume(&pdev->dev);
0350     pm_runtime_set_active(&pdev->dev);
0351     pm_runtime_enable(&pdev->dev);
0352
0353     ret = of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev);
0354     if (ret)
0355         goto pm_put;
0356
0357     pm_runtime_put(&pdev->dev);
0358
0359     return 0;
0360
0361 pm_put:
0362     pm_runtime_disable(&pdev->dev);
0363     pm_runtime_set_suspended(&pdev->dev);
0364     pm_runtime_put_noidle(&pdev->dev);
0365     stm32_dfsdm_clk_disable_unprepare(dfsdm);
0366
0367     return ret;
0368 }
0369
0370 static int stm32_dfsdm_core_remove(struct platform_device *pdev)
0371 {
0372     struct stm32_dfsdm *dfsdm = platform_get_drvdata(pdev);
0373
0374     pm_runtime_get_sync(&pdev->dev);
0375     of_platform_depopulate(&pdev->dev);
0376     pm_runtime_disable(&pdev->dev);
0377     pm_runtime_set_suspended(&pdev->dev);
0378     pm_runtime_put_noidle(&pdev->dev);
0379     stm32_dfsdm_clk_disable_unprepare(dfsdm);
0380
0381     return 0;
0382 }
0383
0384 static int stm32_dfsdm_core_suspend(struct device *dev)
0385 {
0386     struct stm32_dfsdm *dfsdm = dev_get_drvdata(dev);
0387     struct dfsdm_priv *priv = to_stm32_dfsdm_priv(dfsdm);
0388     int ret;
0389
0390     ret = pm_runtime_force_suspend(dev);
0391     if (ret)
0392         return ret;
0393
0394     /* Balance devm_regmap_init_mmio_clk() clk_prepare() */
0395     clk_unprepare(priv->clk);
0396
0397     return pinctrl_pm_select_sleep_state(dev);
0398 }
0399
0400 static int stm32_dfsdm_core_resume(struct device *dev)
0401 {
0402     struct stm32_dfsdm *dfsdm = dev_get_drvdata(dev);
0403     struct dfsdm_priv *priv = to_stm32_dfsdm_priv(dfsdm);
0404     int ret;
0405
0406     ret = pinctrl_pm_select_default_state(dev);
0407     if (ret)
0408         return ret;
0409
0410     ret = clk_prepare(priv->clk);
0411     if (ret)
0412         return ret;
0413
0414     return pm_runtime_force_resume(dev);
0415 }
0416
0417 static int stm32_dfsdm_core_runtime_suspend(struct device *dev)
0418 {
0419     struct stm32_dfsdm *dfsdm = dev_get_drvdata(dev);
0420
0421     stm32_dfsdm_clk_disable_unprepare(dfsdm);
0422
0423     return 0;
0424 }
0425
0426 static int stm32_dfsdm_core_runtime_resume(struct device *dev)
0427 {
0428     struct stm32_dfsdm *dfsdm = dev_get_drvdata(dev);
0429
0430     return stm32_dfsdm_clk_prepare_enable(dfsdm);
0431 }
0432
0433 static const struct dev_pm_ops stm32_dfsdm_core_pm_ops = {
0434     SYSTEM_SLEEP_PM_OPS(stm32_dfsdm_core_suspend, stm32_dfsdm_core_resume)
0435     RUNTIME_PM_OPS(stm32_dfsdm_core_runtime_suspend,
0436                stm32_dfsdm_core_runtime_resume,
0437                NULL)
0438 };
0439
0440 static struct platform_driver stm32_dfsdm_driver = {
0441     .probe = stm32_dfsdm_probe,
0442     .remove = stm32_dfsdm_core_remove,
0443     .driver = {
0444         .name = "stm32-dfsdm",
0445         .of_match_table = stm32_dfsdm_of_match,
0446         .pm = pm_ptr(&stm32_dfsdm_core_pm_ops),
0447     },
0448 };
0449
0450 module_platform_driver(stm32_dfsdm_driver);
0451
0452 MODULE_AUTHOR("Arnaud Pouliquen <arnaud.pouliquen@st.com>");
0453 MODULE_DESCRIPTION("STMicroelectronics STM32 dfsdm driver");
0454 MODULE_LICENSE("GPL v2");