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0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * This file is part of STM32 ADC driver
0004  *
0005  * Copyright (C) 2016, STMicroelectronics - All Rights Reserved
0006  * Author: Fabrice Gasnier <fabrice.gasnier@st.com>.
0007  *
0008  * Inspired from: fsl-imx25-tsadc
0009  *
0010  */
0011 
0012 #include <linux/clk.h>
0013 #include <linux/interrupt.h>
0014 #include <linux/irqchip/chained_irq.h>
0015 #include <linux/irqdesc.h>
0016 #include <linux/irqdomain.h>
0017 #include <linux/mfd/syscon.h>
0018 #include <linux/module.h>
0019 #include <linux/of_device.h>
0020 #include <linux/pm_runtime.h>
0021 #include <linux/regmap.h>
0022 #include <linux/regulator/consumer.h>
0023 #include <linux/slab.h>
0024 
0025 #include "stm32-adc-core.h"
0026 
0027 #define STM32_ADC_CORE_SLEEP_DELAY_MS   2000
0028 
0029 /* SYSCFG registers */
0030 #define STM32MP1_SYSCFG_PMCSETR     0x04
0031 #define STM32MP1_SYSCFG_PMCCLRR     0x44
0032 
0033 /* SYSCFG bit fields */
0034 #define STM32MP1_SYSCFG_ANASWVDD_MASK   BIT(9)
0035 
0036 /* SYSCFG capability flags */
0037 #define HAS_VBOOSTER        BIT(0)
0038 #define HAS_ANASWVDD        BIT(1)
0039 
0040 /**
0041  * struct stm32_adc_common_regs - stm32 common registers
0042  * @csr:    common status register offset
0043  * @ccr:    common control register offset
0044  * @eoc_msk:    array of eoc (end of conversion flag) masks in csr for adc1..n
0045  * @ovr_msk:    array of ovr (overrun flag) masks in csr for adc1..n
0046  * @ier:    interrupt enable register offset for each adc
0047  * @eocie_msk:  end of conversion interrupt enable mask in @ier
0048  */
0049 struct stm32_adc_common_regs {
0050     u32 csr;
0051     u32 ccr;
0052     u32 eoc_msk[STM32_ADC_MAX_ADCS];
0053     u32 ovr_msk[STM32_ADC_MAX_ADCS];
0054     u32 ier;
0055     u32 eocie_msk;
0056 };
0057 
0058 struct stm32_adc_priv;
0059 
0060 /**
0061  * struct stm32_adc_priv_cfg - stm32 core compatible configuration data
0062  * @regs:   common registers for all instances
0063  * @clk_sel:    clock selection routine
0064  * @max_clk_rate_hz: maximum analog clock rate (Hz, from datasheet)
0065  * @has_syscfg: SYSCFG capability flags
0066  * @num_irqs:   number of interrupt lines
0067  * @num_adcs:   maximum number of ADC instances in the common registers
0068  */
0069 struct stm32_adc_priv_cfg {
0070     const struct stm32_adc_common_regs *regs;
0071     int (*clk_sel)(struct platform_device *, struct stm32_adc_priv *);
0072     u32 max_clk_rate_hz;
0073     unsigned int has_syscfg;
0074     unsigned int num_irqs;
0075     unsigned int num_adcs;
0076 };
0077 
0078 /**
0079  * struct stm32_adc_priv - stm32 ADC core private data
0080  * @irq:        irq(s) for ADC block
0081  * @domain:     irq domain reference
0082  * @aclk:       clock reference for the analog circuitry
0083  * @bclk:       bus clock common for all ADCs, depends on part used
0084  * @max_clk_rate:   desired maximum clock rate
0085  * @booster:        booster supply reference
0086  * @vdd:        vdd supply reference
0087  * @vdda:       vdda analog supply reference
0088  * @vref:       regulator reference
0089  * @vdd_uv:     vdd supply voltage (microvolts)
0090  * @vdda_uv:        vdda supply voltage (microvolts)
0091  * @cfg:        compatible configuration data
0092  * @common:     common data for all ADC instances
0093  * @ccr_bak:        backup CCR in low power mode
0094  * @syscfg:     reference to syscon, system control registers
0095  */
0096 struct stm32_adc_priv {
0097     int             irq[STM32_ADC_MAX_ADCS];
0098     struct irq_domain       *domain;
0099     struct clk          *aclk;
0100     struct clk          *bclk;
0101     u32             max_clk_rate;
0102     struct regulator        *booster;
0103     struct regulator        *vdd;
0104     struct regulator        *vdda;
0105     struct regulator        *vref;
0106     int             vdd_uv;
0107     int             vdda_uv;
0108     const struct stm32_adc_priv_cfg *cfg;
0109     struct stm32_adc_common     common;
0110     u32             ccr_bak;
0111     struct regmap           *syscfg;
0112 };
0113 
0114 static struct stm32_adc_priv *to_stm32_adc_priv(struct stm32_adc_common *com)
0115 {
0116     return container_of(com, struct stm32_adc_priv, common);
0117 }
0118 
0119 /* STM32F4 ADC internal common clock prescaler division ratios */
0120 static int stm32f4_pclk_div[] = {2, 4, 6, 8};
0121 
0122 /**
0123  * stm32f4_adc_clk_sel() - Select stm32f4 ADC common clock prescaler
0124  * @pdev: platform device
0125  * @priv: stm32 ADC core private data
0126  * Select clock prescaler used for analog conversions, before using ADC.
0127  */
0128 static int stm32f4_adc_clk_sel(struct platform_device *pdev,
0129                    struct stm32_adc_priv *priv)
0130 {
0131     unsigned long rate;
0132     u32 val;
0133     int i;
0134 
0135     /* stm32f4 has one clk input for analog (mandatory), enforce it here */
0136     if (!priv->aclk) {
0137         dev_err(&pdev->dev, "No 'adc' clock found\n");
0138         return -ENOENT;
0139     }
0140 
0141     rate = clk_get_rate(priv->aclk);
0142     if (!rate) {
0143         dev_err(&pdev->dev, "Invalid clock rate: 0\n");
0144         return -EINVAL;
0145     }
0146 
0147     for (i = 0; i < ARRAY_SIZE(stm32f4_pclk_div); i++) {
0148         if ((rate / stm32f4_pclk_div[i]) <= priv->max_clk_rate)
0149             break;
0150     }
0151     if (i >= ARRAY_SIZE(stm32f4_pclk_div)) {
0152         dev_err(&pdev->dev, "adc clk selection failed\n");
0153         return -EINVAL;
0154     }
0155 
0156     priv->common.rate = rate / stm32f4_pclk_div[i];
0157     val = readl_relaxed(priv->common.base + STM32F4_ADC_CCR);
0158     val &= ~STM32F4_ADC_ADCPRE_MASK;
0159     val |= i << STM32F4_ADC_ADCPRE_SHIFT;
0160     writel_relaxed(val, priv->common.base + STM32F4_ADC_CCR);
0161 
0162     dev_dbg(&pdev->dev, "Using analog clock source at %ld kHz\n",
0163         priv->common.rate / 1000);
0164 
0165     return 0;
0166 }
0167 
0168 /**
0169  * struct stm32h7_adc_ck_spec - specification for stm32h7 adc clock
0170  * @ckmode: ADC clock mode, Async or sync with prescaler.
0171  * @presc: prescaler bitfield for async clock mode
0172  * @div: prescaler division ratio
0173  */
0174 struct stm32h7_adc_ck_spec {
0175     u32 ckmode;
0176     u32 presc;
0177     int div;
0178 };
0179 
0180 static const struct stm32h7_adc_ck_spec stm32h7_adc_ckmodes_spec[] = {
0181     /* 00: CK_ADC[1..3]: Asynchronous clock modes */
0182     { 0, 0, 1 },
0183     { 0, 1, 2 },
0184     { 0, 2, 4 },
0185     { 0, 3, 6 },
0186     { 0, 4, 8 },
0187     { 0, 5, 10 },
0188     { 0, 6, 12 },
0189     { 0, 7, 16 },
0190     { 0, 8, 32 },
0191     { 0, 9, 64 },
0192     { 0, 10, 128 },
0193     { 0, 11, 256 },
0194     /* HCLK used: Synchronous clock modes (1, 2 or 4 prescaler) */
0195     { 1, 0, 1 },
0196     { 2, 0, 2 },
0197     { 3, 0, 4 },
0198 };
0199 
0200 static int stm32h7_adc_clk_sel(struct platform_device *pdev,
0201                    struct stm32_adc_priv *priv)
0202 {
0203     u32 ckmode, presc, val;
0204     unsigned long rate;
0205     int i, div, duty;
0206 
0207     /* stm32h7 bus clock is common for all ADC instances (mandatory) */
0208     if (!priv->bclk) {
0209         dev_err(&pdev->dev, "No 'bus' clock found\n");
0210         return -ENOENT;
0211     }
0212 
0213     /*
0214      * stm32h7 can use either 'bus' or 'adc' clock for analog circuitry.
0215      * So, choice is to have bus clock mandatory and adc clock optional.
0216      * If optional 'adc' clock has been found, then try to use it first.
0217      */
0218     if (priv->aclk) {
0219         /*
0220          * Asynchronous clock modes (e.g. ckmode == 0)
0221          * From spec: PLL output musn't exceed max rate
0222          */
0223         rate = clk_get_rate(priv->aclk);
0224         if (!rate) {
0225             dev_err(&pdev->dev, "Invalid adc clock rate: 0\n");
0226             return -EINVAL;
0227         }
0228 
0229         /* If duty is an error, kindly use at least /2 divider */
0230         duty = clk_get_scaled_duty_cycle(priv->aclk, 100);
0231         if (duty < 0)
0232             dev_warn(&pdev->dev, "adc clock duty: %d\n", duty);
0233 
0234         for (i = 0; i < ARRAY_SIZE(stm32h7_adc_ckmodes_spec); i++) {
0235             ckmode = stm32h7_adc_ckmodes_spec[i].ckmode;
0236             presc = stm32h7_adc_ckmodes_spec[i].presc;
0237             div = stm32h7_adc_ckmodes_spec[i].div;
0238 
0239             if (ckmode)
0240                 continue;
0241 
0242             /*
0243              * For proper operation, clock duty cycle range is 49%
0244              * to 51%. Apply at least /2 prescaler otherwise.
0245              */
0246             if (div == 1 && (duty < 49 || duty > 51))
0247                 continue;
0248 
0249             if ((rate / div) <= priv->max_clk_rate)
0250                 goto out;
0251         }
0252     }
0253 
0254     /* Synchronous clock modes (e.g. ckmode is 1, 2 or 3) */
0255     rate = clk_get_rate(priv->bclk);
0256     if (!rate) {
0257         dev_err(&pdev->dev, "Invalid bus clock rate: 0\n");
0258         return -EINVAL;
0259     }
0260 
0261     duty = clk_get_scaled_duty_cycle(priv->bclk, 100);
0262     if (duty < 0)
0263         dev_warn(&pdev->dev, "bus clock duty: %d\n", duty);
0264 
0265     for (i = 0; i < ARRAY_SIZE(stm32h7_adc_ckmodes_spec); i++) {
0266         ckmode = stm32h7_adc_ckmodes_spec[i].ckmode;
0267         presc = stm32h7_adc_ckmodes_spec[i].presc;
0268         div = stm32h7_adc_ckmodes_spec[i].div;
0269 
0270         if (!ckmode)
0271             continue;
0272 
0273         if (div == 1 && (duty < 49 || duty > 51))
0274             continue;
0275 
0276         if ((rate / div) <= priv->max_clk_rate)
0277             goto out;
0278     }
0279 
0280     dev_err(&pdev->dev, "adc clk selection failed\n");
0281     return -EINVAL;
0282 
0283 out:
0284     /* rate used later by each ADC instance to control BOOST mode */
0285     priv->common.rate = rate / div;
0286 
0287     /* Set common clock mode and prescaler */
0288     val = readl_relaxed(priv->common.base + STM32H7_ADC_CCR);
0289     val &= ~(STM32H7_CKMODE_MASK | STM32H7_PRESC_MASK);
0290     val |= ckmode << STM32H7_CKMODE_SHIFT;
0291     val |= presc << STM32H7_PRESC_SHIFT;
0292     writel_relaxed(val, priv->common.base + STM32H7_ADC_CCR);
0293 
0294     dev_dbg(&pdev->dev, "Using %s clock/%d source at %ld kHz\n",
0295         ckmode ? "bus" : "adc", div, priv->common.rate / 1000);
0296 
0297     return 0;
0298 }
0299 
0300 /* STM32F4 common registers definitions */
0301 static const struct stm32_adc_common_regs stm32f4_adc_common_regs = {
0302     .csr = STM32F4_ADC_CSR,
0303     .ccr = STM32F4_ADC_CCR,
0304     .eoc_msk = { STM32F4_EOC1, STM32F4_EOC2, STM32F4_EOC3},
0305     .ovr_msk = { STM32F4_OVR1, STM32F4_OVR2, STM32F4_OVR3},
0306     .ier = STM32F4_ADC_CR1,
0307     .eocie_msk = STM32F4_EOCIE,
0308 };
0309 
0310 /* STM32H7 common registers definitions */
0311 static const struct stm32_adc_common_regs stm32h7_adc_common_regs = {
0312     .csr = STM32H7_ADC_CSR,
0313     .ccr = STM32H7_ADC_CCR,
0314     .eoc_msk = { STM32H7_EOC_MST, STM32H7_EOC_SLV},
0315     .ovr_msk = { STM32H7_OVR_MST, STM32H7_OVR_SLV},
0316     .ier = STM32H7_ADC_IER,
0317     .eocie_msk = STM32H7_EOCIE,
0318 };
0319 
0320 static const unsigned int stm32_adc_offset[STM32_ADC_MAX_ADCS] = {
0321     0, STM32_ADC_OFFSET, STM32_ADC_OFFSET * 2,
0322 };
0323 
0324 static unsigned int stm32_adc_eoc_enabled(struct stm32_adc_priv *priv,
0325                       unsigned int adc)
0326 {
0327     u32 ier, offset = stm32_adc_offset[adc];
0328 
0329     ier = readl_relaxed(priv->common.base + offset + priv->cfg->regs->ier);
0330 
0331     return ier & priv->cfg->regs->eocie_msk;
0332 }
0333 
0334 /* ADC common interrupt for all instances */
0335 static void stm32_adc_irq_handler(struct irq_desc *desc)
0336 {
0337     struct stm32_adc_priv *priv = irq_desc_get_handler_data(desc);
0338     struct irq_chip *chip = irq_desc_get_chip(desc);
0339     int i;
0340     u32 status;
0341 
0342     chained_irq_enter(chip, desc);
0343     status = readl_relaxed(priv->common.base + priv->cfg->regs->csr);
0344 
0345     /*
0346      * End of conversion may be handled by using IRQ or DMA. There may be a
0347      * race here when two conversions complete at the same time on several
0348      * ADCs. EOC may be read 'set' for several ADCs, with:
0349      * - an ADC configured to use DMA (EOC triggers the DMA request, and
0350      *   is then automatically cleared by DR read in hardware)
0351      * - an ADC configured to use IRQs (EOCIE bit is set. The handler must
0352      *   be called in this case)
0353      * So both EOC status bit in CSR and EOCIE control bit must be checked
0354      * before invoking the interrupt handler (e.g. call ISR only for
0355      * IRQ-enabled ADCs).
0356      */
0357     for (i = 0; i < priv->cfg->num_adcs; i++) {
0358         if ((status & priv->cfg->regs->eoc_msk[i] &&
0359              stm32_adc_eoc_enabled(priv, i)) ||
0360              (status & priv->cfg->regs->ovr_msk[i]))
0361             generic_handle_domain_irq(priv->domain, i);
0362     }
0363 
0364     chained_irq_exit(chip, desc);
0365 };
0366 
0367 static int stm32_adc_domain_map(struct irq_domain *d, unsigned int irq,
0368                 irq_hw_number_t hwirq)
0369 {
0370     irq_set_chip_data(irq, d->host_data);
0371     irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_level_irq);
0372 
0373     return 0;
0374 }
0375 
0376 static void stm32_adc_domain_unmap(struct irq_domain *d, unsigned int irq)
0377 {
0378     irq_set_chip_and_handler(irq, NULL, NULL);
0379     irq_set_chip_data(irq, NULL);
0380 }
0381 
0382 static const struct irq_domain_ops stm32_adc_domain_ops = {
0383     .map = stm32_adc_domain_map,
0384     .unmap  = stm32_adc_domain_unmap,
0385     .xlate = irq_domain_xlate_onecell,
0386 };
0387 
0388 static int stm32_adc_irq_probe(struct platform_device *pdev,
0389                    struct stm32_adc_priv *priv)
0390 {
0391     struct device_node *np = pdev->dev.of_node;
0392     unsigned int i;
0393 
0394     /*
0395      * Interrupt(s) must be provided, depending on the compatible:
0396      * - stm32f4/h7 shares a common interrupt line.
0397      * - stm32mp1, has one line per ADC
0398      */
0399     for (i = 0; i < priv->cfg->num_irqs; i++) {
0400         priv->irq[i] = platform_get_irq(pdev, i);
0401         if (priv->irq[i] < 0)
0402             return priv->irq[i];
0403     }
0404 
0405     priv->domain = irq_domain_add_simple(np, STM32_ADC_MAX_ADCS, 0,
0406                          &stm32_adc_domain_ops,
0407                          priv);
0408     if (!priv->domain) {
0409         dev_err(&pdev->dev, "Failed to add irq domain\n");
0410         return -ENOMEM;
0411     }
0412 
0413     for (i = 0; i < priv->cfg->num_irqs; i++) {
0414         irq_set_chained_handler(priv->irq[i], stm32_adc_irq_handler);
0415         irq_set_handler_data(priv->irq[i], priv);
0416     }
0417 
0418     return 0;
0419 }
0420 
0421 static void stm32_adc_irq_remove(struct platform_device *pdev,
0422                  struct stm32_adc_priv *priv)
0423 {
0424     int hwirq;
0425     unsigned int i;
0426 
0427     for (hwirq = 0; hwirq < STM32_ADC_MAX_ADCS; hwirq++)
0428         irq_dispose_mapping(irq_find_mapping(priv->domain, hwirq));
0429     irq_domain_remove(priv->domain);
0430 
0431     for (i = 0; i < priv->cfg->num_irqs; i++)
0432         irq_set_chained_handler(priv->irq[i], NULL);
0433 }
0434 
0435 static int stm32_adc_core_switches_supply_en(struct stm32_adc_priv *priv,
0436                          struct device *dev)
0437 {
0438     int ret;
0439 
0440     /*
0441      * On STM32H7 and STM32MP1, the ADC inputs are multiplexed with analog
0442      * switches (via PCSEL) which have reduced performances when their
0443      * supply is below 2.7V (vdda by default):
0444      * - Voltage booster can be used, to get full ADC performances
0445      *   (increases power consumption).
0446      * - Vdd can be used to supply them, if above 2.7V (STM32MP1 only).
0447      *
0448      * Recommended settings for ANASWVDD and EN_BOOSTER:
0449      * - vdda < 2.7V but vdd > 2.7V: ANASWVDD = 1, EN_BOOSTER = 0 (stm32mp1)
0450      * - vdda < 2.7V and vdd < 2.7V: ANASWVDD = 0, EN_BOOSTER = 1
0451      * - vdda >= 2.7V:               ANASWVDD = 0, EN_BOOSTER = 0 (default)
0452      */
0453     if (priv->vdda_uv < 2700000) {
0454         if (priv->syscfg && priv->vdd_uv > 2700000) {
0455             ret = regulator_enable(priv->vdd);
0456             if (ret < 0) {
0457                 dev_err(dev, "vdd enable failed %d\n", ret);
0458                 return ret;
0459             }
0460 
0461             ret = regmap_write(priv->syscfg,
0462                        STM32MP1_SYSCFG_PMCSETR,
0463                        STM32MP1_SYSCFG_ANASWVDD_MASK);
0464             if (ret < 0) {
0465                 regulator_disable(priv->vdd);
0466                 dev_err(dev, "vdd select failed, %d\n", ret);
0467                 return ret;
0468             }
0469             dev_dbg(dev, "analog switches supplied by vdd\n");
0470 
0471             return 0;
0472         }
0473 
0474         if (priv->booster) {
0475             /*
0476              * This is optional, as this is a trade-off between
0477              * analog performance and power consumption.
0478              */
0479             ret = regulator_enable(priv->booster);
0480             if (ret < 0) {
0481                 dev_err(dev, "booster enable failed %d\n", ret);
0482                 return ret;
0483             }
0484             dev_dbg(dev, "analog switches supplied by booster\n");
0485 
0486             return 0;
0487         }
0488     }
0489 
0490     /* Fallback using vdda (default), nothing to do */
0491     dev_dbg(dev, "analog switches supplied by vdda (%d uV)\n",
0492         priv->vdda_uv);
0493 
0494     return 0;
0495 }
0496 
0497 static void stm32_adc_core_switches_supply_dis(struct stm32_adc_priv *priv)
0498 {
0499     if (priv->vdda_uv < 2700000) {
0500         if (priv->syscfg && priv->vdd_uv > 2700000) {
0501             regmap_write(priv->syscfg, STM32MP1_SYSCFG_PMCCLRR,
0502                      STM32MP1_SYSCFG_ANASWVDD_MASK);
0503             regulator_disable(priv->vdd);
0504             return;
0505         }
0506         if (priv->booster)
0507             regulator_disable(priv->booster);
0508     }
0509 }
0510 
0511 static int stm32_adc_core_hw_start(struct device *dev)
0512 {
0513     struct stm32_adc_common *common = dev_get_drvdata(dev);
0514     struct stm32_adc_priv *priv = to_stm32_adc_priv(common);
0515     int ret;
0516 
0517     ret = regulator_enable(priv->vdda);
0518     if (ret < 0) {
0519         dev_err(dev, "vdda enable failed %d\n", ret);
0520         return ret;
0521     }
0522 
0523     ret = regulator_get_voltage(priv->vdda);
0524     if (ret < 0) {
0525         dev_err(dev, "vdda get voltage failed, %d\n", ret);
0526         goto err_vdda_disable;
0527     }
0528     priv->vdda_uv = ret;
0529 
0530     ret = stm32_adc_core_switches_supply_en(priv, dev);
0531     if (ret < 0)
0532         goto err_vdda_disable;
0533 
0534     ret = regulator_enable(priv->vref);
0535     if (ret < 0) {
0536         dev_err(dev, "vref enable failed\n");
0537         goto err_switches_dis;
0538     }
0539 
0540     ret = clk_prepare_enable(priv->bclk);
0541     if (ret < 0) {
0542         dev_err(dev, "bus clk enable failed\n");
0543         goto err_regulator_disable;
0544     }
0545 
0546     ret = clk_prepare_enable(priv->aclk);
0547     if (ret < 0) {
0548         dev_err(dev, "adc clk enable failed\n");
0549         goto err_bclk_disable;
0550     }
0551 
0552     writel_relaxed(priv->ccr_bak, priv->common.base + priv->cfg->regs->ccr);
0553 
0554     return 0;
0555 
0556 err_bclk_disable:
0557     clk_disable_unprepare(priv->bclk);
0558 err_regulator_disable:
0559     regulator_disable(priv->vref);
0560 err_switches_dis:
0561     stm32_adc_core_switches_supply_dis(priv);
0562 err_vdda_disable:
0563     regulator_disable(priv->vdda);
0564 
0565     return ret;
0566 }
0567 
0568 static void stm32_adc_core_hw_stop(struct device *dev)
0569 {
0570     struct stm32_adc_common *common = dev_get_drvdata(dev);
0571     struct stm32_adc_priv *priv = to_stm32_adc_priv(common);
0572 
0573     /* Backup CCR that may be lost (depends on power state to achieve) */
0574     priv->ccr_bak = readl_relaxed(priv->common.base + priv->cfg->regs->ccr);
0575     clk_disable_unprepare(priv->aclk);
0576     clk_disable_unprepare(priv->bclk);
0577     regulator_disable(priv->vref);
0578     stm32_adc_core_switches_supply_dis(priv);
0579     regulator_disable(priv->vdda);
0580 }
0581 
0582 static int stm32_adc_core_switches_probe(struct device *dev,
0583                      struct stm32_adc_priv *priv)
0584 {
0585     struct device_node *np = dev->of_node;
0586     int ret;
0587 
0588     /* Analog switches supply can be controlled by syscfg (optional) */
0589     priv->syscfg = syscon_regmap_lookup_by_phandle(np, "st,syscfg");
0590     if (IS_ERR(priv->syscfg)) {
0591         ret = PTR_ERR(priv->syscfg);
0592         if (ret != -ENODEV)
0593             return dev_err_probe(dev, ret, "Can't probe syscfg\n");
0594 
0595         priv->syscfg = NULL;
0596     }
0597 
0598     /* Booster can be used to supply analog switches (optional) */
0599     if (priv->cfg->has_syscfg & HAS_VBOOSTER &&
0600         of_property_read_bool(np, "booster-supply")) {
0601         priv->booster = devm_regulator_get_optional(dev, "booster");
0602         if (IS_ERR(priv->booster)) {
0603             ret = PTR_ERR(priv->booster);
0604             if (ret != -ENODEV)
0605                 return dev_err_probe(dev, ret, "can't get booster\n");
0606 
0607             priv->booster = NULL;
0608         }
0609     }
0610 
0611     /* Vdd can be used to supply analog switches (optional) */
0612     if (priv->cfg->has_syscfg & HAS_ANASWVDD &&
0613         of_property_read_bool(np, "vdd-supply")) {
0614         priv->vdd = devm_regulator_get_optional(dev, "vdd");
0615         if (IS_ERR(priv->vdd)) {
0616             ret = PTR_ERR(priv->vdd);
0617             if (ret != -ENODEV)
0618                 return dev_err_probe(dev, ret, "can't get vdd\n");
0619 
0620             priv->vdd = NULL;
0621         }
0622     }
0623 
0624     if (priv->vdd) {
0625         ret = regulator_enable(priv->vdd);
0626         if (ret < 0) {
0627             dev_err(dev, "vdd enable failed %d\n", ret);
0628             return ret;
0629         }
0630 
0631         ret = regulator_get_voltage(priv->vdd);
0632         if (ret < 0) {
0633             dev_err(dev, "vdd get voltage failed %d\n", ret);
0634             regulator_disable(priv->vdd);
0635             return ret;
0636         }
0637         priv->vdd_uv = ret;
0638 
0639         regulator_disable(priv->vdd);
0640     }
0641 
0642     return 0;
0643 }
0644 
0645 static int stm32_adc_probe(struct platform_device *pdev)
0646 {
0647     struct stm32_adc_priv *priv;
0648     struct device *dev = &pdev->dev;
0649     struct device_node *np = pdev->dev.of_node;
0650     struct resource *res;
0651     u32 max_rate;
0652     int ret;
0653 
0654     if (!pdev->dev.of_node)
0655         return -ENODEV;
0656 
0657     priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
0658     if (!priv)
0659         return -ENOMEM;
0660     platform_set_drvdata(pdev, &priv->common);
0661 
0662     priv->cfg = (const struct stm32_adc_priv_cfg *)
0663         of_match_device(dev->driver->of_match_table, dev)->data;
0664     spin_lock_init(&priv->common.lock);
0665 
0666     res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
0667     priv->common.base = devm_ioremap_resource(&pdev->dev, res);
0668     if (IS_ERR(priv->common.base))
0669         return PTR_ERR(priv->common.base);
0670     priv->common.phys_base = res->start;
0671 
0672     priv->vdda = devm_regulator_get(&pdev->dev, "vdda");
0673     if (IS_ERR(priv->vdda))
0674         return dev_err_probe(&pdev->dev, PTR_ERR(priv->vdda),
0675                      "vdda get failed\n");
0676 
0677     priv->vref = devm_regulator_get(&pdev->dev, "vref");
0678     if (IS_ERR(priv->vref))
0679         return dev_err_probe(&pdev->dev, PTR_ERR(priv->vref),
0680                      "vref get failed\n");
0681 
0682     priv->aclk = devm_clk_get_optional(&pdev->dev, "adc");
0683     if (IS_ERR(priv->aclk))
0684         return dev_err_probe(&pdev->dev, PTR_ERR(priv->aclk),
0685                      "Can't get 'adc' clock\n");
0686 
0687     priv->bclk = devm_clk_get_optional(&pdev->dev, "bus");
0688     if (IS_ERR(priv->bclk))
0689         return dev_err_probe(&pdev->dev, PTR_ERR(priv->bclk),
0690                      "Can't get 'bus' clock\n");
0691 
0692     ret = stm32_adc_core_switches_probe(dev, priv);
0693     if (ret)
0694         return ret;
0695 
0696     pm_runtime_get_noresume(dev);
0697     pm_runtime_set_active(dev);
0698     pm_runtime_set_autosuspend_delay(dev, STM32_ADC_CORE_SLEEP_DELAY_MS);
0699     pm_runtime_use_autosuspend(dev);
0700     pm_runtime_enable(dev);
0701 
0702     ret = stm32_adc_core_hw_start(dev);
0703     if (ret)
0704         goto err_pm_stop;
0705 
0706     ret = regulator_get_voltage(priv->vref);
0707     if (ret < 0) {
0708         dev_err(&pdev->dev, "vref get voltage failed, %d\n", ret);
0709         goto err_hw_stop;
0710     }
0711     priv->common.vref_mv = ret / 1000;
0712     dev_dbg(&pdev->dev, "vref+=%dmV\n", priv->common.vref_mv);
0713 
0714     ret = of_property_read_u32(pdev->dev.of_node, "st,max-clk-rate-hz",
0715                    &max_rate);
0716     if (!ret)
0717         priv->max_clk_rate = min(max_rate, priv->cfg->max_clk_rate_hz);
0718     else
0719         priv->max_clk_rate = priv->cfg->max_clk_rate_hz;
0720 
0721     ret = priv->cfg->clk_sel(pdev, priv);
0722     if (ret < 0)
0723         goto err_hw_stop;
0724 
0725     ret = stm32_adc_irq_probe(pdev, priv);
0726     if (ret < 0)
0727         goto err_hw_stop;
0728 
0729     ret = of_platform_populate(np, NULL, NULL, &pdev->dev);
0730     if (ret < 0) {
0731         dev_err(&pdev->dev, "failed to populate DT children\n");
0732         goto err_irq_remove;
0733     }
0734 
0735     pm_runtime_mark_last_busy(dev);
0736     pm_runtime_put_autosuspend(dev);
0737 
0738     return 0;
0739 
0740 err_irq_remove:
0741     stm32_adc_irq_remove(pdev, priv);
0742 err_hw_stop:
0743     stm32_adc_core_hw_stop(dev);
0744 err_pm_stop:
0745     pm_runtime_disable(dev);
0746     pm_runtime_set_suspended(dev);
0747     pm_runtime_put_noidle(dev);
0748 
0749     return ret;
0750 }
0751 
0752 static int stm32_adc_remove(struct platform_device *pdev)
0753 {
0754     struct stm32_adc_common *common = platform_get_drvdata(pdev);
0755     struct stm32_adc_priv *priv = to_stm32_adc_priv(common);
0756 
0757     pm_runtime_get_sync(&pdev->dev);
0758     of_platform_depopulate(&pdev->dev);
0759     stm32_adc_irq_remove(pdev, priv);
0760     stm32_adc_core_hw_stop(&pdev->dev);
0761     pm_runtime_disable(&pdev->dev);
0762     pm_runtime_set_suspended(&pdev->dev);
0763     pm_runtime_put_noidle(&pdev->dev);
0764 
0765     return 0;
0766 }
0767 
0768 static int stm32_adc_core_runtime_suspend(struct device *dev)
0769 {
0770     stm32_adc_core_hw_stop(dev);
0771 
0772     return 0;
0773 }
0774 
0775 static int stm32_adc_core_runtime_resume(struct device *dev)
0776 {
0777     return stm32_adc_core_hw_start(dev);
0778 }
0779 
0780 static int stm32_adc_core_runtime_idle(struct device *dev)
0781 {
0782     pm_runtime_mark_last_busy(dev);
0783 
0784     return 0;
0785 }
0786 
0787 static DEFINE_RUNTIME_DEV_PM_OPS(stm32_adc_core_pm_ops,
0788                 stm32_adc_core_runtime_suspend,
0789                 stm32_adc_core_runtime_resume,
0790                 stm32_adc_core_runtime_idle);
0791 
0792 static const struct stm32_adc_priv_cfg stm32f4_adc_priv_cfg = {
0793     .regs = &stm32f4_adc_common_regs,
0794     .clk_sel = stm32f4_adc_clk_sel,
0795     .max_clk_rate_hz = 36000000,
0796     .num_irqs = 1,
0797     .num_adcs = 3,
0798 };
0799 
0800 static const struct stm32_adc_priv_cfg stm32h7_adc_priv_cfg = {
0801     .regs = &stm32h7_adc_common_regs,
0802     .clk_sel = stm32h7_adc_clk_sel,
0803     .max_clk_rate_hz = 36000000,
0804     .has_syscfg = HAS_VBOOSTER,
0805     .num_irqs = 1,
0806     .num_adcs = 2,
0807 };
0808 
0809 static const struct stm32_adc_priv_cfg stm32mp1_adc_priv_cfg = {
0810     .regs = &stm32h7_adc_common_regs,
0811     .clk_sel = stm32h7_adc_clk_sel,
0812     .max_clk_rate_hz = 36000000,
0813     .has_syscfg = HAS_VBOOSTER | HAS_ANASWVDD,
0814     .num_irqs = 2,
0815     .num_adcs = 2,
0816 };
0817 
0818 static const struct of_device_id stm32_adc_of_match[] = {
0819     {
0820         .compatible = "st,stm32f4-adc-core",
0821         .data = (void *)&stm32f4_adc_priv_cfg
0822     }, {
0823         .compatible = "st,stm32h7-adc-core",
0824         .data = (void *)&stm32h7_adc_priv_cfg
0825     }, {
0826         .compatible = "st,stm32mp1-adc-core",
0827         .data = (void *)&stm32mp1_adc_priv_cfg
0828     }, {
0829     },
0830 };
0831 MODULE_DEVICE_TABLE(of, stm32_adc_of_match);
0832 
0833 static struct platform_driver stm32_adc_driver = {
0834     .probe = stm32_adc_probe,
0835     .remove = stm32_adc_remove,
0836     .driver = {
0837         .name = "stm32-adc-core",
0838         .of_match_table = stm32_adc_of_match,
0839         .pm = pm_ptr(&stm32_adc_core_pm_ops),
0840     },
0841 };
0842 module_platform_driver(stm32_adc_driver);
0843 
0844 MODULE_AUTHOR("Fabrice Gasnier <fabrice.gasnier@st.com>");
0845 MODULE_DESCRIPTION("STMicroelectronics STM32 ADC core driver");
0846 MODULE_LICENSE("GPL v2");
0847 MODULE_ALIAS("platform:stm32-adc-core");
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