iio/adc/sc27xx_adc.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 // Copyright (C) 2018 Spreadtrum Communications Inc.
0003
0004 #include <linux/hwspinlock.h>
0005 #include <linux/iio/iio.h>
0006 #include <linux/module.h>
0007 #include <linux/nvmem-consumer.h>
0008 #include <linux/of.h>
0009 #include <linux/of_device.h>
0010 #include <linux/platform_device.h>
0011 #include <linux/regmap.h>
0012 #include <linux/regulator/consumer.h>
0013 #include <linux/slab.h>
0014
0015 /* PMIC global registers definition */
0016 #define SC2730_MODULE_EN        0x1808
0017 #define SC2731_MODULE_EN        0xc08
0018 #define SC27XX_MODULE_ADC_EN        BIT(5)
0019 #define SC2721_ARM_CLK_EN       0xc0c
0020 #define SC2730_ARM_CLK_EN       0x180c
0021 #define SC2731_ARM_CLK_EN       0xc10
0022 #define SC27XX_CLK_ADC_EN       BIT(5)
0023 #define SC27XX_CLK_ADC_CLK_EN       BIT(6)
0024
0025 /* ADC controller registers definition */
0026 #define SC27XX_ADC_CTL          0x0
0027 #define SC27XX_ADC_CH_CFG       0x4
0028 #define SC27XX_ADC_DATA         0x4c
0029 #define SC27XX_ADC_INT_EN       0x50
0030 #define SC27XX_ADC_INT_CLR      0x54
0031 #define SC27XX_ADC_INT_STS      0x58
0032 #define SC27XX_ADC_INT_RAW      0x5c
0033
0034 /* Bits and mask definition for SC27XX_ADC_CTL register */
0035 #define SC27XX_ADC_EN           BIT(0)
0036 #define SC27XX_ADC_CHN_RUN      BIT(1)
0037 #define SC27XX_ADC_12BIT_MODE       BIT(2)
0038 #define SC27XX_ADC_RUN_NUM_MASK     GENMASK(7, 4)
0039 #define SC27XX_ADC_RUN_NUM_SHIFT    4
0040
0041 /* Bits and mask definition for SC27XX_ADC_CH_CFG register */
0042 #define SC27XX_ADC_CHN_ID_MASK      GENMASK(4, 0)
0043 #define SC27XX_ADC_SCALE_MASK       GENMASK(10, 9)
0044 #define SC2721_ADC_SCALE_MASK       BIT(5)
0045 #define SC27XX_ADC_SCALE_SHIFT      9
0046 #define SC2721_ADC_SCALE_SHIFT      5
0047
0048 /* Bits definitions for SC27XX_ADC_INT_EN registers */
0049 #define SC27XX_ADC_IRQ_EN       BIT(0)
0050
0051 /* Bits definitions for SC27XX_ADC_INT_CLR registers */
0052 #define SC27XX_ADC_IRQ_CLR      BIT(0)
0053
0054 /* Bits definitions for SC27XX_ADC_INT_RAW registers */
0055 #define SC27XX_ADC_IRQ_RAW      BIT(0)
0056
0057 /* Mask definition for SC27XX_ADC_DATA register */
0058 #define SC27XX_ADC_DATA_MASK        GENMASK(11, 0)
0059
0060 /* Timeout (ms) for the trylock of hardware spinlocks */
0061 #define SC27XX_ADC_HWLOCK_TIMEOUT   5000
0062
0063 /* Timeout (us) for ADC data conversion according to ADC datasheet */
0064 #define SC27XX_ADC_RDY_TIMEOUT      1000000
0065 #define SC27XX_ADC_POLL_RAW_STATUS  500
0066
0067 /* Maximum ADC channel number */
0068 #define SC27XX_ADC_CHANNEL_MAX      32
0069
0070 /* ADC voltage ratio definition */
0071 #define SC27XX_VOLT_RATIO(n, d)     \
0072     (((n) << SC27XX_RATIO_NUMERATOR_OFFSET) | (d))
0073 #define SC27XX_RATIO_NUMERATOR_OFFSET   16
0074 #define SC27XX_RATIO_DENOMINATOR_MASK   GENMASK(15, 0)
0075
0076 /* ADC specific channel reference voltage 3.5V */
0077 #define SC27XX_ADC_REFVOL_VDD35     3500000
0078
0079 /* ADC default channel reference voltage is 2.8V */
0080 #define SC27XX_ADC_REFVOL_VDD28     2800000
0081
0082 struct sc27xx_adc_data {
0083     struct device *dev;
0084     struct regulator *volref;
0085     struct regmap *regmap;
0086     /*
0087      * One hardware spinlock to synchronize between the multiple
0088      * subsystems which will access the unique ADC controller.
0089      */
0090     struct hwspinlock *hwlock;
0091     int channel_scale[SC27XX_ADC_CHANNEL_MAX];
0092     u32 base;
0093     int irq;
0094     const struct sc27xx_adc_variant_data *var_data;
0095 };
0096
0097 /*
0098  * Since different PMICs of SC27xx series can have different
0099  * address and ratio, we should save ratio config and base
0100  * in the device data structure.
0101  */
0102 struct sc27xx_adc_variant_data {
0103     u32 module_en;
0104     u32 clk_en;
0105     u32 scale_shift;
0106     u32 scale_mask;
0107     const struct sc27xx_adc_linear_graph *bscale_cal;
0108     const struct sc27xx_adc_linear_graph *sscale_cal;
0109     void (*init_scale)(struct sc27xx_adc_data *data);
0110     int (*get_ratio)(int channel, int scale);
0111     bool set_volref;
0112 };
0113
0114 struct sc27xx_adc_linear_graph {
0115     int volt0;
0116     int adc0;
0117     int volt1;
0118     int adc1;
0119 };
0120
0121 /*
0122  * According to the datasheet, we can convert one ADC value to one voltage value
0123  * through 2 points in the linear graph. If the voltage is less than 1.2v, we
0124  * should use the small-scale graph, and if more than 1.2v, we should use the
0125  * big-scale graph.
0126  */
0127 static struct sc27xx_adc_linear_graph big_scale_graph = {
0128     4200, 3310,
0129     3600, 2832,
0130 };
0131
0132 static struct sc27xx_adc_linear_graph small_scale_graph = {
0133     1000, 3413,
0134     100, 341,
0135 };
0136
0137 static const struct sc27xx_adc_linear_graph sc2731_big_scale_graph_calib = {
0138     4200, 850,
0139     3600, 728,
0140 };
0141
0142 static const struct sc27xx_adc_linear_graph sc2731_small_scale_graph_calib = {
0143     1000, 838,
0144     100, 84,
0145 };
0146
0147 static const struct sc27xx_adc_linear_graph big_scale_graph_calib = {
0148     4200, 856,
0149     3600, 733,
0150 };
0151
0152 static const struct sc27xx_adc_linear_graph small_scale_graph_calib = {
0153     1000, 833,
0154     100, 80,
0155 };
0156
0157 static int sc27xx_adc_get_calib_data(u32 calib_data, int calib_adc)
0158 {
0159     return ((calib_data & 0xff) + calib_adc - 128) * 4;
0160 }
0161
0162 /* get the adc nvmem cell calibration data */
0163 static int adc_nvmem_cell_calib_data(struct sc27xx_adc_data *data, const char *cell_name)
0164 {
0165     struct nvmem_cell *cell;
0166     void *buf;
0167     u32 origin_calib_data = 0;
0168     size_t len;
0169
0170     if (!data)
0171         return -EINVAL;
0172
0173     cell = nvmem_cell_get(data->dev, cell_name);
0174     if (IS_ERR(cell))
0175         return PTR_ERR(cell);
0176
0177     buf = nvmem_cell_read(cell, &len);
0178     if (IS_ERR(buf)) {
0179         nvmem_cell_put(cell);
0180         return PTR_ERR(buf);
0181     }
0182
0183     memcpy(&origin_calib_data, buf, min(len, sizeof(u32)));
0184
0185     kfree(buf);
0186     nvmem_cell_put(cell);
0187     return origin_calib_data;
0188 }
0189
0190 static int sc27xx_adc_scale_calibration(struct sc27xx_adc_data *data,
0191                     bool big_scale)
0192 {
0193     const struct sc27xx_adc_linear_graph *calib_graph;
0194     struct sc27xx_adc_linear_graph *graph;
0195     const char *cell_name;
0196     u32 calib_data = 0;
0197
0198     if (big_scale) {
0199         calib_graph = data->var_data->bscale_cal;
0200         graph = &big_scale_graph;
0201         cell_name = "big_scale_calib";
0202     } else {
0203         calib_graph = data->var_data->sscale_cal;
0204         graph = &small_scale_graph;
0205         cell_name = "small_scale_calib";
0206     }
0207
0208     calib_data = adc_nvmem_cell_calib_data(data, cell_name);
0209
0210     /* Only need to calibrate the adc values in the linear graph. */
0211     graph->adc0 = sc27xx_adc_get_calib_data(calib_data, calib_graph->adc0);
0212     graph->adc1 = sc27xx_adc_get_calib_data(calib_data >> 8,
0213                         calib_graph->adc1);
0214
0215     return 0;
0216 }
0217
0218 static int sc2720_adc_get_ratio(int channel, int scale)
0219 {
0220     switch (channel) {
0221     case 14:
0222         switch (scale) {
0223         case 0:
0224             return SC27XX_VOLT_RATIO(68, 900);
0225         case 1:
0226             return SC27XX_VOLT_RATIO(68, 1760);
0227         case 2:
0228             return SC27XX_VOLT_RATIO(68, 2327);
0229         case 3:
0230             return SC27XX_VOLT_RATIO(68, 3654);
0231         default:
0232             return SC27XX_VOLT_RATIO(1, 1);
0233         }
0234     case 16:
0235         switch (scale) {
0236         case 0:
0237             return SC27XX_VOLT_RATIO(48, 100);
0238         case 1:
0239             return SC27XX_VOLT_RATIO(480, 1955);
0240         case 2:
0241             return SC27XX_VOLT_RATIO(480, 2586);
0242         case 3:
0243             return SC27XX_VOLT_RATIO(48, 406);
0244         default:
0245             return SC27XX_VOLT_RATIO(1, 1);
0246         }
0247     case 21:
0248     case 22:
0249     case 23:
0250         switch (scale) {
0251         case 0:
0252             return SC27XX_VOLT_RATIO(3, 8);
0253         case 1:
0254             return SC27XX_VOLT_RATIO(375, 1955);
0255         case 2:
0256             return SC27XX_VOLT_RATIO(375, 2586);
0257         case 3:
0258             return SC27XX_VOLT_RATIO(300, 3248);
0259         default:
0260             return SC27XX_VOLT_RATIO(1, 1);
0261         }
0262     default:
0263         switch (scale) {
0264         case 0:
0265             return SC27XX_VOLT_RATIO(1, 1);
0266         case 1:
0267             return SC27XX_VOLT_RATIO(1000, 1955);
0268         case 2:
0269             return SC27XX_VOLT_RATIO(1000, 2586);
0270         case 3:
0271             return SC27XX_VOLT_RATIO(100, 406);
0272         default:
0273             return SC27XX_VOLT_RATIO(1, 1);
0274         }
0275     }
0276     return SC27XX_VOLT_RATIO(1, 1);
0277 }
0278
0279 static int sc2721_adc_get_ratio(int channel, int scale)
0280 {
0281     switch (channel) {
0282     case 1:
0283     case 2:
0284     case 3:
0285     case 4:
0286         return scale ? SC27XX_VOLT_RATIO(400, 1025) :
0287             SC27XX_VOLT_RATIO(1, 1);
0288     case 5:
0289         return SC27XX_VOLT_RATIO(7, 29);
0290     case 7:
0291     case 9:
0292         return scale ? SC27XX_VOLT_RATIO(100, 125) :
0293             SC27XX_VOLT_RATIO(1, 1);
0294     case 14:
0295         return SC27XX_VOLT_RATIO(68, 900);
0296     case 16:
0297         return SC27XX_VOLT_RATIO(48, 100);
0298     case 19:
0299         return SC27XX_VOLT_RATIO(1, 3);
0300     default:
0301         return SC27XX_VOLT_RATIO(1, 1);
0302     }
0303     return SC27XX_VOLT_RATIO(1, 1);
0304 }
0305
0306 static int sc2730_adc_get_ratio(int channel, int scale)
0307 {
0308     switch (channel) {
0309     case 14:
0310         switch (scale) {
0311         case 0:
0312             return SC27XX_VOLT_RATIO(68, 900);
0313         case 1:
0314             return SC27XX_VOLT_RATIO(68, 1760);
0315         case 2:
0316             return SC27XX_VOLT_RATIO(68, 2327);
0317         case 3:
0318             return SC27XX_VOLT_RATIO(68, 3654);
0319         default:
0320             return SC27XX_VOLT_RATIO(1, 1);
0321         }
0322     case 15:
0323         switch (scale) {
0324         case 0:
0325             return SC27XX_VOLT_RATIO(1, 3);
0326         case 1:
0327             return SC27XX_VOLT_RATIO(1000, 5865);
0328         case 2:
0329             return SC27XX_VOLT_RATIO(500, 3879);
0330         case 3:
0331             return SC27XX_VOLT_RATIO(500, 6090);
0332         default:
0333             return SC27XX_VOLT_RATIO(1, 1);
0334         }
0335     case 16:
0336         switch (scale) {
0337         case 0:
0338             return SC27XX_VOLT_RATIO(48, 100);
0339         case 1:
0340             return SC27XX_VOLT_RATIO(480, 1955);
0341         case 2:
0342             return SC27XX_VOLT_RATIO(480, 2586);
0343         case 3:
0344             return SC27XX_VOLT_RATIO(48, 406);
0345         default:
0346             return SC27XX_VOLT_RATIO(1, 1);
0347         }
0348     case 21:
0349     case 22:
0350     case 23:
0351         switch (scale) {
0352         case 0:
0353             return SC27XX_VOLT_RATIO(3, 8);
0354         case 1:
0355             return SC27XX_VOLT_RATIO(375, 1955);
0356         case 2:
0357             return SC27XX_VOLT_RATIO(375, 2586);
0358         case 3:
0359             return SC27XX_VOLT_RATIO(300, 3248);
0360         default:
0361             return SC27XX_VOLT_RATIO(1, 1);
0362         }
0363     default:
0364         switch (scale) {
0365         case 0:
0366             return SC27XX_VOLT_RATIO(1, 1);
0367         case 1:
0368             return SC27XX_VOLT_RATIO(1000, 1955);
0369         case 2:
0370             return SC27XX_VOLT_RATIO(1000, 2586);
0371         case 3:
0372             return SC27XX_VOLT_RATIO(1000, 4060);
0373         default:
0374             return SC27XX_VOLT_RATIO(1, 1);
0375         }
0376     }
0377     return SC27XX_VOLT_RATIO(1, 1);
0378 }
0379
0380 static int sc2731_adc_get_ratio(int channel, int scale)
0381 {
0382     switch (channel) {
0383     case 1:
0384     case 2:
0385     case 3:
0386     case 4:
0387         return scale ? SC27XX_VOLT_RATIO(400, 1025) :
0388             SC27XX_VOLT_RATIO(1, 1);
0389     case 5:
0390         return SC27XX_VOLT_RATIO(7, 29);
0391     case 6:
0392         return SC27XX_VOLT_RATIO(375, 9000);
0393     case 7:
0394     case 8:
0395         return scale ? SC27XX_VOLT_RATIO(100, 125) :
0396             SC27XX_VOLT_RATIO(1, 1);
0397     case 19:
0398         return SC27XX_VOLT_RATIO(1, 3);
0399     default:
0400         return SC27XX_VOLT_RATIO(1, 1);
0401     }
0402     return SC27XX_VOLT_RATIO(1, 1);
0403 }
0404
0405 /*
0406  * According to the datasheet set specific value on some channel.
0407  */
0408 static void sc2720_adc_scale_init(struct sc27xx_adc_data *data)
0409 {
0410     int i;
0411
0412     for (i = 0; i < SC27XX_ADC_CHANNEL_MAX; i++) {
0413         switch (i) {
0414         case 5:
0415             data->channel_scale[i] = 3;
0416             break;
0417         case 7:
0418         case 9:
0419             data->channel_scale[i] = 2;
0420             break;
0421         case 13:
0422             data->channel_scale[i] = 1;
0423             break;
0424         case 19:
0425         case 30:
0426         case 31:
0427             data->channel_scale[i] = 3;
0428             break;
0429         default:
0430             data->channel_scale[i] = 0;
0431             break;
0432         }
0433     }
0434 }
0435
0436 static void sc2730_adc_scale_init(struct sc27xx_adc_data *data)
0437 {
0438     int i;
0439
0440     for (i = 0; i < SC27XX_ADC_CHANNEL_MAX; i++) {
0441         switch (i) {
0442         case 5:
0443         case 10:
0444         case 19:
0445         case 30:
0446         case 31:
0447             data->channel_scale[i] = 3;
0448             break;
0449         case 7:
0450         case 9:
0451             data->channel_scale[i] = 2;
0452             break;
0453         case 13:
0454             data->channel_scale[i] = 1;
0455             break;
0456         default:
0457             data->channel_scale[i] = 0;
0458             break;
0459         }
0460     }
0461 }
0462
0463 static void sc2731_adc_scale_init(struct sc27xx_adc_data *data)
0464 {
0465     int i;
0466     /*
0467      * In the current software design, SC2731 support 2 scales,
0468      * channels 5 uses big scale, others use smale.
0469      */
0470     for (i = 0; i < SC27XX_ADC_CHANNEL_MAX; i++) {
0471         switch (i) {
0472         case 5:
0473             data->channel_scale[i] = 1;
0474             break;
0475         default:
0476             data->channel_scale[i] = 0;
0477             break;
0478         }
0479     }
0480 }
0481
0482 static int sc27xx_adc_read(struct sc27xx_adc_data *data, int channel,
0483                int scale, int *val)
0484 {
0485     int ret, ret_volref;
0486     u32 tmp, value, status;
0487
0488     ret = hwspin_lock_timeout_raw(data->hwlock, SC27XX_ADC_HWLOCK_TIMEOUT);
0489     if (ret) {
0490         dev_err(data->dev, "timeout to get the hwspinlock\n");
0491         return ret;
0492     }
0493
0494     /*
0495      * According to the sc2721 chip data sheet, the reference voltage of
0496      * specific channel 30 and channel 31 in ADC module needs to be set from
0497      * the default 2.8v to 3.5v.
0498      */
0499     if ((data->var_data->set_volref) && (channel == 30 || channel == 31)) {
0500         ret = regulator_set_voltage(data->volref,
0501                     SC27XX_ADC_REFVOL_VDD35,
0502                     SC27XX_ADC_REFVOL_VDD35);
0503         if (ret) {
0504             dev_err(data->dev, "failed to set the volref 3.5v\n");
0505             goto unlock_adc;
0506         }
0507     }
0508
0509     ret = regmap_update_bits(data->regmap, data->base + SC27XX_ADC_CTL,
0510                  SC27XX_ADC_EN, SC27XX_ADC_EN);
0511     if (ret)
0512         goto regulator_restore;
0513
0514     ret = regmap_update_bits(data->regmap, data->base + SC27XX_ADC_INT_CLR,
0515                  SC27XX_ADC_IRQ_CLR, SC27XX_ADC_IRQ_CLR);
0516     if (ret)
0517         goto disable_adc;
0518
0519     /* Configure the channel id and scale */
0520     tmp = (scale << data->var_data->scale_shift) & data->var_data->scale_mask;
0521     tmp |= channel & SC27XX_ADC_CHN_ID_MASK;
0522     ret = regmap_update_bits(data->regmap, data->base + SC27XX_ADC_CH_CFG,
0523                  SC27XX_ADC_CHN_ID_MASK |
0524                  data->var_data->scale_mask,
0525                  tmp);
0526     if (ret)
0527         goto disable_adc;
0528
0529     /* Select 12bit conversion mode, and only sample 1 time */
0530     tmp = SC27XX_ADC_12BIT_MODE;
0531     tmp |= (0 << SC27XX_ADC_RUN_NUM_SHIFT) & SC27XX_ADC_RUN_NUM_MASK;
0532     ret = regmap_update_bits(data->regmap, data->base + SC27XX_ADC_CTL,
0533                  SC27XX_ADC_RUN_NUM_MASK | SC27XX_ADC_12BIT_MODE,
0534                  tmp);
0535     if (ret)
0536         goto disable_adc;
0537
0538     ret = regmap_update_bits(data->regmap, data->base + SC27XX_ADC_CTL,
0539                  SC27XX_ADC_CHN_RUN, SC27XX_ADC_CHN_RUN);
0540     if (ret)
0541         goto disable_adc;
0542
0543     ret = regmap_read_poll_timeout(data->regmap,
0544                        data->base + SC27XX_ADC_INT_RAW,
0545                        status, (status & SC27XX_ADC_IRQ_RAW),
0546                        SC27XX_ADC_POLL_RAW_STATUS,
0547                        SC27XX_ADC_RDY_TIMEOUT);
0548     if (ret) {
0549         dev_err(data->dev, "read adc timeout, status = 0x%x\n", status);
0550         goto disable_adc;
0551     }
0552
0553     ret = regmap_read(data->regmap, data->base + SC27XX_ADC_DATA, &value);
0554     if (ret)
0555         goto disable_adc;
0556
0557     value &= SC27XX_ADC_DATA_MASK;
0558
0559 disable_adc:
0560     regmap_update_bits(data->regmap, data->base + SC27XX_ADC_CTL,
0561                SC27XX_ADC_EN, 0);
0562 regulator_restore:
0563     if ((data->var_data->set_volref) && (channel == 30 || channel == 31)) {
0564         ret_volref = regulator_set_voltage(data->volref,
0565                         SC27XX_ADC_REFVOL_VDD28,
0566                         SC27XX_ADC_REFVOL_VDD28);
0567         if (ret_volref) {
0568             dev_err(data->dev, "failed to set the volref 2.8v,ret_volref = 0x%x\n",
0569                      ret_volref);
0570             ret = ret || ret_volref;
0571         }
0572     }
0573 unlock_adc:
0574     hwspin_unlock_raw(data->hwlock);
0575
0576     if (!ret)
0577         *val = value;
0578
0579     return ret;
0580 }
0581
0582 static void sc27xx_adc_volt_ratio(struct sc27xx_adc_data *data, int channel, int scale,
0583                   struct u32_fract *fract)
0584 {
0585     u32 ratio;
0586
0587     ratio = data->var_data->get_ratio(channel, scale);
0588     fract->numerator = ratio >> SC27XX_RATIO_NUMERATOR_OFFSET;
0589     fract->denominator = ratio & SC27XX_RATIO_DENOMINATOR_MASK;
0590 }
0591
0592 static int adc_to_volt(struct sc27xx_adc_linear_graph *graph,
0593                   int raw_adc)
0594 {
0595     int tmp;
0596
0597     tmp = (graph->volt0 - graph->volt1) * (raw_adc - graph->adc1);
0598     tmp /= (graph->adc0 - graph->adc1);
0599     tmp += graph->volt1;
0600
0601     return tmp;
0602 }
0603
0604 static int sc27xx_adc_to_volt(struct sc27xx_adc_linear_graph *graph,
0605                   int raw_adc)
0606 {
0607     int tmp;
0608
0609     tmp = adc_to_volt(graph, raw_adc);
0610
0611     return tmp < 0 ? 0 : tmp;
0612 }
0613
0614 static int sc27xx_adc_convert_volt(struct sc27xx_adc_data *data, int channel,
0615                    int scale, int raw_adc)
0616 {
0617     struct u32_fract fract;
0618     u32 volt;
0619
0620     /*
0621      * Convert ADC values to voltage values according to the linear graph,
0622      * and channel 5 and channel 1 has been calibrated, so we can just
0623      * return the voltage values calculated by the linear graph. But other
0624      * channels need be calculated to the real voltage values with the
0625      * voltage ratio.
0626      */
0627     switch (channel) {
0628     case 5:
0629         return sc27xx_adc_to_volt(&big_scale_graph, raw_adc);
0630
0631     case 1:
0632         return sc27xx_adc_to_volt(&small_scale_graph, raw_adc);
0633
0634     default:
0635         volt = sc27xx_adc_to_volt(&small_scale_graph, raw_adc);
0636         break;
0637     }
0638
0639     sc27xx_adc_volt_ratio(data, channel, scale, &fract);
0640
0641     return DIV_ROUND_CLOSEST(volt * fract.denominator, fract.numerator);
0642 }
0643
0644 static int sc27xx_adc_read_processed(struct sc27xx_adc_data *data,
0645                      int channel, int scale, int *val)
0646 {
0647     int ret, raw_adc;
0648
0649     ret = sc27xx_adc_read(data, channel, scale, &raw_adc);
0650     if (ret)
0651         return ret;
0652
0653     *val = sc27xx_adc_convert_volt(data, channel, scale, raw_adc);
0654     return 0;
0655 }
0656
0657 static int sc27xx_adc_read_raw(struct iio_dev *indio_dev,
0658                    struct iio_chan_spec const *chan,
0659                    int *val, int *val2, long mask)
0660 {
0661     struct sc27xx_adc_data *data = iio_priv(indio_dev);
0662     int scale = data->channel_scale[chan->channel];
0663     int ret, tmp;
0664
0665     switch (mask) {
0666     case IIO_CHAN_INFO_RAW:
0667         mutex_lock(&indio_dev->mlock);
0668         ret = sc27xx_adc_read(data, chan->channel, scale, &tmp);
0669         mutex_unlock(&indio_dev->mlock);
0670
0671         if (ret)
0672             return ret;
0673
0674         *val = tmp;
0675         return IIO_VAL_INT;
0676
0677     case IIO_CHAN_INFO_PROCESSED:
0678         mutex_lock(&indio_dev->mlock);
0679         ret = sc27xx_adc_read_processed(data, chan->channel, scale,
0680                         &tmp);
0681         mutex_unlock(&indio_dev->mlock);
0682
0683         if (ret)
0684             return ret;
0685
0686         *val = tmp;
0687         return IIO_VAL_INT;
0688
0689     case IIO_CHAN_INFO_SCALE:
0690         *val = scale;
0691         return IIO_VAL_INT;
0692
0693     default:
0694         return -EINVAL;
0695     }
0696 }
0697
0698 static int sc27xx_adc_write_raw(struct iio_dev *indio_dev,
0699                 struct iio_chan_spec const *chan,
0700                 int val, int val2, long mask)
0701 {
0702     struct sc27xx_adc_data *data = iio_priv(indio_dev);
0703
0704     switch (mask) {
0705     case IIO_CHAN_INFO_SCALE:
0706         data->channel_scale[chan->channel] = val;
0707         return IIO_VAL_INT;
0708
0709     default:
0710         return -EINVAL;
0711     }
0712 }
0713
0714 static const struct iio_info sc27xx_info = {
0715     .read_raw = &sc27xx_adc_read_raw,
0716     .write_raw = &sc27xx_adc_write_raw,
0717 };
0718
0719 #define SC27XX_ADC_CHANNEL(index, mask) {           \
0720     .type = IIO_VOLTAGE,                    \
0721     .channel = index,                   \
0722     .info_mask_separate = mask | BIT(IIO_CHAN_INFO_SCALE),  \
0723     .datasheet_name = "CH##index",              \
0724     .indexed = 1,                       \
0725 }
0726
0727 static const struct iio_chan_spec sc27xx_channels[] = {
0728     SC27XX_ADC_CHANNEL(0, BIT(IIO_CHAN_INFO_PROCESSED)),
0729     SC27XX_ADC_CHANNEL(1, BIT(IIO_CHAN_INFO_PROCESSED)),
0730     SC27XX_ADC_CHANNEL(2, BIT(IIO_CHAN_INFO_PROCESSED)),
0731     SC27XX_ADC_CHANNEL(3, BIT(IIO_CHAN_INFO_PROCESSED)),
0732     SC27XX_ADC_CHANNEL(4, BIT(IIO_CHAN_INFO_PROCESSED)),
0733     SC27XX_ADC_CHANNEL(5, BIT(IIO_CHAN_INFO_PROCESSED)),
0734     SC27XX_ADC_CHANNEL(6, BIT(IIO_CHAN_INFO_PROCESSED)),
0735     SC27XX_ADC_CHANNEL(7, BIT(IIO_CHAN_INFO_PROCESSED)),
0736     SC27XX_ADC_CHANNEL(8, BIT(IIO_CHAN_INFO_PROCESSED)),
0737     SC27XX_ADC_CHANNEL(9, BIT(IIO_CHAN_INFO_PROCESSED)),
0738     SC27XX_ADC_CHANNEL(10, BIT(IIO_CHAN_INFO_PROCESSED)),
0739     SC27XX_ADC_CHANNEL(11, BIT(IIO_CHAN_INFO_PROCESSED)),
0740     SC27XX_ADC_CHANNEL(12, BIT(IIO_CHAN_INFO_PROCESSED)),
0741     SC27XX_ADC_CHANNEL(13, BIT(IIO_CHAN_INFO_PROCESSED)),
0742     SC27XX_ADC_CHANNEL(14, BIT(IIO_CHAN_INFO_PROCESSED)),
0743     SC27XX_ADC_CHANNEL(15, BIT(IIO_CHAN_INFO_PROCESSED)),
0744     SC27XX_ADC_CHANNEL(16, BIT(IIO_CHAN_INFO_PROCESSED)),
0745     SC27XX_ADC_CHANNEL(17, BIT(IIO_CHAN_INFO_PROCESSED)),
0746     SC27XX_ADC_CHANNEL(18, BIT(IIO_CHAN_INFO_PROCESSED)),
0747     SC27XX_ADC_CHANNEL(19, BIT(IIO_CHAN_INFO_PROCESSED)),
0748     SC27XX_ADC_CHANNEL(20, BIT(IIO_CHAN_INFO_RAW)),
0749     SC27XX_ADC_CHANNEL(21, BIT(IIO_CHAN_INFO_PROCESSED)),
0750     SC27XX_ADC_CHANNEL(22, BIT(IIO_CHAN_INFO_PROCESSED)),
0751     SC27XX_ADC_CHANNEL(23, BIT(IIO_CHAN_INFO_PROCESSED)),
0752     SC27XX_ADC_CHANNEL(24, BIT(IIO_CHAN_INFO_PROCESSED)),
0753     SC27XX_ADC_CHANNEL(25, BIT(IIO_CHAN_INFO_PROCESSED)),
0754     SC27XX_ADC_CHANNEL(26, BIT(IIO_CHAN_INFO_PROCESSED)),
0755     SC27XX_ADC_CHANNEL(27, BIT(IIO_CHAN_INFO_PROCESSED)),
0756     SC27XX_ADC_CHANNEL(28, BIT(IIO_CHAN_INFO_PROCESSED)),
0757     SC27XX_ADC_CHANNEL(29, BIT(IIO_CHAN_INFO_PROCESSED)),
0758     SC27XX_ADC_CHANNEL(30, BIT(IIO_CHAN_INFO_PROCESSED)),
0759     SC27XX_ADC_CHANNEL(31, BIT(IIO_CHAN_INFO_PROCESSED)),
0760 };
0761
0762 static int sc27xx_adc_enable(struct sc27xx_adc_data *data)
0763 {
0764     int ret;
0765
0766     ret = regmap_update_bits(data->regmap, data->var_data->module_en,
0767                  SC27XX_MODULE_ADC_EN, SC27XX_MODULE_ADC_EN);
0768     if (ret)
0769         return ret;
0770
0771     /* Enable ADC work clock and controller clock */
0772     ret = regmap_update_bits(data->regmap, data->var_data->clk_en,
0773                  SC27XX_CLK_ADC_EN | SC27XX_CLK_ADC_CLK_EN,
0774                  SC27XX_CLK_ADC_EN | SC27XX_CLK_ADC_CLK_EN);
0775     if (ret)
0776         goto disable_adc;
0777
0778     /* ADC channel scales' calibration from nvmem device */
0779     ret = sc27xx_adc_scale_calibration(data, true);
0780     if (ret)
0781         goto disable_clk;
0782
0783     ret = sc27xx_adc_scale_calibration(data, false);
0784     if (ret)
0785         goto disable_clk;
0786
0787     return 0;
0788
0789 disable_clk:
0790     regmap_update_bits(data->regmap, data->var_data->clk_en,
0791                SC27XX_CLK_ADC_EN | SC27XX_CLK_ADC_CLK_EN, 0);
0792 disable_adc:
0793     regmap_update_bits(data->regmap, data->var_data->module_en,
0794                SC27XX_MODULE_ADC_EN, 0);
0795
0796     return ret;
0797 }
0798
0799 static void sc27xx_adc_disable(void *_data)
0800 {
0801     struct sc27xx_adc_data *data = _data;
0802
0803     /* Disable ADC work clock and controller clock */
0804     regmap_update_bits(data->regmap, data->var_data->clk_en,
0805                SC27XX_CLK_ADC_EN | SC27XX_CLK_ADC_CLK_EN, 0);
0806
0807     regmap_update_bits(data->regmap, data->var_data->module_en,
0808                SC27XX_MODULE_ADC_EN, 0);
0809 }
0810
0811 static const struct sc27xx_adc_variant_data sc2731_data = {
0812     .module_en = SC2731_MODULE_EN,
0813     .clk_en = SC2731_ARM_CLK_EN,
0814     .scale_shift = SC27XX_ADC_SCALE_SHIFT,
0815     .scale_mask = SC27XX_ADC_SCALE_MASK,
0816     .bscale_cal = &sc2731_big_scale_graph_calib,
0817     .sscale_cal = &sc2731_small_scale_graph_calib,
0818     .init_scale = sc2731_adc_scale_init,
0819     .get_ratio = sc2731_adc_get_ratio,
0820     .set_volref = false,
0821 };
0822
0823 static const struct sc27xx_adc_variant_data sc2730_data = {
0824     .module_en = SC2730_MODULE_EN,
0825     .clk_en = SC2730_ARM_CLK_EN,
0826     .scale_shift = SC27XX_ADC_SCALE_SHIFT,
0827     .scale_mask = SC27XX_ADC_SCALE_MASK,
0828     .bscale_cal = &big_scale_graph_calib,
0829     .sscale_cal = &small_scale_graph_calib,
0830     .init_scale = sc2730_adc_scale_init,
0831     .get_ratio = sc2730_adc_get_ratio,
0832     .set_volref = false,
0833 };
0834
0835 static const struct sc27xx_adc_variant_data sc2721_data = {
0836     .module_en = SC2731_MODULE_EN,
0837     .clk_en = SC2721_ARM_CLK_EN,
0838     .scale_shift = SC2721_ADC_SCALE_SHIFT,
0839     .scale_mask = SC2721_ADC_SCALE_MASK,
0840     .bscale_cal = &sc2731_big_scale_graph_calib,
0841     .sscale_cal = &sc2731_small_scale_graph_calib,
0842     .init_scale = sc2731_adc_scale_init,
0843     .get_ratio = sc2721_adc_get_ratio,
0844     .set_volref = true,
0845 };
0846
0847 static const struct sc27xx_adc_variant_data sc2720_data = {
0848     .module_en = SC2731_MODULE_EN,
0849     .clk_en = SC2721_ARM_CLK_EN,
0850     .scale_shift = SC27XX_ADC_SCALE_SHIFT,
0851     .scale_mask = SC27XX_ADC_SCALE_MASK,
0852     .bscale_cal = &big_scale_graph_calib,
0853     .sscale_cal = &small_scale_graph_calib,
0854     .init_scale = sc2720_adc_scale_init,
0855     .get_ratio = sc2720_adc_get_ratio,
0856     .set_volref = false,
0857 };
0858
0859 static int sc27xx_adc_probe(struct platform_device *pdev)
0860 {
0861     struct device *dev = &pdev->dev;
0862     struct device_node *np = dev->of_node;
0863     struct sc27xx_adc_data *sc27xx_data;
0864     const struct sc27xx_adc_variant_data *pdata;
0865     struct iio_dev *indio_dev;
0866     int ret;
0867
0868     pdata = of_device_get_match_data(dev);
0869     if (!pdata) {
0870         dev_err(dev, "No matching driver data found\n");
0871         return -EINVAL;
0872     }
0873
0874     indio_dev = devm_iio_device_alloc(dev, sizeof(*sc27xx_data));
0875     if (!indio_dev)
0876         return -ENOMEM;
0877
0878     sc27xx_data = iio_priv(indio_dev);
0879
0880     sc27xx_data->regmap = dev_get_regmap(dev->parent, NULL);
0881     if (!sc27xx_data->regmap) {
0882         dev_err(dev, "failed to get ADC regmap\n");
0883         return -ENODEV;
0884     }
0885
0886     ret = of_property_read_u32(np, "reg", &sc27xx_data->base);
0887     if (ret) {
0888         dev_err(dev, "failed to get ADC base address\n");
0889         return ret;
0890     }
0891
0892     sc27xx_data->irq = platform_get_irq(pdev, 0);
0893     if (sc27xx_data->irq < 0)
0894         return sc27xx_data->irq;
0895
0896     ret = of_hwspin_lock_get_id(np, 0);
0897     if (ret < 0) {
0898         dev_err(dev, "failed to get hwspinlock id\n");
0899         return ret;
0900     }
0901
0902     sc27xx_data->hwlock = devm_hwspin_lock_request_specific(dev, ret);
0903     if (!sc27xx_data->hwlock) {
0904         dev_err(dev, "failed to request hwspinlock\n");
0905         return -ENXIO;
0906     }
0907
0908     sc27xx_data->dev = dev;
0909     if (pdata->set_volref) {
0910         sc27xx_data->volref = devm_regulator_get(dev, "vref");
0911         if (IS_ERR(sc27xx_data->volref)) {
0912             ret = PTR_ERR(sc27xx_data->volref);
0913             return dev_err_probe(dev, ret, "failed to get ADC volref\n");
0914         }
0915     }
0916
0917     sc27xx_data->var_data = pdata;
0918     sc27xx_data->var_data->init_scale(sc27xx_data);
0919
0920     ret = sc27xx_adc_enable(sc27xx_data);
0921     if (ret) {
0922         dev_err(dev, "failed to enable ADC module\n");
0923         return ret;
0924     }
0925
0926     ret = devm_add_action_or_reset(dev, sc27xx_adc_disable, sc27xx_data);
0927     if (ret) {
0928         dev_err(dev, "failed to add ADC disable action\n");
0929         return ret;
0930     }
0931
0932     indio_dev->name = dev_name(dev);
0933     indio_dev->modes = INDIO_DIRECT_MODE;
0934     indio_dev->info = &sc27xx_info;
0935     indio_dev->channels = sc27xx_channels;
0936     indio_dev->num_channels = ARRAY_SIZE(sc27xx_channels);
0937     ret = devm_iio_device_register(dev, indio_dev);
0938     if (ret)
0939         dev_err(dev, "could not register iio (ADC)");
0940
0941     return ret;
0942 }
0943
0944 static const struct of_device_id sc27xx_adc_of_match[] = {
0945     { .compatible = "sprd,sc2731-adc", .data = &sc2731_data},
0946     { .compatible = "sprd,sc2730-adc", .data = &sc2730_data},
0947     { .compatible = "sprd,sc2721-adc", .data = &sc2721_data},
0948     { .compatible = "sprd,sc2720-adc", .data = &sc2720_data},
0949     { }
0950 };
0951 MODULE_DEVICE_TABLE(of, sc27xx_adc_of_match);
0952
0953 static struct platform_driver sc27xx_adc_driver = {
0954     .probe = sc27xx_adc_probe,
0955     .driver = {
0956         .name = "sc27xx-adc",
0957         .of_match_table = sc27xx_adc_of_match,
0958     },
0959 };
0960
0961 module_platform_driver(sc27xx_adc_driver);
0962
0963 MODULE_AUTHOR("Freeman Liu <freeman.liu@spreadtrum.com>");
0964 MODULE_DESCRIPTION("Spreadtrum SC27XX ADC Driver");
0965 MODULE_LICENSE("GPL v2");