iio/adc/rzg2l_adc.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * RZ/G2L A/D Converter driver
0004  *
0005  *  Copyright (c) 2021 Renesas Electronics Europe GmbH
0006  *
0007  * Author: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
0008  */
0009
0010 #include <linux/bitfield.h>
0011 #include <linux/clk.h>
0012 #include <linux/completion.h>
0013 #include <linux/delay.h>
0014 #include <linux/iio/iio.h>
0015 #include <linux/interrupt.h>
0016 #include <linux/io.h>
0017 #include <linux/mod_devicetable.h>
0018 #include <linux/module.h>
0019 #include <linux/platform_device.h>
0020 #include <linux/pm_runtime.h>
0021 #include <linux/property.h>
0022 #include <linux/reset.h>
0023
0024 #define DRIVER_NAME     "rzg2l-adc"
0025
0026 #define RZG2L_ADM(n)            ((n) * 0x4)
0027 #define RZG2L_ADM0_ADCE         BIT(0)
0028 #define RZG2L_ADM0_ADBSY        BIT(1)
0029 #define RZG2L_ADM0_PWDWNB       BIT(2)
0030 #define RZG2L_ADM0_SRESB        BIT(15)
0031 #define RZG2L_ADM1_TRG          BIT(0)
0032 #define RZG2L_ADM1_MS           BIT(2)
0033 #define RZG2L_ADM1_BS           BIT(4)
0034 #define RZG2L_ADM1_EGA_MASK     GENMASK(13, 12)
0035 #define RZG2L_ADM2_CHSEL_MASK       GENMASK(7, 0)
0036 #define RZG2L_ADM3_ADIL_MASK        GENMASK(31, 24)
0037 #define RZG2L_ADM3_ADCMP_MASK       GENMASK(23, 16)
0038 #define RZG2L_ADM3_ADCMP_E      FIELD_PREP(RZG2L_ADM3_ADCMP_MASK, 0xe)
0039 #define RZG2L_ADM3_ADSMP_MASK       GENMASK(15, 0)
0040
0041 #define RZG2L_ADINT         0x20
0042 #define RZG2L_ADINT_INTEN_MASK      GENMASK(7, 0)
0043 #define RZG2L_ADINT_CSEEN       BIT(16)
0044 #define RZG2L_ADINT_INTS        BIT(31)
0045
0046 #define RZG2L_ADSTS         0x24
0047 #define RZG2L_ADSTS_CSEST       BIT(16)
0048 #define RZG2L_ADSTS_INTST_MASK      GENMASK(7, 0)
0049
0050 #define RZG2L_ADIVC         0x28
0051 #define RZG2L_ADIVC_DIVADC_MASK     GENMASK(8, 0)
0052 #define RZG2L_ADIVC_DIVADC_4        FIELD_PREP(RZG2L_ADIVC_DIVADC_MASK, 0x4)
0053
0054 #define RZG2L_ADFIL         0x2c
0055
0056 #define RZG2L_ADCR(n)           (0x30 + ((n) * 0x4))
0057 #define RZG2L_ADCR_AD_MASK      GENMASK(11, 0)
0058
0059 #define RZG2L_ADSMP_DEFAULT_SAMPLING    0x578
0060
0061 #define RZG2L_ADC_MAX_CHANNELS      8
0062 #define RZG2L_ADC_CHN_MASK      0x7
0063 #define RZG2L_ADC_TIMEOUT       usecs_to_jiffies(1 * 4)
0064
0065 struct rzg2l_adc_data {
0066     const struct iio_chan_spec *channels;
0067     u8 num_channels;
0068 };
0069
0070 struct rzg2l_adc {
0071     void __iomem *base;
0072     struct clk *pclk;
0073     struct clk *adclk;
0074     struct reset_control *presetn;
0075     struct reset_control *adrstn;
0076     struct completion completion;
0077     const struct rzg2l_adc_data *data;
0078     struct mutex lock;
0079     u16 last_val[RZG2L_ADC_MAX_CHANNELS];
0080 };
0081
0082 static const char * const rzg2l_adc_channel_name[] = {
0083     "adc0",
0084     "adc1",
0085     "adc2",
0086     "adc3",
0087     "adc4",
0088     "adc5",
0089     "adc6",
0090     "adc7",
0091 };
0092
0093 static unsigned int rzg2l_adc_readl(struct rzg2l_adc *adc, u32 reg)
0094 {
0095     return readl(adc->base + reg);
0096 }
0097
0098 static void rzg2l_adc_writel(struct rzg2l_adc *adc, unsigned int reg, u32 val)
0099 {
0100     writel(val, adc->base + reg);
0101 }
0102
0103 static void rzg2l_adc_pwr(struct rzg2l_adc *adc, bool on)
0104 {
0105     u32 reg;
0106
0107     reg = rzg2l_adc_readl(adc, RZG2L_ADM(0));
0108     if (on)
0109         reg |= RZG2L_ADM0_PWDWNB;
0110     else
0111         reg &= ~RZG2L_ADM0_PWDWNB;
0112     rzg2l_adc_writel(adc, RZG2L_ADM(0), reg);
0113     udelay(2);
0114 }
0115
0116 static void rzg2l_adc_start_stop(struct rzg2l_adc *adc, bool start)
0117 {
0118     int timeout = 5;
0119     u32 reg;
0120
0121     reg = rzg2l_adc_readl(adc, RZG2L_ADM(0));
0122     if (start)
0123         reg |= RZG2L_ADM0_ADCE;
0124     else
0125         reg &= ~RZG2L_ADM0_ADCE;
0126     rzg2l_adc_writel(adc, RZG2L_ADM(0), reg);
0127
0128     if (start)
0129         return;
0130
0131     do {
0132         usleep_range(100, 200);
0133         reg = rzg2l_adc_readl(adc, RZG2L_ADM(0));
0134         timeout--;
0135         if (!timeout) {
0136             pr_err("%s stopping ADC timed out\n", __func__);
0137             break;
0138         }
0139     } while (((reg & RZG2L_ADM0_ADBSY) || (reg & RZG2L_ADM0_ADCE)));
0140 }
0141
0142 static void rzg2l_set_trigger(struct rzg2l_adc *adc)
0143 {
0144     u32 reg;
0145
0146     /*
0147      * Setup ADM1 for SW trigger
0148      * EGA[13:12] - Set 00 to indicate hardware trigger is invalid
0149      * BS[4] - Enable 1-buffer mode
0150      * MS[1] - Enable Select mode
0151      * TRG[0] - Enable software trigger mode
0152      */
0153     reg = rzg2l_adc_readl(adc, RZG2L_ADM(1));
0154     reg &= ~RZG2L_ADM1_EGA_MASK;
0155     reg &= ~RZG2L_ADM1_BS;
0156     reg &= ~RZG2L_ADM1_TRG;
0157     reg |= RZG2L_ADM1_MS;
0158     rzg2l_adc_writel(adc, RZG2L_ADM(1), reg);
0159 }
0160
0161 static int rzg2l_adc_conversion_setup(struct rzg2l_adc *adc, u8 ch)
0162 {
0163     u32 reg;
0164
0165     if (rzg2l_adc_readl(adc, RZG2L_ADM(0)) & RZG2L_ADM0_ADBSY)
0166         return -EBUSY;
0167
0168     rzg2l_set_trigger(adc);
0169
0170     /* Select analog input channel subjected to conversion. */
0171     reg = rzg2l_adc_readl(adc, RZG2L_ADM(2));
0172     reg &= ~RZG2L_ADM2_CHSEL_MASK;
0173     reg |= BIT(ch);
0174     rzg2l_adc_writel(adc, RZG2L_ADM(2), reg);
0175
0176     /*
0177      * Setup ADINT
0178      * INTS[31] - Select pulse signal
0179      * CSEEN[16] - Enable channel select error interrupt
0180      * INTEN[7:0] - Select channel interrupt
0181      */
0182     reg = rzg2l_adc_readl(adc, RZG2L_ADINT);
0183     reg &= ~RZG2L_ADINT_INTS;
0184     reg &= ~RZG2L_ADINT_INTEN_MASK;
0185     reg |= (RZG2L_ADINT_CSEEN | BIT(ch));
0186     rzg2l_adc_writel(adc, RZG2L_ADINT, reg);
0187
0188     return 0;
0189 }
0190
0191 static int rzg2l_adc_set_power(struct iio_dev *indio_dev, bool on)
0192 {
0193     struct device *dev = indio_dev->dev.parent;
0194
0195     if (on)
0196         return pm_runtime_resume_and_get(dev);
0197
0198     return pm_runtime_put_sync(dev);
0199 }
0200
0201 static int rzg2l_adc_conversion(struct iio_dev *indio_dev, struct rzg2l_adc *adc, u8 ch)
0202 {
0203     int ret;
0204
0205     ret = rzg2l_adc_set_power(indio_dev, true);
0206     if (ret)
0207         return ret;
0208
0209     ret = rzg2l_adc_conversion_setup(adc, ch);
0210     if (ret) {
0211         rzg2l_adc_set_power(indio_dev, false);
0212         return ret;
0213     }
0214
0215     reinit_completion(&adc->completion);
0216
0217     rzg2l_adc_start_stop(adc, true);
0218
0219     if (!wait_for_completion_timeout(&adc->completion, RZG2L_ADC_TIMEOUT)) {
0220         rzg2l_adc_writel(adc, RZG2L_ADINT,
0221                  rzg2l_adc_readl(adc, RZG2L_ADINT) & ~RZG2L_ADINT_INTEN_MASK);
0222         rzg2l_adc_start_stop(adc, false);
0223         rzg2l_adc_set_power(indio_dev, false);
0224         return -ETIMEDOUT;
0225     }
0226
0227     return rzg2l_adc_set_power(indio_dev, false);
0228 }
0229
0230 static int rzg2l_adc_read_raw(struct iio_dev *indio_dev,
0231                   struct iio_chan_spec const *chan,
0232                   int *val, int *val2, long mask)
0233 {
0234     struct rzg2l_adc *adc = iio_priv(indio_dev);
0235     int ret;
0236     u8 ch;
0237
0238     switch (mask) {
0239     case IIO_CHAN_INFO_RAW:
0240         if (chan->type != IIO_VOLTAGE)
0241             return -EINVAL;
0242
0243         mutex_lock(&adc->lock);
0244         ch = chan->channel & RZG2L_ADC_CHN_MASK;
0245         ret = rzg2l_adc_conversion(indio_dev, adc, ch);
0246         if (ret) {
0247             mutex_unlock(&adc->lock);
0248             return ret;
0249         }
0250         *val = adc->last_val[ch];
0251         mutex_unlock(&adc->lock);
0252
0253         return IIO_VAL_INT;
0254
0255     default:
0256         return -EINVAL;
0257     }
0258 }
0259
0260 static int rzg2l_adc_read_label(struct iio_dev *iio_dev,
0261                 const struct iio_chan_spec *chan,
0262                 char *label)
0263 {
0264     return sysfs_emit(label, "%s\n", rzg2l_adc_channel_name[chan->channel]);
0265 }
0266
0267 static const struct iio_info rzg2l_adc_iio_info = {
0268     .read_raw = rzg2l_adc_read_raw,
0269     .read_label = rzg2l_adc_read_label,
0270 };
0271
0272 static irqreturn_t rzg2l_adc_isr(int irq, void *dev_id)
0273 {
0274     struct rzg2l_adc *adc = dev_id;
0275     unsigned long intst;
0276     u32 reg;
0277     int ch;
0278
0279     reg = rzg2l_adc_readl(adc, RZG2L_ADSTS);
0280
0281     /* A/D conversion channel select error interrupt */
0282     if (reg & RZG2L_ADSTS_CSEST) {
0283         rzg2l_adc_writel(adc, RZG2L_ADSTS, reg);
0284         return IRQ_HANDLED;
0285     }
0286
0287     intst = reg & RZG2L_ADSTS_INTST_MASK;
0288     if (!intst)
0289         return IRQ_NONE;
0290
0291     for_each_set_bit(ch, &intst, RZG2L_ADC_MAX_CHANNELS)
0292         adc->last_val[ch] = rzg2l_adc_readl(adc, RZG2L_ADCR(ch)) & RZG2L_ADCR_AD_MASK;
0293
0294     /* clear the channel interrupt */
0295     rzg2l_adc_writel(adc, RZG2L_ADSTS, reg);
0296
0297     complete(&adc->completion);
0298
0299     return IRQ_HANDLED;
0300 }
0301
0302 static int rzg2l_adc_parse_properties(struct platform_device *pdev, struct rzg2l_adc *adc)
0303 {
0304     struct iio_chan_spec *chan_array;
0305     struct fwnode_handle *fwnode;
0306     struct rzg2l_adc_data *data;
0307     unsigned int channel;
0308     int num_channels;
0309     int ret;
0310     u8 i;
0311
0312     data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
0313     if (!data)
0314         return -ENOMEM;
0315
0316     num_channels = device_get_child_node_count(&pdev->dev);
0317     if (!num_channels) {
0318         dev_err(&pdev->dev, "no channel children\n");
0319         return -ENODEV;
0320     }
0321
0322     if (num_channels > RZG2L_ADC_MAX_CHANNELS) {
0323         dev_err(&pdev->dev, "num of channel children out of range\n");
0324         return -EINVAL;
0325     }
0326
0327     chan_array = devm_kcalloc(&pdev->dev, num_channels, sizeof(*chan_array),
0328                   GFP_KERNEL);
0329     if (!chan_array)
0330         return -ENOMEM;
0331
0332     i = 0;
0333     device_for_each_child_node(&pdev->dev, fwnode) {
0334         ret = fwnode_property_read_u32(fwnode, "reg", &channel);
0335         if (ret) {
0336             fwnode_handle_put(fwnode);
0337             return ret;
0338         }
0339
0340         if (channel >= RZG2L_ADC_MAX_CHANNELS) {
0341             fwnode_handle_put(fwnode);
0342             return -EINVAL;
0343         }
0344
0345         chan_array[i].type = IIO_VOLTAGE;
0346         chan_array[i].indexed = 1;
0347         chan_array[i].channel = channel;
0348         chan_array[i].info_mask_separate = BIT(IIO_CHAN_INFO_RAW);
0349         chan_array[i].datasheet_name = rzg2l_adc_channel_name[channel];
0350         i++;
0351     }
0352
0353     data->num_channels = num_channels;
0354     data->channels = chan_array;
0355     adc->data = data;
0356
0357     return 0;
0358 }
0359
0360 static int rzg2l_adc_hw_init(struct rzg2l_adc *adc)
0361 {
0362     int timeout = 5;
0363     u32 reg;
0364     int ret;
0365
0366     ret = clk_prepare_enable(adc->pclk);
0367     if (ret)
0368         return ret;
0369
0370     /* SW reset */
0371     reg = rzg2l_adc_readl(adc, RZG2L_ADM(0));
0372     reg |= RZG2L_ADM0_SRESB;
0373     rzg2l_adc_writel(adc, RZG2L_ADM(0), reg);
0374
0375     while (!(rzg2l_adc_readl(adc, RZG2L_ADM(0)) & RZG2L_ADM0_SRESB)) {
0376         if (!timeout) {
0377             ret = -EBUSY;
0378             goto exit_hw_init;
0379         }
0380         timeout--;
0381         usleep_range(100, 200);
0382     }
0383
0384     /* Only division by 4 can be set */
0385     reg = rzg2l_adc_readl(adc, RZG2L_ADIVC);
0386     reg &= ~RZG2L_ADIVC_DIVADC_MASK;
0387     reg |= RZG2L_ADIVC_DIVADC_4;
0388     rzg2l_adc_writel(adc, RZG2L_ADIVC, reg);
0389
0390     /*
0391      * Setup AMD3
0392      * ADIL[31:24] - Should be always set to 0
0393      * ADCMP[23:16] - Should be always set to 0xe
0394      * ADSMP[15:0] - Set default (0x578) sampling period
0395      */
0396     reg = rzg2l_adc_readl(adc, RZG2L_ADM(3));
0397     reg &= ~RZG2L_ADM3_ADIL_MASK;
0398     reg &= ~RZG2L_ADM3_ADCMP_MASK;
0399     reg &= ~RZG2L_ADM3_ADSMP_MASK;
0400     reg |= (RZG2L_ADM3_ADCMP_E | RZG2L_ADSMP_DEFAULT_SAMPLING);
0401     rzg2l_adc_writel(adc, RZG2L_ADM(3), reg);
0402
0403 exit_hw_init:
0404     clk_disable_unprepare(adc->pclk);
0405
0406     return ret;
0407 }
0408
0409 static void rzg2l_adc_pm_runtime_disable(void *data)
0410 {
0411     struct device *dev = data;
0412
0413     pm_runtime_disable(dev->parent);
0414 }
0415
0416 static void rzg2l_adc_pm_runtime_set_suspended(void *data)
0417 {
0418     struct device *dev = data;
0419
0420     pm_runtime_set_suspended(dev->parent);
0421 }
0422
0423 static void rzg2l_adc_reset_assert(void *data)
0424 {
0425     reset_control_assert(data);
0426 }
0427
0428 static int rzg2l_adc_probe(struct platform_device *pdev)
0429 {
0430     struct device *dev = &pdev->dev;
0431     struct iio_dev *indio_dev;
0432     struct rzg2l_adc *adc;
0433     int ret;
0434     int irq;
0435
0436     indio_dev = devm_iio_device_alloc(dev, sizeof(*adc));
0437     if (!indio_dev)
0438         return -ENOMEM;
0439
0440     adc = iio_priv(indio_dev);
0441
0442     ret = rzg2l_adc_parse_properties(pdev, adc);
0443     if (ret)
0444         return ret;
0445
0446     mutex_init(&adc->lock);
0447
0448     adc->base = devm_platform_ioremap_resource(pdev, 0);
0449     if (IS_ERR(adc->base))
0450         return PTR_ERR(adc->base);
0451
0452     adc->pclk = devm_clk_get(dev, "pclk");
0453     if (IS_ERR(adc->pclk)) {
0454         dev_err(dev, "Failed to get pclk");
0455         return PTR_ERR(adc->pclk);
0456     }
0457
0458     adc->adclk = devm_clk_get(dev, "adclk");
0459     if (IS_ERR(adc->adclk)) {
0460         dev_err(dev, "Failed to get adclk");
0461         return PTR_ERR(adc->adclk);
0462     }
0463
0464     adc->adrstn = devm_reset_control_get_exclusive(dev, "adrst-n");
0465     if (IS_ERR(adc->adrstn)) {
0466         dev_err(dev, "failed to get adrstn\n");
0467         return PTR_ERR(adc->adrstn);
0468     }
0469
0470     adc->presetn = devm_reset_control_get_exclusive(dev, "presetn");
0471     if (IS_ERR(adc->presetn)) {
0472         dev_err(dev, "failed to get presetn\n");
0473         return PTR_ERR(adc->presetn);
0474     }
0475
0476     ret = reset_control_deassert(adc->adrstn);
0477     if (ret) {
0478         dev_err(&pdev->dev, "failed to deassert adrstn pin, %d\n", ret);
0479         return ret;
0480     }
0481
0482     ret = devm_add_action_or_reset(&pdev->dev,
0483                        rzg2l_adc_reset_assert, adc->adrstn);
0484     if (ret) {
0485         dev_err(&pdev->dev, "failed to register adrstn assert devm action, %d\n",
0486             ret);
0487         return ret;
0488     }
0489
0490     ret = reset_control_deassert(adc->presetn);
0491     if (ret) {
0492         dev_err(&pdev->dev, "failed to deassert presetn pin, %d\n", ret);
0493         return ret;
0494     }
0495
0496     ret = devm_add_action_or_reset(&pdev->dev,
0497                        rzg2l_adc_reset_assert, adc->presetn);
0498     if (ret) {
0499         dev_err(&pdev->dev, "failed to register presetn assert devm action, %d\n",
0500             ret);
0501         return ret;
0502     }
0503
0504     ret = rzg2l_adc_hw_init(adc);
0505     if (ret) {
0506         dev_err(&pdev->dev, "failed to initialize ADC HW, %d\n", ret);
0507         return ret;
0508     }
0509
0510     irq = platform_get_irq(pdev, 0);
0511     if (irq < 0)
0512         return irq;
0513
0514     ret = devm_request_irq(dev, irq, rzg2l_adc_isr,
0515                    0, dev_name(dev), adc);
0516     if (ret < 0)
0517         return ret;
0518
0519     init_completion(&adc->completion);
0520
0521     platform_set_drvdata(pdev, indio_dev);
0522
0523     indio_dev->name = DRIVER_NAME;
0524     indio_dev->info = &rzg2l_adc_iio_info;
0525     indio_dev->modes = INDIO_DIRECT_MODE;
0526     indio_dev->channels = adc->data->channels;
0527     indio_dev->num_channels = adc->data->num_channels;
0528
0529     pm_runtime_set_suspended(dev);
0530     ret = devm_add_action_or_reset(&pdev->dev,
0531                        rzg2l_adc_pm_runtime_set_suspended, &indio_dev->dev);
0532     if (ret)
0533         return ret;
0534
0535     pm_runtime_enable(dev);
0536     ret = devm_add_action_or_reset(&pdev->dev,
0537                        rzg2l_adc_pm_runtime_disable, &indio_dev->dev);
0538     if (ret)
0539         return ret;
0540
0541     return devm_iio_device_register(dev, indio_dev);
0542 }
0543
0544 static const struct of_device_id rzg2l_adc_match[] = {
0545     { .compatible = "renesas,rzg2l-adc",},
0546     { /* sentinel */ }
0547 };
0548 MODULE_DEVICE_TABLE(of, rzg2l_adc_match);
0549
0550 static int __maybe_unused rzg2l_adc_pm_runtime_suspend(struct device *dev)
0551 {
0552     struct iio_dev *indio_dev = dev_get_drvdata(dev);
0553     struct rzg2l_adc *adc = iio_priv(indio_dev);
0554
0555     rzg2l_adc_pwr(adc, false);
0556     clk_disable_unprepare(adc->adclk);
0557     clk_disable_unprepare(adc->pclk);
0558
0559     return 0;
0560 }
0561
0562 static int __maybe_unused rzg2l_adc_pm_runtime_resume(struct device *dev)
0563 {
0564     struct iio_dev *indio_dev = dev_get_drvdata(dev);
0565     struct rzg2l_adc *adc = iio_priv(indio_dev);
0566     int ret;
0567
0568     ret = clk_prepare_enable(adc->pclk);
0569     if (ret)
0570         return ret;
0571
0572     ret = clk_prepare_enable(adc->adclk);
0573     if (ret) {
0574         clk_disable_unprepare(adc->pclk);
0575         return ret;
0576     }
0577
0578     rzg2l_adc_pwr(adc, true);
0579
0580     return 0;
0581 }
0582
0583 static const struct dev_pm_ops rzg2l_adc_pm_ops = {
0584     SET_RUNTIME_PM_OPS(rzg2l_adc_pm_runtime_suspend,
0585                rzg2l_adc_pm_runtime_resume,
0586                NULL)
0587 };
0588
0589 static struct platform_driver rzg2l_adc_driver = {
0590     .probe      = rzg2l_adc_probe,
0591     .driver     = {
0592         .name       = DRIVER_NAME,
0593         .of_match_table = rzg2l_adc_match,
0594         .pm     = &rzg2l_adc_pm_ops,
0595     },
0596 };
0597
0598 module_platform_driver(rzg2l_adc_driver);
0599
0600 MODULE_AUTHOR("Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>");
0601 MODULE_DESCRIPTION("Renesas RZ/G2L ADC driver");
0602 MODULE_LICENSE("GPL v2");