iio/adc/rockchip_saradc.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Rockchip Successive Approximation Register (SAR) A/D Converter
0004  * Copyright (C) 2014 ROCKCHIP, Inc.
0005  */
0006
0007 #include <linux/module.h>
0008 #include <linux/platform_device.h>
0009 #include <linux/interrupt.h>
0010 #include <linux/io.h>
0011 #include <linux/of.h>
0012 #include <linux/of_device.h>
0013 #include <linux/clk.h>
0014 #include <linux/completion.h>
0015 #include <linux/delay.h>
0016 #include <linux/reset.h>
0017 #include <linux/regulator/consumer.h>
0018 #include <linux/iio/buffer.h>
0019 #include <linux/iio/iio.h>
0020 #include <linux/iio/trigger_consumer.h>
0021 #include <linux/iio/triggered_buffer.h>
0022
0023 #define SARADC_DATA         0x00
0024
0025 #define SARADC_STAS         0x04
0026 #define SARADC_STAS_BUSY        BIT(0)
0027
0028 #define SARADC_CTRL         0x08
0029 #define SARADC_CTRL_IRQ_STATUS      BIT(6)
0030 #define SARADC_CTRL_IRQ_ENABLE      BIT(5)
0031 #define SARADC_CTRL_POWER_CTRL      BIT(3)
0032 #define SARADC_CTRL_CHN_MASK        0x7
0033
0034 #define SARADC_DLY_PU_SOC       0x0c
0035 #define SARADC_DLY_PU_SOC_MASK      0x3f
0036
0037 #define SARADC_TIMEOUT          msecs_to_jiffies(100)
0038 #define SARADC_MAX_CHANNELS     8
0039
0040 struct rockchip_saradc_data {
0041     const struct iio_chan_spec  *channels;
0042     int             num_channels;
0043     unsigned long           clk_rate;
0044 };
0045
0046 struct rockchip_saradc {
0047     void __iomem        *regs;
0048     struct clk      *pclk;
0049     struct clk      *clk;
0050     struct completion   completion;
0051     struct regulator    *vref;
0052     int         uv_vref;
0053     struct reset_control    *reset;
0054     const struct rockchip_saradc_data *data;
0055     u16         last_val;
0056     const struct iio_chan_spec *last_chan;
0057     struct notifier_block nb;
0058 };
0059
0060 static void rockchip_saradc_power_down(struct rockchip_saradc *info)
0061 {
0062     /* Clear irq & power down adc */
0063     writel_relaxed(0, info->regs + SARADC_CTRL);
0064 }
0065
0066 static int rockchip_saradc_conversion(struct rockchip_saradc *info,
0067                    struct iio_chan_spec const *chan)
0068 {
0069     reinit_completion(&info->completion);
0070
0071     /* 8 clock periods as delay between power up and start cmd */
0072     writel_relaxed(8, info->regs + SARADC_DLY_PU_SOC);
0073
0074     info->last_chan = chan;
0075
0076     /* Select the channel to be used and trigger conversion */
0077     writel(SARADC_CTRL_POWER_CTRL
0078             | (chan->channel & SARADC_CTRL_CHN_MASK)
0079             | SARADC_CTRL_IRQ_ENABLE,
0080            info->regs + SARADC_CTRL);
0081
0082     if (!wait_for_completion_timeout(&info->completion, SARADC_TIMEOUT))
0083         return -ETIMEDOUT;
0084
0085     return 0;
0086 }
0087
0088 static int rockchip_saradc_read_raw(struct iio_dev *indio_dev,
0089                     struct iio_chan_spec const *chan,
0090                     int *val, int *val2, long mask)
0091 {
0092     struct rockchip_saradc *info = iio_priv(indio_dev);
0093     int ret;
0094
0095     switch (mask) {
0096     case IIO_CHAN_INFO_RAW:
0097         mutex_lock(&indio_dev->mlock);
0098
0099         ret = rockchip_saradc_conversion(info, chan);
0100         if (ret) {
0101             rockchip_saradc_power_down(info);
0102             mutex_unlock(&indio_dev->mlock);
0103             return ret;
0104         }
0105
0106         *val = info->last_val;
0107         mutex_unlock(&indio_dev->mlock);
0108         return IIO_VAL_INT;
0109     case IIO_CHAN_INFO_SCALE:
0110         *val = info->uv_vref / 1000;
0111         *val2 = chan->scan_type.realbits;
0112         return IIO_VAL_FRACTIONAL_LOG2;
0113     default:
0114         return -EINVAL;
0115     }
0116 }
0117
0118 static irqreturn_t rockchip_saradc_isr(int irq, void *dev_id)
0119 {
0120     struct rockchip_saradc *info = dev_id;
0121
0122     /* Read value */
0123     info->last_val = readl_relaxed(info->regs + SARADC_DATA);
0124     info->last_val &= GENMASK(info->last_chan->scan_type.realbits - 1, 0);
0125
0126     rockchip_saradc_power_down(info);
0127
0128     complete(&info->completion);
0129
0130     return IRQ_HANDLED;
0131 }
0132
0133 static const struct iio_info rockchip_saradc_iio_info = {
0134     .read_raw = rockchip_saradc_read_raw,
0135 };
0136
0137 #define SARADC_CHANNEL(_index, _id, _res) {         \
0138     .type = IIO_VOLTAGE,                    \
0139     .indexed = 1,                       \
0140     .channel = _index,                  \
0141     .info_mask_separate = BIT(IIO_CHAN_INFO_RAW),       \
0142     .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),   \
0143     .datasheet_name = _id,                  \
0144     .scan_index = _index,                   \
0145     .scan_type = {                      \
0146         .sign = 'u',                    \
0147         .realbits = _res,               \
0148         .storagebits = 16,              \
0149         .endianness = IIO_CPU,              \
0150     },                          \
0151 }
0152
0153 static const struct iio_chan_spec rockchip_saradc_iio_channels[] = {
0154     SARADC_CHANNEL(0, "adc0", 10),
0155     SARADC_CHANNEL(1, "adc1", 10),
0156     SARADC_CHANNEL(2, "adc2", 10),
0157 };
0158
0159 static const struct rockchip_saradc_data saradc_data = {
0160     .channels = rockchip_saradc_iio_channels,
0161     .num_channels = ARRAY_SIZE(rockchip_saradc_iio_channels),
0162     .clk_rate = 1000000,
0163 };
0164
0165 static const struct iio_chan_spec rockchip_rk3066_tsadc_iio_channels[] = {
0166     SARADC_CHANNEL(0, "adc0", 12),
0167     SARADC_CHANNEL(1, "adc1", 12),
0168 };
0169
0170 static const struct rockchip_saradc_data rk3066_tsadc_data = {
0171     .channels = rockchip_rk3066_tsadc_iio_channels,
0172     .num_channels = ARRAY_SIZE(rockchip_rk3066_tsadc_iio_channels),
0173     .clk_rate = 50000,
0174 };
0175
0176 static const struct iio_chan_spec rockchip_rk3399_saradc_iio_channels[] = {
0177     SARADC_CHANNEL(0, "adc0", 10),
0178     SARADC_CHANNEL(1, "adc1", 10),
0179     SARADC_CHANNEL(2, "adc2", 10),
0180     SARADC_CHANNEL(3, "adc3", 10),
0181     SARADC_CHANNEL(4, "adc4", 10),
0182     SARADC_CHANNEL(5, "adc5", 10),
0183 };
0184
0185 static const struct rockchip_saradc_data rk3399_saradc_data = {
0186     .channels = rockchip_rk3399_saradc_iio_channels,
0187     .num_channels = ARRAY_SIZE(rockchip_rk3399_saradc_iio_channels),
0188     .clk_rate = 1000000,
0189 };
0190
0191 static const struct iio_chan_spec rockchip_rk3568_saradc_iio_channels[] = {
0192     SARADC_CHANNEL(0, "adc0", 10),
0193     SARADC_CHANNEL(1, "adc1", 10),
0194     SARADC_CHANNEL(2, "adc2", 10),
0195     SARADC_CHANNEL(3, "adc3", 10),
0196     SARADC_CHANNEL(4, "adc4", 10),
0197     SARADC_CHANNEL(5, "adc5", 10),
0198     SARADC_CHANNEL(6, "adc6", 10),
0199     SARADC_CHANNEL(7, "adc7", 10),
0200 };
0201
0202 static const struct rockchip_saradc_data rk3568_saradc_data = {
0203     .channels = rockchip_rk3568_saradc_iio_channels,
0204     .num_channels = ARRAY_SIZE(rockchip_rk3568_saradc_iio_channels),
0205     .clk_rate = 1000000,
0206 };
0207
0208 static const struct of_device_id rockchip_saradc_match[] = {
0209     {
0210         .compatible = "rockchip,saradc",
0211         .data = &saradc_data,
0212     }, {
0213         .compatible = "rockchip,rk3066-tsadc",
0214         .data = &rk3066_tsadc_data,
0215     }, {
0216         .compatible = "rockchip,rk3399-saradc",
0217         .data = &rk3399_saradc_data,
0218     }, {
0219         .compatible = "rockchip,rk3568-saradc",
0220         .data = &rk3568_saradc_data,
0221     },
0222     {},
0223 };
0224 MODULE_DEVICE_TABLE(of, rockchip_saradc_match);
0225
0226 /*
0227  * Reset SARADC Controller.
0228  */
0229 static void rockchip_saradc_reset_controller(struct reset_control *reset)
0230 {
0231     reset_control_assert(reset);
0232     usleep_range(10, 20);
0233     reset_control_deassert(reset);
0234 }
0235
0236 static void rockchip_saradc_clk_disable(void *data)
0237 {
0238     struct rockchip_saradc *info = data;
0239
0240     clk_disable_unprepare(info->clk);
0241 }
0242
0243 static void rockchip_saradc_pclk_disable(void *data)
0244 {
0245     struct rockchip_saradc *info = data;
0246
0247     clk_disable_unprepare(info->pclk);
0248 }
0249
0250 static void rockchip_saradc_regulator_disable(void *data)
0251 {
0252     struct rockchip_saradc *info = data;
0253
0254     regulator_disable(info->vref);
0255 }
0256
0257 static irqreturn_t rockchip_saradc_trigger_handler(int irq, void *p)
0258 {
0259     struct iio_poll_func *pf = p;
0260     struct iio_dev *i_dev = pf->indio_dev;
0261     struct rockchip_saradc *info = iio_priv(i_dev);
0262     /*
0263      * @values: each channel takes an u16 value
0264      * @timestamp: will be 8-byte aligned automatically
0265      */
0266     struct {
0267         u16 values[SARADC_MAX_CHANNELS];
0268         int64_t timestamp;
0269     } data;
0270     int ret;
0271     int i, j = 0;
0272
0273     mutex_lock(&i_dev->mlock);
0274
0275     for_each_set_bit(i, i_dev->active_scan_mask, i_dev->masklength) {
0276         const struct iio_chan_spec *chan = &i_dev->channels[i];
0277
0278         ret = rockchip_saradc_conversion(info, chan);
0279         if (ret) {
0280             rockchip_saradc_power_down(info);
0281             goto out;
0282         }
0283
0284         data.values[j] = info->last_val;
0285         j++;
0286     }
0287
0288     iio_push_to_buffers_with_timestamp(i_dev, &data, iio_get_time_ns(i_dev));
0289 out:
0290     mutex_unlock(&i_dev->mlock);
0291
0292     iio_trigger_notify_done(i_dev->trig);
0293
0294     return IRQ_HANDLED;
0295 }
0296
0297 static int rockchip_saradc_volt_notify(struct notifier_block *nb,
0298                            unsigned long event,
0299                            void *data)
0300 {
0301     struct rockchip_saradc *info =
0302             container_of(nb, struct rockchip_saradc, nb);
0303
0304     if (event & REGULATOR_EVENT_VOLTAGE_CHANGE)
0305         info->uv_vref = (unsigned long)data;
0306
0307     return NOTIFY_OK;
0308 }
0309
0310 static void rockchip_saradc_regulator_unreg_notifier(void *data)
0311 {
0312     struct rockchip_saradc *info = data;
0313
0314     regulator_unregister_notifier(info->vref, &info->nb);
0315 }
0316
0317 static int rockchip_saradc_probe(struct platform_device *pdev)
0318 {
0319     struct rockchip_saradc *info = NULL;
0320     struct device_node *np = pdev->dev.of_node;
0321     struct iio_dev *indio_dev = NULL;
0322     const struct of_device_id *match;
0323     int ret;
0324     int irq;
0325
0326     if (!np)
0327         return -ENODEV;
0328
0329     indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*info));
0330     if (!indio_dev) {
0331         dev_err(&pdev->dev, "failed allocating iio device\n");
0332         return -ENOMEM;
0333     }
0334     info = iio_priv(indio_dev);
0335
0336     match = of_match_device(rockchip_saradc_match, &pdev->dev);
0337     if (!match) {
0338         dev_err(&pdev->dev, "failed to match device\n");
0339         return -ENODEV;
0340     }
0341
0342     info->data = match->data;
0343
0344     /* Sanity check for possible later IP variants with more channels */
0345     if (info->data->num_channels > SARADC_MAX_CHANNELS) {
0346         dev_err(&pdev->dev, "max channels exceeded");
0347         return -EINVAL;
0348     }
0349
0350     info->regs = devm_platform_ioremap_resource(pdev, 0);
0351     if (IS_ERR(info->regs))
0352         return PTR_ERR(info->regs);
0353
0354     /*
0355      * The reset should be an optional property, as it should work
0356      * with old devicetrees as well
0357      */
0358     info->reset = devm_reset_control_get_exclusive(&pdev->dev,
0359                                "saradc-apb");
0360     if (IS_ERR(info->reset)) {
0361         ret = PTR_ERR(info->reset);
0362         if (ret != -ENOENT)
0363             return dev_err_probe(&pdev->dev, ret,
0364                          "failed to get saradc-apb\n");
0365
0366         dev_dbg(&pdev->dev, "no reset control found\n");
0367         info->reset = NULL;
0368     }
0369
0370     init_completion(&info->completion);
0371
0372     irq = platform_get_irq(pdev, 0);
0373     if (irq < 0)
0374         return dev_err_probe(&pdev->dev, irq, "failed to get irq\n");
0375
0376     ret = devm_request_irq(&pdev->dev, irq, rockchip_saradc_isr,
0377                    0, dev_name(&pdev->dev), info);
0378     if (ret < 0) {
0379         dev_err(&pdev->dev, "failed requesting irq %d\n", irq);
0380         return ret;
0381     }
0382
0383     info->pclk = devm_clk_get(&pdev->dev, "apb_pclk");
0384     if (IS_ERR(info->pclk))
0385         return dev_err_probe(&pdev->dev, PTR_ERR(info->pclk),
0386                      "failed to get pclk\n");
0387
0388     info->clk = devm_clk_get(&pdev->dev, "saradc");
0389     if (IS_ERR(info->clk))
0390         return dev_err_probe(&pdev->dev, PTR_ERR(info->clk),
0391                      "failed to get adc clock\n");
0392
0393     info->vref = devm_regulator_get(&pdev->dev, "vref");
0394     if (IS_ERR(info->vref))
0395         return dev_err_probe(&pdev->dev, PTR_ERR(info->vref),
0396                      "failed to get regulator\n");
0397
0398     if (info->reset)
0399         rockchip_saradc_reset_controller(info->reset);
0400
0401     /*
0402      * Use a default value for the converter clock.
0403      * This may become user-configurable in the future.
0404      */
0405     ret = clk_set_rate(info->clk, info->data->clk_rate);
0406     if (ret < 0) {
0407         dev_err(&pdev->dev, "failed to set adc clk rate, %d\n", ret);
0408         return ret;
0409     }
0410
0411     ret = regulator_enable(info->vref);
0412     if (ret < 0) {
0413         dev_err(&pdev->dev, "failed to enable vref regulator\n");
0414         return ret;
0415     }
0416     ret = devm_add_action_or_reset(&pdev->dev,
0417                        rockchip_saradc_regulator_disable, info);
0418     if (ret) {
0419         dev_err(&pdev->dev, "failed to register devm action, %d\n",
0420             ret);
0421         return ret;
0422     }
0423
0424     ret = regulator_get_voltage(info->vref);
0425     if (ret < 0)
0426         return ret;
0427
0428     info->uv_vref = ret;
0429
0430     ret = clk_prepare_enable(info->pclk);
0431     if (ret < 0) {
0432         dev_err(&pdev->dev, "failed to enable pclk\n");
0433         return ret;
0434     }
0435     ret = devm_add_action_or_reset(&pdev->dev,
0436                        rockchip_saradc_pclk_disable, info);
0437     if (ret) {
0438         dev_err(&pdev->dev, "failed to register devm action, %d\n",
0439             ret);
0440         return ret;
0441     }
0442
0443     ret = clk_prepare_enable(info->clk);
0444     if (ret < 0) {
0445         dev_err(&pdev->dev, "failed to enable converter clock\n");
0446         return ret;
0447     }
0448     ret = devm_add_action_or_reset(&pdev->dev,
0449                        rockchip_saradc_clk_disable, info);
0450     if (ret) {
0451         dev_err(&pdev->dev, "failed to register devm action, %d\n",
0452             ret);
0453         return ret;
0454     }
0455
0456     platform_set_drvdata(pdev, indio_dev);
0457
0458     indio_dev->name = dev_name(&pdev->dev);
0459     indio_dev->info = &rockchip_saradc_iio_info;
0460     indio_dev->modes = INDIO_DIRECT_MODE;
0461
0462     indio_dev->channels = info->data->channels;
0463     indio_dev->num_channels = info->data->num_channels;
0464     ret = devm_iio_triggered_buffer_setup(&indio_dev->dev, indio_dev, NULL,
0465                           rockchip_saradc_trigger_handler,
0466                           NULL);
0467     if (ret)
0468         return ret;
0469
0470     info->nb.notifier_call = rockchip_saradc_volt_notify;
0471     ret = regulator_register_notifier(info->vref, &info->nb);
0472     if (ret)
0473         return ret;
0474
0475     ret = devm_add_action_or_reset(&pdev->dev,
0476                        rockchip_saradc_regulator_unreg_notifier,
0477                        info);
0478     if (ret)
0479         return ret;
0480
0481     return devm_iio_device_register(&pdev->dev, indio_dev);
0482 }
0483
0484 static int rockchip_saradc_suspend(struct device *dev)
0485 {
0486     struct iio_dev *indio_dev = dev_get_drvdata(dev);
0487     struct rockchip_saradc *info = iio_priv(indio_dev);
0488
0489     clk_disable_unprepare(info->clk);
0490     clk_disable_unprepare(info->pclk);
0491     regulator_disable(info->vref);
0492
0493     return 0;
0494 }
0495
0496 static int rockchip_saradc_resume(struct device *dev)
0497 {
0498     struct iio_dev *indio_dev = dev_get_drvdata(dev);
0499     struct rockchip_saradc *info = iio_priv(indio_dev);
0500     int ret;
0501
0502     ret = regulator_enable(info->vref);
0503     if (ret)
0504         return ret;
0505
0506     ret = clk_prepare_enable(info->pclk);
0507     if (ret)
0508         return ret;
0509
0510     ret = clk_prepare_enable(info->clk);
0511     if (ret)
0512         clk_disable_unprepare(info->pclk);
0513
0514     return ret;
0515 }
0516
0517 static DEFINE_SIMPLE_DEV_PM_OPS(rockchip_saradc_pm_ops,
0518                 rockchip_saradc_suspend,
0519                 rockchip_saradc_resume);
0520
0521 static struct platform_driver rockchip_saradc_driver = {
0522     .probe      = rockchip_saradc_probe,
0523     .driver     = {
0524         .name   = "rockchip-saradc",
0525         .of_match_table = rockchip_saradc_match,
0526         .pm = pm_sleep_ptr(&rockchip_saradc_pm_ops),
0527     },
0528 };
0529
0530 module_platform_driver(rockchip_saradc_driver);
0531
0532 MODULE_AUTHOR("Heiko Stuebner <heiko@sntech.de>");
0533 MODULE_DESCRIPTION("Rockchip SARADC driver");
0534 MODULE_LICENSE("GPL v2");