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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (c) 2016-2017, 2019, The Linux Foundation. All rights reserved.
0004  * Copyright (c) 2022 Linaro Limited.
0005  *  Author: Caleb Connolly <caleb.connolly@linaro.org>
0006  *
0007  * This driver is for the Round Robin ADC found in the pmi8998 and pm660 PMICs.
0008  */
0009 
0010 #include <linux/bitfield.h>
0011 #include <linux/delay.h>
0012 #include <linux/kernel.h>
0013 #include <linux/math64.h>
0014 #include <linux/module.h>
0015 #include <linux/mod_devicetable.h>
0016 #include <linux/platform_device.h>
0017 #include <linux/property.h>
0018 #include <linux/regmap.h>
0019 #include <linux/spmi.h>
0020 #include <linux/types.h>
0021 #include <linux/units.h>
0022 
0023 #include <asm/unaligned.h>
0024 
0025 #include <linux/iio/iio.h>
0026 #include <linux/iio/types.h>
0027 
0028 #include <soc/qcom/qcom-spmi-pmic.h>
0029 
0030 #define DRIVER_NAME "qcom-spmi-rradc"
0031 
0032 #define RR_ADC_EN_CTL 0x46
0033 #define RR_ADC_SKIN_TEMP_LSB 0x50
0034 #define RR_ADC_SKIN_TEMP_MSB 0x51
0035 #define RR_ADC_CTL 0x52
0036 #define RR_ADC_CTL_CONTINUOUS_SEL BIT(3)
0037 #define RR_ADC_LOG 0x53
0038 #define RR_ADC_LOG_CLR_CTRL BIT(0)
0039 
0040 #define RR_ADC_FAKE_BATT_LOW_LSB 0x58
0041 #define RR_ADC_FAKE_BATT_LOW_MSB 0x59
0042 #define RR_ADC_FAKE_BATT_HIGH_LSB 0x5A
0043 #define RR_ADC_FAKE_BATT_HIGH_MSB 0x5B
0044 
0045 #define RR_ADC_BATT_ID_CTRL 0x60
0046 #define RR_ADC_BATT_ID_CTRL_CHANNEL_CONV BIT(0)
0047 #define RR_ADC_BATT_ID_TRIGGER 0x61
0048 #define RR_ADC_BATT_ID_STS 0x62
0049 #define RR_ADC_BATT_ID_CFG 0x63
0050 #define BATT_ID_SETTLE_MASK GENMASK(7, 5)
0051 #define RR_ADC_BATT_ID_5_LSB 0x66
0052 #define RR_ADC_BATT_ID_5_MSB 0x67
0053 #define RR_ADC_BATT_ID_15_LSB 0x68
0054 #define RR_ADC_BATT_ID_15_MSB 0x69
0055 #define RR_ADC_BATT_ID_150_LSB 0x6A
0056 #define RR_ADC_BATT_ID_150_MSB 0x6B
0057 
0058 #define RR_ADC_BATT_THERM_CTRL 0x70
0059 #define RR_ADC_BATT_THERM_TRIGGER 0x71
0060 #define RR_ADC_BATT_THERM_STS 0x72
0061 #define RR_ADC_BATT_THERM_CFG 0x73
0062 #define RR_ADC_BATT_THERM_LSB 0x74
0063 #define RR_ADC_BATT_THERM_MSB 0x75
0064 #define RR_ADC_BATT_THERM_FREQ 0x76
0065 
0066 #define RR_ADC_AUX_THERM_CTRL 0x80
0067 #define RR_ADC_AUX_THERM_TRIGGER 0x81
0068 #define RR_ADC_AUX_THERM_STS 0x82
0069 #define RR_ADC_AUX_THERM_CFG 0x83
0070 #define RR_ADC_AUX_THERM_LSB 0x84
0071 #define RR_ADC_AUX_THERM_MSB 0x85
0072 
0073 #define RR_ADC_SKIN_HOT 0x86
0074 #define RR_ADC_SKIN_TOO_HOT 0x87
0075 
0076 #define RR_ADC_AUX_THERM_C1 0x88
0077 #define RR_ADC_AUX_THERM_C2 0x89
0078 #define RR_ADC_AUX_THERM_C3 0x8A
0079 #define RR_ADC_AUX_THERM_HALF_RANGE 0x8B
0080 
0081 #define RR_ADC_USB_IN_V_CTRL 0x90
0082 #define RR_ADC_USB_IN_V_TRIGGER 0x91
0083 #define RR_ADC_USB_IN_V_STS 0x92
0084 #define RR_ADC_USB_IN_V_LSB 0x94
0085 #define RR_ADC_USB_IN_V_MSB 0x95
0086 #define RR_ADC_USB_IN_I_CTRL 0x98
0087 #define RR_ADC_USB_IN_I_TRIGGER 0x99
0088 #define RR_ADC_USB_IN_I_STS 0x9A
0089 #define RR_ADC_USB_IN_I_LSB 0x9C
0090 #define RR_ADC_USB_IN_I_MSB 0x9D
0091 
0092 #define RR_ADC_DC_IN_V_CTRL 0xA0
0093 #define RR_ADC_DC_IN_V_TRIGGER 0xA1
0094 #define RR_ADC_DC_IN_V_STS 0xA2
0095 #define RR_ADC_DC_IN_V_LSB 0xA4
0096 #define RR_ADC_DC_IN_V_MSB 0xA5
0097 #define RR_ADC_DC_IN_I_CTRL 0xA8
0098 #define RR_ADC_DC_IN_I_TRIGGER 0xA9
0099 #define RR_ADC_DC_IN_I_STS 0xAA
0100 #define RR_ADC_DC_IN_I_LSB 0xAC
0101 #define RR_ADC_DC_IN_I_MSB 0xAD
0102 
0103 #define RR_ADC_PMI_DIE_TEMP_CTRL 0xB0
0104 #define RR_ADC_PMI_DIE_TEMP_TRIGGER 0xB1
0105 #define RR_ADC_PMI_DIE_TEMP_STS 0xB2
0106 #define RR_ADC_PMI_DIE_TEMP_CFG 0xB3
0107 #define RR_ADC_PMI_DIE_TEMP_LSB 0xB4
0108 #define RR_ADC_PMI_DIE_TEMP_MSB 0xB5
0109 
0110 #define RR_ADC_CHARGER_TEMP_CTRL 0xB8
0111 #define RR_ADC_CHARGER_TEMP_TRIGGER 0xB9
0112 #define RR_ADC_CHARGER_TEMP_STS 0xBA
0113 #define RR_ADC_CHARGER_TEMP_CFG 0xBB
0114 #define RR_ADC_CHARGER_TEMP_LSB 0xBC
0115 #define RR_ADC_CHARGER_TEMP_MSB 0xBD
0116 #define RR_ADC_CHARGER_HOT 0xBE
0117 #define RR_ADC_CHARGER_TOO_HOT 0xBF
0118 
0119 #define RR_ADC_GPIO_CTRL 0xC0
0120 #define RR_ADC_GPIO_TRIGGER 0xC1
0121 #define RR_ADC_GPIO_STS 0xC2
0122 #define RR_ADC_GPIO_LSB 0xC4
0123 #define RR_ADC_GPIO_MSB 0xC5
0124 
0125 #define RR_ADC_ATEST_CTRL 0xC8
0126 #define RR_ADC_ATEST_TRIGGER 0xC9
0127 #define RR_ADC_ATEST_STS 0xCA
0128 #define RR_ADC_ATEST_LSB 0xCC
0129 #define RR_ADC_ATEST_MSB 0xCD
0130 #define RR_ADC_SEC_ACCESS 0xD0
0131 
0132 #define RR_ADC_PERPH_RESET_CTL2 0xD9
0133 #define RR_ADC_PERPH_RESET_CTL3 0xDA
0134 #define RR_ADC_PERPH_RESET_CTL4 0xDB
0135 #define RR_ADC_INT_TEST1 0xE0
0136 #define RR_ADC_INT_TEST_VAL 0xE1
0137 
0138 #define RR_ADC_TM_TRIGGER_CTRLS 0xE2
0139 #define RR_ADC_TM_ADC_CTRLS 0xE3
0140 #define RR_ADC_TM_CNL_CTRL 0xE4
0141 #define RR_ADC_TM_BATT_ID_CTRL 0xE5
0142 #define RR_ADC_TM_THERM_CTRL 0xE6
0143 #define RR_ADC_TM_CONV_STS 0xE7
0144 #define RR_ADC_TM_ADC_READ_LSB 0xE8
0145 #define RR_ADC_TM_ADC_READ_MSB 0xE9
0146 #define RR_ADC_TM_ATEST_MUX_1 0xEA
0147 #define RR_ADC_TM_ATEST_MUX_2 0xEB
0148 #define RR_ADC_TM_REFERENCES 0xED
0149 #define RR_ADC_TM_MISC_CTL 0xEE
0150 #define RR_ADC_TM_RR_CTRL 0xEF
0151 
0152 #define RR_ADC_TRIGGER_EVERY_CYCLE BIT(7)
0153 #define RR_ADC_TRIGGER_CTL BIT(0)
0154 
0155 #define RR_ADC_BATT_ID_RANGE 820
0156 
0157 #define RR_ADC_BITS 10
0158 #define RR_ADC_CHAN_MSB (1 << RR_ADC_BITS)
0159 #define RR_ADC_FS_VOLTAGE_MV 2500
0160 
0161 /* BATT_THERM 0.25K/LSB */
0162 #define RR_ADC_BATT_THERM_LSB_K 4
0163 
0164 #define RR_ADC_TEMP_FS_VOLTAGE_NUM 5000000
0165 #define RR_ADC_TEMP_FS_VOLTAGE_DEN 3
0166 #define RR_ADC_DIE_TEMP_OFFSET 601400
0167 #define RR_ADC_DIE_TEMP_SLOPE 2
0168 #define RR_ADC_DIE_TEMP_OFFSET_MILLI_DEGC 25000
0169 
0170 #define RR_ADC_CHG_TEMP_GF_OFFSET_UV 1303168
0171 #define RR_ADC_CHG_TEMP_GF_SLOPE_UV_PER_C 3784
0172 #define RR_ADC_CHG_TEMP_SMIC_OFFSET_UV 1338433
0173 #define RR_ADC_CHG_TEMP_SMIC_SLOPE_UV_PER_C 3655
0174 #define RR_ADC_CHG_TEMP_660_GF_OFFSET_UV 1309001
0175 #define RR_ADC_CHG_TEMP_660_GF_SLOPE_UV_PER_C 3403
0176 #define RR_ADC_CHG_TEMP_660_SMIC_OFFSET_UV 1295898
0177 #define RR_ADC_CHG_TEMP_660_SMIC_SLOPE_UV_PER_C 3596
0178 #define RR_ADC_CHG_TEMP_660_MGNA_OFFSET_UV 1314779
0179 #define RR_ADC_CHG_TEMP_660_MGNA_SLOPE_UV_PER_C 3496
0180 #define RR_ADC_CHG_TEMP_OFFSET_MILLI_DEGC 25000
0181 #define RR_ADC_CHG_THRESHOLD_SCALE 4
0182 
0183 #define RR_ADC_VOLT_INPUT_FACTOR 8
0184 #define RR_ADC_CURR_INPUT_FACTOR 2000
0185 #define RR_ADC_CURR_USBIN_INPUT_FACTOR_MIL 1886
0186 #define RR_ADC_CURR_USBIN_660_FACTOR_MIL 9
0187 #define RR_ADC_CURR_USBIN_660_UV_VAL 579500
0188 
0189 #define RR_ADC_GPIO_FS_RANGE 5000
0190 #define RR_ADC_COHERENT_CHECK_RETRY 5
0191 #define RR_ADC_CHAN_MAX_CONTINUOUS_BUFFER_LEN 16
0192 
0193 #define RR_ADC_STS_CHANNEL_READING_MASK GENMASK(1, 0)
0194 #define RR_ADC_STS_CHANNEL_STS BIT(1)
0195 
0196 #define RR_ADC_TP_REV_VERSION1 21
0197 #define RR_ADC_TP_REV_VERSION2 29
0198 #define RR_ADC_TP_REV_VERSION3 32
0199 
0200 #define RRADC_BATT_ID_DELAY_MAX 8
0201 
0202 enum rradc_channel_id {
0203     RR_ADC_BATT_ID = 0,
0204     RR_ADC_BATT_THERM,
0205     RR_ADC_SKIN_TEMP,
0206     RR_ADC_USBIN_I,
0207     RR_ADC_USBIN_V,
0208     RR_ADC_DCIN_I,
0209     RR_ADC_DCIN_V,
0210     RR_ADC_DIE_TEMP,
0211     RR_ADC_CHG_TEMP,
0212     RR_ADC_GPIO,
0213     RR_ADC_CHAN_MAX
0214 };
0215 
0216 struct rradc_chip;
0217 
0218 /**
0219  * struct rradc_channel - rradc channel data
0220  * @label:      channel label
0221  * @lsb:        Channel least significant byte
0222  * @status:     Channel status address
0223  * @size:       number of bytes to read
0224  * @trigger_addr:   Trigger address, trigger is only used on some channels
0225  * @trigger_mask:   Trigger mask
0226  * @scale_fn:       Post process callback for channels which can't be exposed
0227  *          as offset + scale.
0228  */
0229 struct rradc_channel {
0230     const char *label;
0231     u8 lsb;
0232     u8 status;
0233     int size;
0234     int trigger_addr;
0235     int trigger_mask;
0236     int (*scale_fn)(struct rradc_chip *chip, u16 adc_code, int *result);
0237 };
0238 
0239 struct rradc_chip {
0240     struct device *dev;
0241     const struct qcom_spmi_pmic *pmic;
0242     /*
0243      * Lock held while doing channel conversion
0244      * involving multiple register read/writes
0245      */
0246     struct mutex conversion_lock;
0247     struct regmap *regmap;
0248     u32 base;
0249     int batt_id_delay;
0250     u16 batt_id_data;
0251 };
0252 
0253 static const int batt_id_delays[] = { 0, 1, 4, 12, 20, 40, 60, 80 };
0254 static const struct rradc_channel rradc_chans[RR_ADC_CHAN_MAX];
0255 static const struct iio_chan_spec rradc_iio_chans[RR_ADC_CHAN_MAX];
0256 
0257 static int rradc_read(struct rradc_chip *chip, u16 addr, __le16 *buf, int len)
0258 {
0259     int ret, retry_cnt = 0;
0260     __le16 data_check[RR_ADC_CHAN_MAX_CONTINUOUS_BUFFER_LEN / 2];
0261 
0262     if (len > RR_ADC_CHAN_MAX_CONTINUOUS_BUFFER_LEN) {
0263         dev_err(chip->dev,
0264             "Can't read more than %d bytes, but asked to read %d bytes.\n",
0265             RR_ADC_CHAN_MAX_CONTINUOUS_BUFFER_LEN, len);
0266         return -EINVAL;
0267     }
0268 
0269     while (retry_cnt < RR_ADC_COHERENT_CHECK_RETRY) {
0270         ret = regmap_bulk_read(chip->regmap, chip->base + addr, buf,
0271                        len);
0272         if (ret < 0) {
0273             dev_err(chip->dev, "rr_adc reg 0x%x failed :%d\n", addr,
0274                 ret);
0275             return ret;
0276         }
0277 
0278         ret = regmap_bulk_read(chip->regmap, chip->base + addr,
0279                        data_check, len);
0280         if (ret < 0) {
0281             dev_err(chip->dev, "rr_adc reg 0x%x failed :%d\n", addr,
0282                 ret);
0283             return ret;
0284         }
0285 
0286         if (memcmp(buf, data_check, len) != 0) {
0287             retry_cnt++;
0288             dev_dbg(chip->dev,
0289                 "coherent read error, retry_cnt:%d\n",
0290                 retry_cnt);
0291             continue;
0292         }
0293 
0294         break;
0295     }
0296 
0297     if (retry_cnt == RR_ADC_COHERENT_CHECK_RETRY)
0298         dev_err(chip->dev, "Retry exceeded for coherency check\n");
0299 
0300     return ret;
0301 }
0302 
0303 static int rradc_get_fab_coeff(struct rradc_chip *chip, int64_t *offset,
0304                    int64_t *slope)
0305 {
0306     if (chip->pmic->subtype == PM660_SUBTYPE) {
0307         switch (chip->pmic->fab_id) {
0308         case PM660_FAB_ID_GF:
0309             *offset = RR_ADC_CHG_TEMP_660_GF_OFFSET_UV;
0310             *slope = RR_ADC_CHG_TEMP_660_GF_SLOPE_UV_PER_C;
0311             return 0;
0312         case PM660_FAB_ID_TSMC:
0313             *offset = RR_ADC_CHG_TEMP_660_SMIC_OFFSET_UV;
0314             *slope = RR_ADC_CHG_TEMP_660_SMIC_SLOPE_UV_PER_C;
0315             return 0;
0316         default:
0317             *offset = RR_ADC_CHG_TEMP_660_MGNA_OFFSET_UV;
0318             *slope = RR_ADC_CHG_TEMP_660_MGNA_SLOPE_UV_PER_C;
0319         }
0320     } else if (chip->pmic->subtype == PMI8998_SUBTYPE) {
0321         switch (chip->pmic->fab_id) {
0322         case PMI8998_FAB_ID_GF:
0323             *offset = RR_ADC_CHG_TEMP_GF_OFFSET_UV;
0324             *slope = RR_ADC_CHG_TEMP_GF_SLOPE_UV_PER_C;
0325             return 0;
0326         case PMI8998_FAB_ID_SMIC:
0327             *offset = RR_ADC_CHG_TEMP_SMIC_OFFSET_UV;
0328             *slope = RR_ADC_CHG_TEMP_SMIC_SLOPE_UV_PER_C;
0329             return 0;
0330         default:
0331             return -EINVAL;
0332         }
0333     }
0334 
0335     return -EINVAL;
0336 }
0337 
0338 /*
0339  * These functions explicitly cast int64_t to int.
0340  * They will never overflow, as the values are small enough.
0341  */
0342 static int rradc_post_process_batt_id(struct rradc_chip *chip, u16 adc_code,
0343                       int *result_ohms)
0344 {
0345     uint32_t current_value;
0346     int64_t r_id;
0347 
0348     current_value = chip->batt_id_data;
0349     r_id = ((int64_t)adc_code * RR_ADC_FS_VOLTAGE_MV);
0350     r_id = div64_s64(r_id, (RR_ADC_CHAN_MSB * current_value));
0351     *result_ohms = (int)(r_id * MILLI);
0352 
0353     return 0;
0354 }
0355 
0356 static int rradc_enable_continuous_mode(struct rradc_chip *chip)
0357 {
0358     int ret;
0359 
0360     /* Clear channel log */
0361     ret = regmap_update_bits(chip->regmap, chip->base + RR_ADC_LOG,
0362                  RR_ADC_LOG_CLR_CTRL, RR_ADC_LOG_CLR_CTRL);
0363     if (ret < 0) {
0364         dev_err(chip->dev, "log ctrl update to clear failed:%d\n", ret);
0365         return ret;
0366     }
0367 
0368     ret = regmap_update_bits(chip->regmap, chip->base + RR_ADC_LOG,
0369                  RR_ADC_LOG_CLR_CTRL, 0);
0370     if (ret < 0) {
0371         dev_err(chip->dev, "log ctrl update to not clear failed:%d\n",
0372             ret);
0373         return ret;
0374     }
0375 
0376     /* Switch to continuous mode */
0377     ret = regmap_update_bits(chip->regmap, chip->base + RR_ADC_CTL,
0378                  RR_ADC_CTL_CONTINUOUS_SEL,
0379                  RR_ADC_CTL_CONTINUOUS_SEL);
0380     if (ret < 0)
0381         dev_err(chip->dev, "Update to continuous mode failed:%d\n",
0382             ret);
0383 
0384     return ret;
0385 }
0386 
0387 static int rradc_disable_continuous_mode(struct rradc_chip *chip)
0388 {
0389     int ret;
0390 
0391     /* Switch to non continuous mode */
0392     ret = regmap_update_bits(chip->regmap, chip->base + RR_ADC_CTL,
0393                  RR_ADC_CTL_CONTINUOUS_SEL, 0);
0394     if (ret < 0)
0395         dev_err(chip->dev, "Update to non-continuous mode failed:%d\n",
0396             ret);
0397 
0398     return ret;
0399 }
0400 
0401 static bool rradc_is_ready(struct rradc_chip *chip,
0402                enum rradc_channel_id chan_address)
0403 {
0404     const struct rradc_channel *chan = &rradc_chans[chan_address];
0405     int ret;
0406     unsigned int status, mask;
0407 
0408     /* BATT_ID STS bit does not get set initially */
0409     switch (chan_address) {
0410     case RR_ADC_BATT_ID:
0411         mask = RR_ADC_STS_CHANNEL_STS;
0412         break;
0413     default:
0414         mask = RR_ADC_STS_CHANNEL_READING_MASK;
0415         break;
0416     }
0417 
0418     ret = regmap_read(chip->regmap, chip->base + chan->status, &status);
0419     if (ret < 0 || !(status & mask))
0420         return false;
0421 
0422     return true;
0423 }
0424 
0425 static int rradc_read_status_in_cont_mode(struct rradc_chip *chip,
0426                       enum rradc_channel_id chan_address)
0427 {
0428     const struct rradc_channel *chan = &rradc_chans[chan_address];
0429     const struct iio_chan_spec *iio_chan = &rradc_iio_chans[chan_address];
0430     int ret, i;
0431 
0432     if (chan->trigger_mask == 0) {
0433         dev_err(chip->dev, "Channel doesn't have a trigger mask\n");
0434         return -EINVAL;
0435     }
0436 
0437     ret = regmap_update_bits(chip->regmap, chip->base + chan->trigger_addr,
0438                  chan->trigger_mask, chan->trigger_mask);
0439     if (ret < 0) {
0440         dev_err(chip->dev,
0441             "Failed to apply trigger for channel '%s' ret=%d\n",
0442             iio_chan->extend_name, ret);
0443         return ret;
0444     }
0445 
0446     ret = rradc_enable_continuous_mode(chip);
0447     if (ret < 0) {
0448         dev_err(chip->dev, "Failed to switch to continuous mode\n");
0449         goto disable_trigger;
0450     }
0451 
0452     /*
0453      * The wait/sleep values were found through trial and error,
0454      * this is mostly for the battery ID channel which takes some
0455      * time to settle.
0456      */
0457     for (i = 0; i < 5; i++) {
0458         if (rradc_is_ready(chip, chan_address))
0459             break;
0460         usleep_range(50000, 50000 + 500);
0461     }
0462 
0463     if (i == 5) {
0464         dev_err(chip->dev, "Channel '%s' is not ready\n",
0465             iio_chan->extend_name);
0466         ret = -ETIMEDOUT;
0467     }
0468 
0469     rradc_disable_continuous_mode(chip);
0470 
0471 disable_trigger:
0472     regmap_update_bits(chip->regmap, chip->base + chan->trigger_addr,
0473                chan->trigger_mask, 0);
0474 
0475     return ret;
0476 }
0477 
0478 static int rradc_prepare_batt_id_conversion(struct rradc_chip *chip,
0479                         enum rradc_channel_id chan_address,
0480                         u16 *data)
0481 {
0482     int ret;
0483 
0484     ret = regmap_update_bits(chip->regmap, chip->base + RR_ADC_BATT_ID_CTRL,
0485                  RR_ADC_BATT_ID_CTRL_CHANNEL_CONV,
0486                  RR_ADC_BATT_ID_CTRL_CHANNEL_CONV);
0487     if (ret < 0) {
0488         dev_err(chip->dev, "Enabling BATT ID channel failed:%d\n", ret);
0489         return ret;
0490     }
0491 
0492     ret = regmap_update_bits(chip->regmap,
0493                  chip->base + RR_ADC_BATT_ID_TRIGGER,
0494                  RR_ADC_TRIGGER_CTL, RR_ADC_TRIGGER_CTL);
0495     if (ret < 0) {
0496         dev_err(chip->dev, "BATT_ID trigger set failed:%d\n", ret);
0497         goto out_disable_batt_id;
0498     }
0499 
0500     ret = rradc_read_status_in_cont_mode(chip, chan_address);
0501 
0502     /* Reset registers back to default values */
0503     regmap_update_bits(chip->regmap, chip->base + RR_ADC_BATT_ID_TRIGGER,
0504                RR_ADC_TRIGGER_CTL, 0);
0505 
0506 out_disable_batt_id:
0507     regmap_update_bits(chip->regmap, chip->base + RR_ADC_BATT_ID_CTRL,
0508                RR_ADC_BATT_ID_CTRL_CHANNEL_CONV, 0);
0509 
0510     return ret;
0511 }
0512 
0513 static int rradc_do_conversion(struct rradc_chip *chip,
0514                    enum rradc_channel_id chan_address, u16 *data)
0515 {
0516     const struct rradc_channel *chan = &rradc_chans[chan_address];
0517     const struct iio_chan_spec *iio_chan = &rradc_iio_chans[chan_address];
0518     int ret;
0519     __le16 buf[3];
0520 
0521     mutex_lock(&chip->conversion_lock);
0522 
0523     switch (chan_address) {
0524     case RR_ADC_BATT_ID:
0525         ret = rradc_prepare_batt_id_conversion(chip, chan_address, data);
0526         if (ret < 0) {
0527             dev_err(chip->dev, "Battery ID conversion failed:%d\n",
0528                 ret);
0529             goto unlock_out;
0530         }
0531         break;
0532 
0533     case RR_ADC_USBIN_V:
0534     case RR_ADC_DIE_TEMP:
0535         ret = rradc_read_status_in_cont_mode(chip, chan_address);
0536         if (ret < 0) {
0537             dev_err(chip->dev,
0538                 "Error reading in continuous mode:%d\n", ret);
0539             goto unlock_out;
0540         }
0541         break;
0542     default:
0543         if (!rradc_is_ready(chip, chan_address)) {
0544             /*
0545              * Usually this means the channel isn't attached, for example
0546              * the in_voltage_usbin_v_input channel will not be ready if
0547              * no USB cable is attached
0548              */
0549             dev_dbg(chip->dev, "channel '%s' is not ready\n",
0550                 iio_chan->extend_name);
0551             ret = -ENODATA;
0552             goto unlock_out;
0553         }
0554         break;
0555     }
0556 
0557     ret = rradc_read(chip, chan->lsb, buf, chan->size);
0558     if (ret) {
0559         dev_err(chip->dev, "read data failed\n");
0560         goto unlock_out;
0561     }
0562 
0563     /*
0564      * For the battery ID we read the register for every ID ADC and then
0565      * see which one is actually connected.
0566      */
0567     if (chan_address == RR_ADC_BATT_ID) {
0568         u16 batt_id_150 = le16_to_cpu(buf[2]);
0569         u16 batt_id_15 = le16_to_cpu(buf[1]);
0570         u16 batt_id_5 = le16_to_cpu(buf[0]);
0571 
0572         if (!batt_id_150 && !batt_id_15 && !batt_id_5) {
0573             dev_err(chip->dev,
0574                 "Invalid batt_id values with all zeros\n");
0575             ret = -EINVAL;
0576             goto unlock_out;
0577         }
0578 
0579         if (batt_id_150 <= RR_ADC_BATT_ID_RANGE) {
0580             *data = batt_id_150;
0581             chip->batt_id_data = 150;
0582         } else if (batt_id_15 <= RR_ADC_BATT_ID_RANGE) {
0583             *data = batt_id_15;
0584             chip->batt_id_data = 15;
0585         } else {
0586             *data = batt_id_5;
0587             chip->batt_id_data = 5;
0588         }
0589     } else {
0590         /*
0591          * All of the other channels are either 1 or 2 bytes.
0592          * We can rely on the second byte being 0 for 1-byte channels.
0593          */
0594         *data = le16_to_cpu(buf[0]);
0595     }
0596 
0597 unlock_out:
0598     mutex_unlock(&chip->conversion_lock);
0599 
0600     return ret;
0601 }
0602 
0603 static int rradc_read_scale(struct rradc_chip *chip, int chan_address, int *val,
0604                 int *val2)
0605 {
0606     int64_t fab_offset, fab_slope;
0607     int ret;
0608 
0609     ret = rradc_get_fab_coeff(chip, &fab_offset, &fab_slope);
0610     if (ret < 0) {
0611         dev_err(chip->dev, "Unable to get fab id coefficients\n");
0612         return -EINVAL;
0613     }
0614 
0615     switch (chan_address) {
0616     case RR_ADC_SKIN_TEMP:
0617         *val = MILLI;
0618         *val2 = RR_ADC_BATT_THERM_LSB_K;
0619         return IIO_VAL_FRACTIONAL;
0620     case RR_ADC_USBIN_I:
0621         *val = RR_ADC_CURR_USBIN_INPUT_FACTOR_MIL *
0622                RR_ADC_FS_VOLTAGE_MV;
0623         *val2 = RR_ADC_CHAN_MSB;
0624         return IIO_VAL_FRACTIONAL;
0625     case RR_ADC_DCIN_I:
0626         *val = RR_ADC_CURR_INPUT_FACTOR * RR_ADC_FS_VOLTAGE_MV;
0627         *val2 = RR_ADC_CHAN_MSB;
0628         return IIO_VAL_FRACTIONAL;
0629     case RR_ADC_USBIN_V:
0630     case RR_ADC_DCIN_V:
0631         *val = RR_ADC_VOLT_INPUT_FACTOR * RR_ADC_FS_VOLTAGE_MV * MILLI;
0632         *val2 = RR_ADC_CHAN_MSB;
0633         return IIO_VAL_FRACTIONAL;
0634     case RR_ADC_GPIO:
0635         *val = RR_ADC_GPIO_FS_RANGE;
0636         *val2 = RR_ADC_CHAN_MSB;
0637         return IIO_VAL_FRACTIONAL;
0638     case RR_ADC_CHG_TEMP:
0639         /*
0640          * We divide val2 by MILLI instead of multiplying val
0641          * to avoid an integer overflow.
0642          */
0643         *val = -RR_ADC_TEMP_FS_VOLTAGE_NUM;
0644         *val2 = div64_s64(RR_ADC_TEMP_FS_VOLTAGE_DEN * RR_ADC_CHAN_MSB *
0645                       fab_slope,
0646                   MILLI);
0647 
0648         return IIO_VAL_FRACTIONAL;
0649     case RR_ADC_DIE_TEMP:
0650         *val = RR_ADC_TEMP_FS_VOLTAGE_NUM;
0651         *val2 = RR_ADC_TEMP_FS_VOLTAGE_DEN * RR_ADC_CHAN_MSB *
0652             RR_ADC_DIE_TEMP_SLOPE;
0653 
0654         return IIO_VAL_FRACTIONAL;
0655     default:
0656         return -EINVAL;
0657     }
0658 }
0659 
0660 static int rradc_read_offset(struct rradc_chip *chip, int chan_address, int *val)
0661 {
0662     int64_t fab_offset, fab_slope;
0663     int64_t offset1, offset2;
0664     int ret;
0665 
0666     switch (chan_address) {
0667     case RR_ADC_SKIN_TEMP:
0668         /*
0669          * Offset from kelvin to degC, divided by the
0670          * scale factor (250). We lose some precision here.
0671          * 273150 / 250 = 1092.6
0672          */
0673         *val = div64_s64(ABSOLUTE_ZERO_MILLICELSIUS,
0674                  (MILLI / RR_ADC_BATT_THERM_LSB_K));
0675         return IIO_VAL_INT;
0676     case RR_ADC_CHG_TEMP:
0677         ret = rradc_get_fab_coeff(chip, &fab_offset, &fab_slope);
0678         if (ret < 0) {
0679             dev_err(chip->dev,
0680                 "Unable to get fab id coefficients\n");
0681             return -EINVAL;
0682         }
0683         offset1 = -(fab_offset * RR_ADC_TEMP_FS_VOLTAGE_DEN *
0684                 RR_ADC_CHAN_MSB);
0685         offset1 += (int64_t)RR_ADC_TEMP_FS_VOLTAGE_NUM / 2ULL;
0686         offset1 = div64_s64(offset1,
0687                     (int64_t)(RR_ADC_TEMP_FS_VOLTAGE_NUM));
0688 
0689         offset2 = (int64_t)RR_ADC_CHG_TEMP_OFFSET_MILLI_DEGC *
0690               RR_ADC_TEMP_FS_VOLTAGE_DEN * RR_ADC_CHAN_MSB *
0691               (int64_t)fab_slope;
0692         offset2 += ((int64_t)MILLI * RR_ADC_TEMP_FS_VOLTAGE_NUM) / 2;
0693         offset2 = div64_s64(
0694             offset2, ((int64_t)MILLI * RR_ADC_TEMP_FS_VOLTAGE_NUM));
0695 
0696         /*
0697          * The -1 is to compensate for lost precision.
0698          * It should actually be -0.7906976744186046.
0699          * This works out to every value being off
0700          * by about +0.091 degrees C after applying offset and scale.
0701          */
0702         *val = (int)(offset1 - offset2 - 1);
0703         return IIO_VAL_INT;
0704     case RR_ADC_DIE_TEMP:
0705         offset1 = -RR_ADC_DIE_TEMP_OFFSET *
0706               (int64_t)RR_ADC_TEMP_FS_VOLTAGE_DEN *
0707               (int64_t)RR_ADC_CHAN_MSB;
0708         offset1 = div64_s64(offset1, RR_ADC_TEMP_FS_VOLTAGE_NUM);
0709 
0710         offset2 = -(int64_t)RR_ADC_CHG_TEMP_OFFSET_MILLI_DEGC *
0711               RR_ADC_TEMP_FS_VOLTAGE_DEN * RR_ADC_CHAN_MSB *
0712               RR_ADC_DIE_TEMP_SLOPE;
0713         offset2 = div64_s64(offset2,
0714                     ((int64_t)RR_ADC_TEMP_FS_VOLTAGE_NUM));
0715 
0716         /*
0717          * The result is -339, it should be -338.69789, this results
0718          * in the calculated die temp being off by
0719          * -0.004 - -0.0175 degrees C
0720          */
0721         *val = (int)(offset1 - offset2);
0722         return IIO_VAL_INT;
0723     default:
0724         break;
0725     }
0726     return -EINVAL;
0727 }
0728 
0729 static int rradc_read_raw(struct iio_dev *indio_dev,
0730               struct iio_chan_spec const *chan_spec, int *val,
0731               int *val2, long mask)
0732 {
0733     struct rradc_chip *chip = iio_priv(indio_dev);
0734     const struct rradc_channel *chan;
0735     int ret;
0736     u16 adc_code;
0737 
0738     if (chan_spec->address >= RR_ADC_CHAN_MAX) {
0739         dev_err(chip->dev, "Invalid channel index:%lu\n",
0740             chan_spec->address);
0741         return -EINVAL;
0742     }
0743 
0744     switch (mask) {
0745     case IIO_CHAN_INFO_SCALE:
0746         return rradc_read_scale(chip, chan_spec->address, val, val2);
0747     case IIO_CHAN_INFO_OFFSET:
0748         return rradc_read_offset(chip, chan_spec->address, val);
0749     case IIO_CHAN_INFO_RAW:
0750         ret = rradc_do_conversion(chip, chan_spec->address, &adc_code);
0751         if (ret < 0)
0752             return ret;
0753 
0754         *val = adc_code;
0755         return IIO_VAL_INT;
0756     case IIO_CHAN_INFO_PROCESSED:
0757         chan = &rradc_chans[chan_spec->address];
0758         if (!chan->scale_fn)
0759             return -EINVAL;
0760         ret = rradc_do_conversion(chip, chan_spec->address, &adc_code);
0761         if (ret < 0)
0762             return ret;
0763 
0764         *val = chan->scale_fn(chip, adc_code, val);
0765         return IIO_VAL_INT;
0766     default:
0767         return -EINVAL;
0768     }
0769 }
0770 
0771 static int rradc_read_label(struct iio_dev *indio_dev,
0772                 struct iio_chan_spec const *chan, char *label)
0773 {
0774     return snprintf(label, PAGE_SIZE, "%s\n",
0775             rradc_chans[chan->address].label);
0776 }
0777 
0778 static const struct iio_info rradc_info = {
0779     .read_raw = rradc_read_raw,
0780     .read_label = rradc_read_label,
0781 };
0782 
0783 static const struct rradc_channel rradc_chans[RR_ADC_CHAN_MAX] = {
0784     {
0785         .label = "batt_id",
0786         .scale_fn = rradc_post_process_batt_id,
0787         .lsb = RR_ADC_BATT_ID_5_LSB,
0788         .status = RR_ADC_BATT_ID_STS,
0789         .size = 6,
0790         .trigger_addr = RR_ADC_BATT_ID_TRIGGER,
0791         .trigger_mask = BIT(0),
0792     }, {
0793         .label = "batt",
0794         .lsb = RR_ADC_BATT_THERM_LSB,
0795         .status = RR_ADC_BATT_THERM_STS,
0796         .size = 2,
0797         .trigger_addr = RR_ADC_BATT_THERM_TRIGGER,
0798     }, {
0799         .label = "pmi8998_skin",
0800         .lsb = RR_ADC_SKIN_TEMP_LSB,
0801         .status = RR_ADC_AUX_THERM_STS,
0802         .size = 2,
0803         .trigger_addr = RR_ADC_AUX_THERM_TRIGGER,
0804     }, {
0805         .label = "usbin_i",
0806         .lsb = RR_ADC_USB_IN_I_LSB,
0807         .status = RR_ADC_USB_IN_I_STS,
0808         .size = 2,
0809         .trigger_addr = RR_ADC_USB_IN_I_TRIGGER,
0810     }, {
0811         .label = "usbin_v",
0812         .lsb = RR_ADC_USB_IN_V_LSB,
0813         .status = RR_ADC_USB_IN_V_STS,
0814         .size = 2,
0815         .trigger_addr = RR_ADC_USB_IN_V_TRIGGER,
0816         .trigger_mask = BIT(7),
0817     }, {
0818         .label = "dcin_i",
0819         .lsb = RR_ADC_DC_IN_I_LSB,
0820         .status = RR_ADC_DC_IN_I_STS,
0821         .size = 2,
0822         .trigger_addr = RR_ADC_DC_IN_I_TRIGGER,
0823     }, {
0824         .label = "dcin_v",
0825         .lsb = RR_ADC_DC_IN_V_LSB,
0826         .status = RR_ADC_DC_IN_V_STS,
0827         .size = 2,
0828         .trigger_addr = RR_ADC_DC_IN_V_TRIGGER,
0829     }, {
0830         .label = "pmi8998_die",
0831         .lsb = RR_ADC_PMI_DIE_TEMP_LSB,
0832         .status = RR_ADC_PMI_DIE_TEMP_STS,
0833         .size = 2,
0834         .trigger_addr = RR_ADC_PMI_DIE_TEMP_TRIGGER,
0835         .trigger_mask = RR_ADC_TRIGGER_EVERY_CYCLE,
0836     }, {
0837         .label = "chg",
0838         .lsb = RR_ADC_CHARGER_TEMP_LSB,
0839         .status = RR_ADC_CHARGER_TEMP_STS,
0840         .size = 2,
0841         .trigger_addr = RR_ADC_CHARGER_TEMP_TRIGGER,
0842     }, {
0843         .label = "gpio",
0844         .lsb = RR_ADC_GPIO_LSB,
0845         .status = RR_ADC_GPIO_STS,
0846         .size = 2,
0847         .trigger_addr = RR_ADC_GPIO_TRIGGER,
0848     },
0849 };
0850 
0851 static const struct iio_chan_spec rradc_iio_chans[RR_ADC_CHAN_MAX] = {
0852     {
0853         .type = IIO_RESISTANCE,
0854         .info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
0855         .address = RR_ADC_BATT_ID,
0856         .channel = 0,
0857         .indexed = 1,
0858     }, {
0859         .type = IIO_TEMP,
0860         .info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
0861         .address = RR_ADC_BATT_THERM,
0862         .channel = 0,
0863         .indexed = 1,
0864     }, {
0865         .type = IIO_TEMP,
0866         .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
0867                       BIT(IIO_CHAN_INFO_SCALE) |
0868                       BIT(IIO_CHAN_INFO_OFFSET),
0869         .address = RR_ADC_SKIN_TEMP,
0870         .channel = 1,
0871         .indexed = 1,
0872     }, {
0873         .type = IIO_CURRENT,
0874         .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
0875                       BIT(IIO_CHAN_INFO_SCALE),
0876         .address = RR_ADC_USBIN_I,
0877         .channel = 0,
0878         .indexed = 1,
0879     }, {
0880         .type = IIO_VOLTAGE,
0881         .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
0882                       BIT(IIO_CHAN_INFO_SCALE),
0883         .address = RR_ADC_USBIN_V,
0884         .channel = 0,
0885         .indexed = 1,
0886     }, {
0887         .type = IIO_CURRENT,
0888         .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
0889                       BIT(IIO_CHAN_INFO_SCALE),
0890         .address = RR_ADC_DCIN_I,
0891         .channel = 1,
0892         .indexed = 1,
0893     }, {
0894         .type = IIO_VOLTAGE,
0895         .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
0896                       BIT(IIO_CHAN_INFO_SCALE),
0897         .address = RR_ADC_DCIN_V,
0898         .channel = 1,
0899         .indexed = 1,
0900     }, {
0901         .type = IIO_TEMP,
0902         .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
0903                       BIT(IIO_CHAN_INFO_SCALE) |
0904                       BIT(IIO_CHAN_INFO_OFFSET),
0905         .address = RR_ADC_DIE_TEMP,
0906         .channel = 2,
0907         .indexed = 1,
0908     }, {
0909         .type = IIO_TEMP,
0910         .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
0911                       BIT(IIO_CHAN_INFO_OFFSET) |
0912                       BIT(IIO_CHAN_INFO_SCALE),
0913         .address = RR_ADC_CHG_TEMP,
0914         .channel = 3,
0915         .indexed = 1,
0916     }, {
0917         .type = IIO_VOLTAGE,
0918         .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED) |
0919                       BIT(IIO_CHAN_INFO_SCALE),
0920         .address = RR_ADC_GPIO,
0921         .channel = 2,
0922         .indexed = 1,
0923     },
0924 };
0925 
0926 static int rradc_probe(struct platform_device *pdev)
0927 {
0928     struct device *dev = &pdev->dev;
0929     struct iio_dev *indio_dev;
0930     struct rradc_chip *chip;
0931     int ret, i, batt_id_delay;
0932 
0933     indio_dev = devm_iio_device_alloc(dev, sizeof(*chip));
0934     if (!indio_dev)
0935         return -ENOMEM;
0936 
0937     chip = iio_priv(indio_dev);
0938     chip->regmap = dev_get_regmap(pdev->dev.parent, NULL);
0939     if (!chip->regmap) {
0940         dev_err(dev, "Couldn't get parent's regmap\n");
0941         return -EINVAL;
0942     }
0943 
0944     chip->dev = dev;
0945     mutex_init(&chip->conversion_lock);
0946 
0947     ret = device_property_read_u32(dev, "reg", &chip->base);
0948     if (ret < 0) {
0949         dev_err(chip->dev, "Couldn't find reg address, ret = %d\n",
0950             ret);
0951         return ret;
0952     }
0953 
0954     batt_id_delay = -1;
0955     ret = device_property_read_u32(dev, "qcom,batt-id-delay-ms",
0956                        &batt_id_delay);
0957     if (!ret) {
0958         for (i = 0; i < RRADC_BATT_ID_DELAY_MAX; i++) {
0959             if (batt_id_delay == batt_id_delays[i])
0960                 break;
0961         }
0962         if (i == RRADC_BATT_ID_DELAY_MAX)
0963             batt_id_delay = -1;
0964     }
0965 
0966     if (batt_id_delay >= 0) {
0967         batt_id_delay = FIELD_PREP(BATT_ID_SETTLE_MASK, batt_id_delay);
0968         ret = regmap_update_bits(chip->regmap,
0969                      chip->base + RR_ADC_BATT_ID_CFG,
0970                      batt_id_delay, batt_id_delay);
0971         if (ret < 0) {
0972             dev_err(chip->dev,
0973                 "BATT_ID settling time config failed:%d\n",
0974                 ret);
0975         }
0976     }
0977 
0978     /* Get the PMIC revision, we need it to handle some varying coefficients */
0979     chip->pmic = qcom_pmic_get(chip->dev);
0980     if (IS_ERR(chip->pmic)) {
0981         dev_err(chip->dev, "Unable to get reference to PMIC device\n");
0982         return PTR_ERR(chip->pmic);
0983     }
0984 
0985     switch (chip->pmic->subtype) {
0986     case PMI8998_SUBTYPE:
0987         indio_dev->name = "pmi8998-rradc";
0988         break;
0989     case PM660_SUBTYPE:
0990         indio_dev->name = "pm660-rradc";
0991         break;
0992     default:
0993         indio_dev->name = DRIVER_NAME;
0994         break;
0995     }
0996     indio_dev->modes = INDIO_DIRECT_MODE;
0997     indio_dev->info = &rradc_info;
0998     indio_dev->channels = rradc_iio_chans;
0999     indio_dev->num_channels = ARRAY_SIZE(rradc_iio_chans);
1000 
1001     return devm_iio_device_register(dev, indio_dev);
1002 }
1003 
1004 static const struct of_device_id rradc_match_table[] = {
1005     { .compatible = "qcom,pm660-rradc" },
1006     { .compatible = "qcom,pmi8998-rradc" },
1007     {}
1008 };
1009 MODULE_DEVICE_TABLE(of, rradc_match_table);
1010 
1011 static struct platform_driver rradc_driver = {
1012     .driver     = {
1013         .name       = DRIVER_NAME,
1014         .of_match_table = rradc_match_table,
1015     },
1016     .probe = rradc_probe,
1017 };
1018 module_platform_driver(rradc_driver);
1019 
1020 MODULE_DESCRIPTION("QCOM SPMI PMIC RR ADC driver");
1021 MODULE_AUTHOR("Caleb Connolly <caleb.connolly@linaro.org>");
1022 MODULE_LICENSE("GPL");
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