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0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Copyright (c) 2018, 2020, The Linux Foundation. All rights reserved.
0004  */
0005 
0006 #include <linux/bitops.h>
0007 #include <linux/completion.h>
0008 #include <linux/delay.h>
0009 #include <linux/err.h>
0010 #include <linux/iio/adc/qcom-vadc-common.h>
0011 #include <linux/iio/iio.h>
0012 #include <linux/interrupt.h>
0013 #include <linux/kernel.h>
0014 #include <linux/log2.h>
0015 #include <linux/math64.h>
0016 #include <linux/module.h>
0017 #include <linux/of.h>
0018 #include <linux/of_device.h>
0019 #include <linux/platform_device.h>
0020 #include <linux/regmap.h>
0021 #include <linux/slab.h>
0022 
0023 #include <dt-bindings/iio/qcom,spmi-vadc.h>
0024 
0025 #define ADC5_USR_REVISION1          0x0
0026 #define ADC5_USR_STATUS1            0x8
0027 #define ADC5_USR_STATUS1_CONV_FAULT     BIT(7)
0028 #define ADC5_USR_STATUS1_REQ_STS        BIT(1)
0029 #define ADC5_USR_STATUS1_EOC            BIT(0)
0030 #define ADC5_USR_STATUS1_REQ_STS_EOC_MASK   0x3
0031 
0032 #define ADC5_USR_STATUS2            0x9
0033 #define ADC5_USR_STATUS2_CONV_SEQ_MASK      0x70
0034 #define ADC5_USR_STATUS2_CONV_SEQ_MASK_SHIFT    0x5
0035 
0036 #define ADC5_USR_IBAT_MEAS          0xf
0037 #define ADC5_USR_IBAT_MEAS_SUPPORTED        BIT(0)
0038 
0039 #define ADC5_USR_DIG_PARAM          0x42
0040 #define ADC5_USR_DIG_PARAM_CAL_VAL      BIT(6)
0041 #define ADC5_USR_DIG_PARAM_CAL_VAL_SHIFT    6
0042 #define ADC5_USR_DIG_PARAM_CAL_SEL      0x30
0043 #define ADC5_USR_DIG_PARAM_CAL_SEL_SHIFT    4
0044 #define ADC5_USR_DIG_PARAM_DEC_RATIO_SEL    0xc
0045 #define ADC5_USR_DIG_PARAM_DEC_RATIO_SEL_SHIFT  2
0046 
0047 #define ADC5_USR_FAST_AVG_CTL           0x43
0048 #define ADC5_USR_FAST_AVG_CTL_EN        BIT(7)
0049 #define ADC5_USR_FAST_AVG_CTL_SAMPLES_MASK  0x7
0050 
0051 #define ADC5_USR_CH_SEL_CTL         0x44
0052 
0053 #define ADC5_USR_DELAY_CTL          0x45
0054 #define ADC5_USR_HW_SETTLE_DELAY_MASK       0xf
0055 
0056 #define ADC5_USR_EN_CTL1            0x46
0057 #define ADC5_USR_EN_CTL1_ADC_EN         BIT(7)
0058 
0059 #define ADC5_USR_CONV_REQ           0x47
0060 #define ADC5_USR_CONV_REQ_REQ           BIT(7)
0061 
0062 #define ADC5_USR_DATA0              0x50
0063 
0064 #define ADC5_USR_DATA1              0x51
0065 
0066 #define ADC5_USR_IBAT_DATA0         0x52
0067 
0068 #define ADC5_USR_IBAT_DATA1         0x53
0069 
0070 #define ADC_CHANNEL_OFFSET          0x8
0071 #define ADC_CHANNEL_MASK            GENMASK(7, 0)
0072 
0073 /*
0074  * Conversion time varies based on the decimation, clock rate, fast average
0075  * samples and measurements queued across different VADC peripherals.
0076  * Set the timeout to a max of 100ms.
0077  */
0078 #define ADC5_CONV_TIME_MIN_US           263
0079 #define ADC5_CONV_TIME_MAX_US           264
0080 #define ADC5_CONV_TIME_RETRY            400
0081 #define ADC5_CONV_TIMEOUT           msecs_to_jiffies(100)
0082 
0083 /* Digital version >= 5.3 supports hw_settle_2 */
0084 #define ADC5_HW_SETTLE_DIFF_MINOR       3
0085 #define ADC5_HW_SETTLE_DIFF_MAJOR       5
0086 
0087 /* For PMIC7 */
0088 #define ADC_APP_SID             0x40
0089 #define ADC_APP_SID_MASK            GENMASK(3, 0)
0090 #define ADC7_CONV_TIMEOUT           msecs_to_jiffies(10)
0091 
0092 enum adc5_cal_method {
0093     ADC5_NO_CAL = 0,
0094     ADC5_RATIOMETRIC_CAL,
0095     ADC5_ABSOLUTE_CAL
0096 };
0097 
0098 enum adc5_cal_val {
0099     ADC5_TIMER_CAL = 0,
0100     ADC5_NEW_CAL
0101 };
0102 
0103 /**
0104  * struct adc5_channel_prop - ADC channel property.
0105  * @channel: channel number, refer to the channel list.
0106  * @cal_method: calibration method.
0107  * @cal_val: calibration value
0108  * @decimation: sampling rate supported for the channel.
0109  * @sid: slave id of PMIC owning the channel, for PMIC7.
0110  * @prescale: channel scaling performed on the input signal.
0111  * @hw_settle_time: the time between AMUX being configured and the
0112  *  start of conversion.
0113  * @avg_samples: ability to provide single result from the ADC
0114  *  that is an average of multiple measurements.
0115  * @scale_fn_type: Represents the scaling function to convert voltage
0116  *  physical units desired by the client for the channel.
0117  * @datasheet_name: Channel name used in device tree.
0118  */
0119 struct adc5_channel_prop {
0120     unsigned int        channel;
0121     enum adc5_cal_method    cal_method;
0122     enum adc5_cal_val   cal_val;
0123     unsigned int        decimation;
0124     unsigned int        sid;
0125     unsigned int        prescale;
0126     unsigned int        hw_settle_time;
0127     unsigned int        avg_samples;
0128     enum vadc_scale_fn_type scale_fn_type;
0129     const char      *datasheet_name;
0130 };
0131 
0132 /**
0133  * struct adc5_chip - ADC private structure.
0134  * @regmap: SPMI ADC5 peripheral register map field.
0135  * @dev: SPMI ADC5 device.
0136  * @base: base address for the ADC peripheral.
0137  * @nchannels: number of ADC channels.
0138  * @chan_props: array of ADC channel properties.
0139  * @iio_chans: array of IIO channels specification.
0140  * @poll_eoc: use polling instead of interrupt.
0141  * @complete: ADC result notification after interrupt is received.
0142  * @lock: ADC lock for access to the peripheral.
0143  * @data: software configuration data.
0144  */
0145 struct adc5_chip {
0146     struct regmap       *regmap;
0147     struct device       *dev;
0148     u16         base;
0149     unsigned int        nchannels;
0150     struct adc5_channel_prop    *chan_props;
0151     struct iio_chan_spec    *iio_chans;
0152     bool            poll_eoc;
0153     struct completion   complete;
0154     struct mutex        lock;
0155     const struct adc5_data  *data;
0156 };
0157 
0158 static int adc5_read(struct adc5_chip *adc, u16 offset, u8 *data, int len)
0159 {
0160     return regmap_bulk_read(adc->regmap, adc->base + offset, data, len);
0161 }
0162 
0163 static int adc5_write(struct adc5_chip *adc, u16 offset, u8 *data, int len)
0164 {
0165     return regmap_bulk_write(adc->regmap, adc->base + offset, data, len);
0166 }
0167 
0168 static int adc5_masked_write(struct adc5_chip *adc, u16 offset, u8 mask, u8 val)
0169 {
0170     return regmap_update_bits(adc->regmap, adc->base + offset, mask, val);
0171 }
0172 
0173 static int adc5_read_voltage_data(struct adc5_chip *adc, u16 *data)
0174 {
0175     int ret;
0176     u8 rslt_lsb, rslt_msb;
0177 
0178     ret = adc5_read(adc, ADC5_USR_DATA0, &rslt_lsb, sizeof(rslt_lsb));
0179     if (ret)
0180         return ret;
0181 
0182     ret = adc5_read(adc, ADC5_USR_DATA1, &rslt_msb, sizeof(rslt_lsb));
0183     if (ret)
0184         return ret;
0185 
0186     *data = (rslt_msb << 8) | rslt_lsb;
0187 
0188     if (*data == ADC5_USR_DATA_CHECK) {
0189         dev_err(adc->dev, "Invalid data:0x%x\n", *data);
0190         return -EINVAL;
0191     }
0192 
0193     dev_dbg(adc->dev, "voltage raw code:0x%x\n", *data);
0194 
0195     return 0;
0196 }
0197 
0198 static int adc5_poll_wait_eoc(struct adc5_chip *adc)
0199 {
0200     unsigned int count, retry = ADC5_CONV_TIME_RETRY;
0201     u8 status1;
0202     int ret;
0203 
0204     for (count = 0; count < retry; count++) {
0205         ret = adc5_read(adc, ADC5_USR_STATUS1, &status1,
0206                             sizeof(status1));
0207         if (ret)
0208             return ret;
0209 
0210         status1 &= ADC5_USR_STATUS1_REQ_STS_EOC_MASK;
0211         if (status1 == ADC5_USR_STATUS1_EOC)
0212             return 0;
0213 
0214         usleep_range(ADC5_CONV_TIME_MIN_US, ADC5_CONV_TIME_MAX_US);
0215     }
0216 
0217     return -ETIMEDOUT;
0218 }
0219 
0220 static void adc5_update_dig_param(struct adc5_chip *adc,
0221             struct adc5_channel_prop *prop, u8 *data)
0222 {
0223     /* Update calibration value */
0224     *data &= ~ADC5_USR_DIG_PARAM_CAL_VAL;
0225     *data |= (prop->cal_val << ADC5_USR_DIG_PARAM_CAL_VAL_SHIFT);
0226 
0227     /* Update calibration select */
0228     *data &= ~ADC5_USR_DIG_PARAM_CAL_SEL;
0229     *data |= (prop->cal_method << ADC5_USR_DIG_PARAM_CAL_SEL_SHIFT);
0230 
0231     /* Update decimation ratio select */
0232     *data &= ~ADC5_USR_DIG_PARAM_DEC_RATIO_SEL;
0233     *data |= (prop->decimation << ADC5_USR_DIG_PARAM_DEC_RATIO_SEL_SHIFT);
0234 }
0235 
0236 static int adc5_configure(struct adc5_chip *adc,
0237             struct adc5_channel_prop *prop)
0238 {
0239     int ret;
0240     u8 buf[6];
0241 
0242     /* Read registers 0x42 through 0x46 */
0243     ret = adc5_read(adc, ADC5_USR_DIG_PARAM, buf, sizeof(buf));
0244     if (ret)
0245         return ret;
0246 
0247     /* Digital param selection */
0248     adc5_update_dig_param(adc, prop, &buf[0]);
0249 
0250     /* Update fast average sample value */
0251     buf[1] &= (u8) ~ADC5_USR_FAST_AVG_CTL_SAMPLES_MASK;
0252     buf[1] |= prop->avg_samples;
0253 
0254     /* Select ADC channel */
0255     buf[2] = prop->channel;
0256 
0257     /* Select HW settle delay for channel */
0258     buf[3] &= (u8) ~ADC5_USR_HW_SETTLE_DELAY_MASK;
0259     buf[3] |= prop->hw_settle_time;
0260 
0261     /* Select ADC enable */
0262     buf[4] |= ADC5_USR_EN_CTL1_ADC_EN;
0263 
0264     /* Select CONV request */
0265     buf[5] |= ADC5_USR_CONV_REQ_REQ;
0266 
0267     if (!adc->poll_eoc)
0268         reinit_completion(&adc->complete);
0269 
0270     return adc5_write(adc, ADC5_USR_DIG_PARAM, buf, sizeof(buf));
0271 }
0272 
0273 static int adc7_configure(struct adc5_chip *adc,
0274             struct adc5_channel_prop *prop)
0275 {
0276     int ret;
0277     u8 conv_req = 0, buf[4];
0278 
0279     ret = adc5_masked_write(adc, ADC_APP_SID, ADC_APP_SID_MASK, prop->sid);
0280     if (ret)
0281         return ret;
0282 
0283     ret = adc5_read(adc, ADC5_USR_DIG_PARAM, buf, sizeof(buf));
0284     if (ret)
0285         return ret;
0286 
0287     /* Digital param selection */
0288     adc5_update_dig_param(adc, prop, &buf[0]);
0289 
0290     /* Update fast average sample value */
0291     buf[1] &= ~ADC5_USR_FAST_AVG_CTL_SAMPLES_MASK;
0292     buf[1] |= prop->avg_samples;
0293 
0294     /* Select ADC channel */
0295     buf[2] = prop->channel;
0296 
0297     /* Select HW settle delay for channel */
0298     buf[3] &= ~ADC5_USR_HW_SETTLE_DELAY_MASK;
0299     buf[3] |= prop->hw_settle_time;
0300 
0301     /* Select CONV request */
0302     conv_req = ADC5_USR_CONV_REQ_REQ;
0303 
0304     if (!adc->poll_eoc)
0305         reinit_completion(&adc->complete);
0306 
0307     ret = adc5_write(adc, ADC5_USR_DIG_PARAM, buf, sizeof(buf));
0308     if (ret)
0309         return ret;
0310 
0311     return adc5_write(adc, ADC5_USR_CONV_REQ, &conv_req, 1);
0312 }
0313 
0314 static int adc5_do_conversion(struct adc5_chip *adc,
0315             struct adc5_channel_prop *prop,
0316             struct iio_chan_spec const *chan,
0317             u16 *data_volt, u16 *data_cur)
0318 {
0319     int ret;
0320 
0321     mutex_lock(&adc->lock);
0322 
0323     ret = adc5_configure(adc, prop);
0324     if (ret) {
0325         dev_err(adc->dev, "ADC configure failed with %d\n", ret);
0326         goto unlock;
0327     }
0328 
0329     if (adc->poll_eoc) {
0330         ret = adc5_poll_wait_eoc(adc);
0331         if (ret) {
0332             dev_err(adc->dev, "EOC bit not set\n");
0333             goto unlock;
0334         }
0335     } else {
0336         ret = wait_for_completion_timeout(&adc->complete,
0337                             ADC5_CONV_TIMEOUT);
0338         if (!ret) {
0339             dev_dbg(adc->dev, "Did not get completion timeout.\n");
0340             ret = adc5_poll_wait_eoc(adc);
0341             if (ret) {
0342                 dev_err(adc->dev, "EOC bit not set\n");
0343                 goto unlock;
0344             }
0345         }
0346     }
0347 
0348     ret = adc5_read_voltage_data(adc, data_volt);
0349 unlock:
0350     mutex_unlock(&adc->lock);
0351 
0352     return ret;
0353 }
0354 
0355 static int adc7_do_conversion(struct adc5_chip *adc,
0356             struct adc5_channel_prop *prop,
0357             struct iio_chan_spec const *chan,
0358             u16 *data_volt, u16 *data_cur)
0359 {
0360     int ret;
0361     u8 status;
0362 
0363     mutex_lock(&adc->lock);
0364 
0365     ret = adc7_configure(adc, prop);
0366     if (ret) {
0367         dev_err(adc->dev, "ADC configure failed with %d\n", ret);
0368         goto unlock;
0369     }
0370 
0371     /* No support for polling mode at present */
0372     wait_for_completion_timeout(&adc->complete, ADC7_CONV_TIMEOUT);
0373 
0374     ret = adc5_read(adc, ADC5_USR_STATUS1, &status, 1);
0375     if (ret)
0376         goto unlock;
0377 
0378     if (status & ADC5_USR_STATUS1_CONV_FAULT) {
0379         dev_err(adc->dev, "Unexpected conversion fault\n");
0380         ret = -EIO;
0381         goto unlock;
0382     }
0383 
0384     ret = adc5_read_voltage_data(adc, data_volt);
0385 
0386 unlock:
0387     mutex_unlock(&adc->lock);
0388 
0389     return ret;
0390 }
0391 
0392 typedef int (*adc_do_conversion)(struct adc5_chip *adc,
0393             struct adc5_channel_prop *prop,
0394             struct iio_chan_spec const *chan,
0395             u16 *data_volt, u16 *data_cur);
0396 
0397 static irqreturn_t adc5_isr(int irq, void *dev_id)
0398 {
0399     struct adc5_chip *adc = dev_id;
0400 
0401     complete(&adc->complete);
0402 
0403     return IRQ_HANDLED;
0404 }
0405 
0406 static int adc5_of_xlate(struct iio_dev *indio_dev,
0407                 const struct of_phandle_args *iiospec)
0408 {
0409     struct adc5_chip *adc = iio_priv(indio_dev);
0410     int i;
0411 
0412     for (i = 0; i < adc->nchannels; i++)
0413         if (adc->chan_props[i].channel == iiospec->args[0])
0414             return i;
0415 
0416     return -EINVAL;
0417 }
0418 
0419 static int adc7_of_xlate(struct iio_dev *indio_dev,
0420                 const struct of_phandle_args *iiospec)
0421 {
0422     struct adc5_chip *adc = iio_priv(indio_dev);
0423     int i, v_channel;
0424 
0425     for (i = 0; i < adc->nchannels; i++) {
0426         v_channel = (adc->chan_props[i].sid << ADC_CHANNEL_OFFSET) |
0427             adc->chan_props[i].channel;
0428         if (v_channel == iiospec->args[0])
0429             return i;
0430     }
0431 
0432     return -EINVAL;
0433 }
0434 
0435 static int adc_read_raw_common(struct iio_dev *indio_dev,
0436              struct iio_chan_spec const *chan, int *val, int *val2,
0437              long mask, adc_do_conversion do_conv)
0438 {
0439     struct adc5_chip *adc = iio_priv(indio_dev);
0440     struct adc5_channel_prop *prop;
0441     u16 adc_code_volt, adc_code_cur;
0442     int ret;
0443 
0444     prop = &adc->chan_props[chan->address];
0445 
0446     switch (mask) {
0447     case IIO_CHAN_INFO_PROCESSED:
0448         ret = do_conv(adc, prop, chan,
0449                     &adc_code_volt, &adc_code_cur);
0450         if (ret)
0451             return ret;
0452 
0453         ret = qcom_adc5_hw_scale(prop->scale_fn_type,
0454             prop->prescale,
0455             adc->data,
0456             adc_code_volt, val);
0457         if (ret)
0458             return ret;
0459 
0460         return IIO_VAL_INT;
0461     default:
0462         return -EINVAL;
0463     }
0464 }
0465 
0466 static int adc5_read_raw(struct iio_dev *indio_dev,
0467              struct iio_chan_spec const *chan, int *val, int *val2,
0468              long mask)
0469 {
0470     return adc_read_raw_common(indio_dev, chan, val, val2,
0471                 mask, adc5_do_conversion);
0472 }
0473 
0474 static int adc7_read_raw(struct iio_dev *indio_dev,
0475              struct iio_chan_spec const *chan, int *val, int *val2,
0476              long mask)
0477 {
0478     return adc_read_raw_common(indio_dev, chan, val, val2,
0479                 mask, adc7_do_conversion);
0480 }
0481 
0482 static const struct iio_info adc5_info = {
0483     .read_raw = adc5_read_raw,
0484     .of_xlate = adc5_of_xlate,
0485 };
0486 
0487 static const struct iio_info adc7_info = {
0488     .read_raw = adc7_read_raw,
0489     .of_xlate = adc7_of_xlate,
0490 };
0491 
0492 struct adc5_channels {
0493     const char *datasheet_name;
0494     unsigned int prescale_index;
0495     enum iio_chan_type type;
0496     long info_mask;
0497     enum vadc_scale_fn_type scale_fn_type;
0498 };
0499 
0500 /* In these definitions, _pre refers to an index into adc5_prescale_ratios. */
0501 #define ADC5_CHAN(_dname, _type, _mask, _pre, _scale)           \
0502     {                               \
0503         .datasheet_name = _dname,               \
0504         .prescale_index = _pre,                 \
0505         .type = _type,                      \
0506         .info_mask = _mask,                 \
0507         .scale_fn_type = _scale,                \
0508     },                              \
0509 
0510 #define ADC5_CHAN_TEMP(_dname, _pre, _scale)                \
0511     ADC5_CHAN(_dname, IIO_TEMP,                 \
0512         BIT(IIO_CHAN_INFO_PROCESSED),               \
0513         _pre, _scale)                       \
0514 
0515 #define ADC5_CHAN_VOLT(_dname, _pre, _scale)                \
0516     ADC5_CHAN(_dname, IIO_VOLTAGE,                  \
0517           BIT(IIO_CHAN_INFO_PROCESSED),             \
0518           _pre, _scale)                     \
0519 
0520 static const struct adc5_channels adc5_chans_pmic[ADC5_MAX_CHANNEL] = {
0521     [ADC5_REF_GND]      = ADC5_CHAN_VOLT("ref_gnd", 0,
0522                     SCALE_HW_CALIB_DEFAULT)
0523     [ADC5_1P25VREF]     = ADC5_CHAN_VOLT("vref_1p25", 0,
0524                     SCALE_HW_CALIB_DEFAULT)
0525     [ADC5_VPH_PWR]      = ADC5_CHAN_VOLT("vph_pwr", 1,
0526                     SCALE_HW_CALIB_DEFAULT)
0527     [ADC5_VBAT_SNS]     = ADC5_CHAN_VOLT("vbat_sns", 1,
0528                     SCALE_HW_CALIB_DEFAULT)
0529     [ADC5_DIE_TEMP]     = ADC5_CHAN_TEMP("die_temp", 0,
0530                     SCALE_HW_CALIB_PMIC_THERM)
0531     [ADC5_USB_IN_I]     = ADC5_CHAN_VOLT("usb_in_i_uv", 0,
0532                     SCALE_HW_CALIB_DEFAULT)
0533     [ADC5_USB_IN_V_16]  = ADC5_CHAN_VOLT("usb_in_v_div_16", 8,
0534                     SCALE_HW_CALIB_DEFAULT)
0535     [ADC5_CHG_TEMP]     = ADC5_CHAN_TEMP("chg_temp", 0,
0536                     SCALE_HW_CALIB_PM5_CHG_TEMP)
0537     /* Charger prescales SBUx and MID_CHG to fit within 1.8V upper unit */
0538     [ADC5_SBUx]     = ADC5_CHAN_VOLT("chg_sbux", 1,
0539                     SCALE_HW_CALIB_DEFAULT)
0540     [ADC5_MID_CHG_DIV6] = ADC5_CHAN_VOLT("chg_mid_chg", 3,
0541                     SCALE_HW_CALIB_DEFAULT)
0542     [ADC5_XO_THERM_100K_PU] = ADC5_CHAN_TEMP("xo_therm", 0,
0543                     SCALE_HW_CALIB_XOTHERM)
0544     [ADC5_AMUX_THM1_100K_PU] = ADC5_CHAN_TEMP("amux_thm1_100k_pu", 0,
0545                     SCALE_HW_CALIB_THERM_100K_PULLUP)
0546     [ADC5_AMUX_THM2_100K_PU] = ADC5_CHAN_TEMP("amux_thm2_100k_pu", 0,
0547                     SCALE_HW_CALIB_THERM_100K_PULLUP)
0548     [ADC5_AMUX_THM3_100K_PU] = ADC5_CHAN_TEMP("amux_thm3_100k_pu", 0,
0549                     SCALE_HW_CALIB_THERM_100K_PULLUP)
0550     [ADC5_AMUX_THM2]    = ADC5_CHAN_TEMP("amux_thm2", 0,
0551                     SCALE_HW_CALIB_PM5_SMB_TEMP)
0552 };
0553 
0554 static const struct adc5_channels adc7_chans_pmic[ADC5_MAX_CHANNEL] = {
0555     [ADC7_REF_GND]      = ADC5_CHAN_VOLT("ref_gnd", 0,
0556                     SCALE_HW_CALIB_DEFAULT)
0557     [ADC7_1P25VREF]     = ADC5_CHAN_VOLT("vref_1p25", 0,
0558                     SCALE_HW_CALIB_DEFAULT)
0559     [ADC7_VPH_PWR]      = ADC5_CHAN_VOLT("vph_pwr", 1,
0560                     SCALE_HW_CALIB_DEFAULT)
0561     [ADC7_VBAT_SNS]     = ADC5_CHAN_VOLT("vbat_sns", 3,
0562                     SCALE_HW_CALIB_DEFAULT)
0563     [ADC7_DIE_TEMP]     = ADC5_CHAN_TEMP("die_temp", 0,
0564                     SCALE_HW_CALIB_PMIC_THERM_PM7)
0565     [ADC7_AMUX_THM1_100K_PU] = ADC5_CHAN_TEMP("amux_thm1_pu2", 0,
0566                     SCALE_HW_CALIB_THERM_100K_PU_PM7)
0567     [ADC7_AMUX_THM2_100K_PU] = ADC5_CHAN_TEMP("amux_thm2_pu2", 0,
0568                     SCALE_HW_CALIB_THERM_100K_PU_PM7)
0569     [ADC7_AMUX_THM3_100K_PU] = ADC5_CHAN_TEMP("amux_thm3_pu2", 0,
0570                     SCALE_HW_CALIB_THERM_100K_PU_PM7)
0571     [ADC7_AMUX_THM4_100K_PU] = ADC5_CHAN_TEMP("amux_thm4_pu2", 0,
0572                     SCALE_HW_CALIB_THERM_100K_PU_PM7)
0573     [ADC7_AMUX_THM5_100K_PU] = ADC5_CHAN_TEMP("amux_thm5_pu2", 0,
0574                     SCALE_HW_CALIB_THERM_100K_PU_PM7)
0575     [ADC7_AMUX_THM6_100K_PU] = ADC5_CHAN_TEMP("amux_thm6_pu2", 0,
0576                     SCALE_HW_CALIB_THERM_100K_PU_PM7)
0577     [ADC7_GPIO1_100K_PU]    = ADC5_CHAN_TEMP("gpio1_pu2", 0,
0578                     SCALE_HW_CALIB_THERM_100K_PU_PM7)
0579     [ADC7_GPIO2_100K_PU]    = ADC5_CHAN_TEMP("gpio2_pu2", 0,
0580                     SCALE_HW_CALIB_THERM_100K_PU_PM7)
0581     [ADC7_GPIO3_100K_PU]    = ADC5_CHAN_TEMP("gpio3_pu2", 0,
0582                     SCALE_HW_CALIB_THERM_100K_PU_PM7)
0583     [ADC7_GPIO4_100K_PU]    = ADC5_CHAN_TEMP("gpio4_pu2", 0,
0584                     SCALE_HW_CALIB_THERM_100K_PU_PM7)
0585 };
0586 
0587 static const struct adc5_channels adc5_chans_rev2[ADC5_MAX_CHANNEL] = {
0588     [ADC5_REF_GND]      = ADC5_CHAN_VOLT("ref_gnd", 0,
0589                     SCALE_HW_CALIB_DEFAULT)
0590     [ADC5_1P25VREF]     = ADC5_CHAN_VOLT("vref_1p25", 0,
0591                     SCALE_HW_CALIB_DEFAULT)
0592     [ADC5_VPH_PWR]      = ADC5_CHAN_VOLT("vph_pwr", 1,
0593                     SCALE_HW_CALIB_DEFAULT)
0594     [ADC5_VBAT_SNS]     = ADC5_CHAN_VOLT("vbat_sns", 1,
0595                     SCALE_HW_CALIB_DEFAULT)
0596     [ADC5_VCOIN]        = ADC5_CHAN_VOLT("vcoin", 1,
0597                     SCALE_HW_CALIB_DEFAULT)
0598     [ADC5_DIE_TEMP]     = ADC5_CHAN_TEMP("die_temp", 0,
0599                     SCALE_HW_CALIB_PMIC_THERM)
0600     [ADC5_AMUX_THM1_100K_PU] = ADC5_CHAN_TEMP("amux_thm1_100k_pu", 0,
0601                     SCALE_HW_CALIB_THERM_100K_PULLUP)
0602     [ADC5_AMUX_THM2_100K_PU] = ADC5_CHAN_TEMP("amux_thm2_100k_pu", 0,
0603                     SCALE_HW_CALIB_THERM_100K_PULLUP)
0604     [ADC5_AMUX_THM3_100K_PU] = ADC5_CHAN_TEMP("amux_thm3_100k_pu", 0,
0605                     SCALE_HW_CALIB_THERM_100K_PULLUP)
0606     [ADC5_AMUX_THM4_100K_PU] = ADC5_CHAN_TEMP("amux_thm4_100k_pu", 0,
0607                     SCALE_HW_CALIB_THERM_100K_PULLUP)
0608     [ADC5_AMUX_THM5_100K_PU] = ADC5_CHAN_TEMP("amux_thm5_100k_pu", 0,
0609                     SCALE_HW_CALIB_THERM_100K_PULLUP)
0610     [ADC5_XO_THERM_100K_PU] = ADC5_CHAN_TEMP("xo_therm_100k_pu", 0,
0611                     SCALE_HW_CALIB_THERM_100K_PULLUP)
0612 };
0613 
0614 static int adc5_get_dt_channel_data(struct adc5_chip *adc,
0615                     struct adc5_channel_prop *prop,
0616                     struct device_node *node,
0617                     const struct adc5_data *data)
0618 {
0619     const char *name = node->name, *channel_name;
0620     u32 chan, value, varr[2];
0621     u32 sid = 0;
0622     int ret;
0623     struct device *dev = adc->dev;
0624 
0625     ret = of_property_read_u32(node, "reg", &chan);
0626     if (ret) {
0627         dev_err(dev, "invalid channel number %s\n", name);
0628         return ret;
0629     }
0630 
0631     /* Value read from "reg" is virtual channel number */
0632 
0633     /* virtual channel number = sid << 8 | channel number */
0634 
0635     if (adc->data->info == &adc7_info) {
0636         sid = chan >> ADC_CHANNEL_OFFSET;
0637         chan = chan & ADC_CHANNEL_MASK;
0638     }
0639 
0640     if (chan > ADC5_PARALLEL_ISENSE_VBAT_IDATA ||
0641         !data->adc_chans[chan].datasheet_name) {
0642         dev_err(dev, "%s invalid channel number %d\n", name, chan);
0643         return -EINVAL;
0644     }
0645 
0646     /* the channel has DT description */
0647     prop->channel = chan;
0648     prop->sid = sid;
0649 
0650     channel_name = of_get_property(node,
0651                 "label", NULL) ? : node->name;
0652     if (!channel_name) {
0653         dev_err(dev, "Invalid channel name\n");
0654         return -EINVAL;
0655     }
0656     prop->datasheet_name = channel_name;
0657 
0658     ret = of_property_read_u32(node, "qcom,decimation", &value);
0659     if (!ret) {
0660         ret = qcom_adc5_decimation_from_dt(value, data->decimation);
0661         if (ret < 0) {
0662             dev_err(dev, "%02x invalid decimation %d\n",
0663                 chan, value);
0664             return ret;
0665         }
0666         prop->decimation = ret;
0667     } else {
0668         prop->decimation = ADC5_DECIMATION_DEFAULT;
0669     }
0670 
0671     ret = of_property_read_u32_array(node, "qcom,pre-scaling", varr, 2);
0672     if (!ret) {
0673         ret = qcom_adc5_prescaling_from_dt(varr[0], varr[1]);
0674         if (ret < 0) {
0675             dev_err(dev, "%02x invalid pre-scaling <%d %d>\n",
0676                 chan, varr[0], varr[1]);
0677             return ret;
0678         }
0679         prop->prescale = ret;
0680     } else {
0681         prop->prescale =
0682             adc->data->adc_chans[prop->channel].prescale_index;
0683     }
0684 
0685     ret = of_property_read_u32(node, "qcom,hw-settle-time", &value);
0686     if (!ret) {
0687         u8 dig_version[2];
0688 
0689         ret = adc5_read(adc, ADC5_USR_REVISION1, dig_version,
0690                             sizeof(dig_version));
0691         if (ret) {
0692             dev_err(dev, "Invalid dig version read %d\n", ret);
0693             return ret;
0694         }
0695 
0696         dev_dbg(dev, "dig_ver:minor:%d, major:%d\n", dig_version[0],
0697                         dig_version[1]);
0698         /* Digital controller >= 5.3 have hw_settle_2 option */
0699         if ((dig_version[0] >= ADC5_HW_SETTLE_DIFF_MINOR &&
0700             dig_version[1] >= ADC5_HW_SETTLE_DIFF_MAJOR) ||
0701             adc->data->info == &adc7_info)
0702             ret = qcom_adc5_hw_settle_time_from_dt(value, data->hw_settle_2);
0703         else
0704             ret = qcom_adc5_hw_settle_time_from_dt(value, data->hw_settle_1);
0705 
0706         if (ret < 0) {
0707             dev_err(dev, "%02x invalid hw-settle-time %d us\n",
0708                 chan, value);
0709             return ret;
0710         }
0711         prop->hw_settle_time = ret;
0712     } else {
0713         prop->hw_settle_time = VADC_DEF_HW_SETTLE_TIME;
0714     }
0715 
0716     ret = of_property_read_u32(node, "qcom,avg-samples", &value);
0717     if (!ret) {
0718         ret = qcom_adc5_avg_samples_from_dt(value);
0719         if (ret < 0) {
0720             dev_err(dev, "%02x invalid avg-samples %d\n",
0721                 chan, value);
0722             return ret;
0723         }
0724         prop->avg_samples = ret;
0725     } else {
0726         prop->avg_samples = VADC_DEF_AVG_SAMPLES;
0727     }
0728 
0729     if (of_property_read_bool(node, "qcom,ratiometric"))
0730         prop->cal_method = ADC5_RATIOMETRIC_CAL;
0731     else
0732         prop->cal_method = ADC5_ABSOLUTE_CAL;
0733 
0734     /*
0735      * Default to using timer calibration. Using a fresh calibration value
0736      * for every conversion will increase the overall time for a request.
0737      */
0738     prop->cal_val = ADC5_TIMER_CAL;
0739 
0740     dev_dbg(dev, "%02x name %s\n", chan, name);
0741 
0742     return 0;
0743 }
0744 
0745 static const struct adc5_data adc5_data_pmic = {
0746     .full_scale_code_volt = 0x70e4,
0747     .full_scale_code_cur = 0x2710,
0748     .adc_chans = adc5_chans_pmic,
0749     .info = &adc5_info,
0750     .decimation = (unsigned int [ADC5_DECIMATION_SAMPLES_MAX])
0751                 {250, 420, 840},
0752     .hw_settle_1 = (unsigned int [VADC_HW_SETTLE_SAMPLES_MAX])
0753                 {15, 100, 200, 300, 400, 500, 600, 700,
0754                 800, 900, 1, 2, 4, 6, 8, 10},
0755     .hw_settle_2 = (unsigned int [VADC_HW_SETTLE_SAMPLES_MAX])
0756                 {15, 100, 200, 300, 400, 500, 600, 700,
0757                 1, 2, 4, 8, 16, 32, 64, 128},
0758 };
0759 
0760 static const struct adc5_data adc7_data_pmic = {
0761     .full_scale_code_volt = 0x70e4,
0762     .adc_chans = adc7_chans_pmic,
0763     .info = &adc7_info,
0764     .decimation = (unsigned int [ADC5_DECIMATION_SAMPLES_MAX])
0765                 {85, 340, 1360},
0766     .hw_settle_2 = (unsigned int [VADC_HW_SETTLE_SAMPLES_MAX])
0767                 {15, 100, 200, 300, 400, 500, 600, 700,
0768                 1000, 2000, 4000, 8000, 16000, 32000,
0769                 64000, 128000},
0770 };
0771 
0772 static const struct adc5_data adc5_data_pmic_rev2 = {
0773     .full_scale_code_volt = 0x4000,
0774     .full_scale_code_cur = 0x1800,
0775     .adc_chans = adc5_chans_rev2,
0776     .info = &adc5_info,
0777     .decimation = (unsigned int [ADC5_DECIMATION_SAMPLES_MAX])
0778                 {256, 512, 1024},
0779     .hw_settle_1 = (unsigned int [VADC_HW_SETTLE_SAMPLES_MAX])
0780                 {0, 100, 200, 300, 400, 500, 600, 700,
0781                 800, 900, 1, 2, 4, 6, 8, 10},
0782     .hw_settle_2 = (unsigned int [VADC_HW_SETTLE_SAMPLES_MAX])
0783                 {15, 100, 200, 300, 400, 500, 600, 700,
0784                 1, 2, 4, 8, 16, 32, 64, 128},
0785 };
0786 
0787 static const struct of_device_id adc5_match_table[] = {
0788     {
0789         .compatible = "qcom,spmi-adc5",
0790         .data = &adc5_data_pmic,
0791     },
0792     {
0793         .compatible = "qcom,spmi-adc7",
0794         .data = &adc7_data_pmic,
0795     },
0796     {
0797         .compatible = "qcom,spmi-adc-rev2",
0798         .data = &adc5_data_pmic_rev2,
0799     },
0800     { }
0801 };
0802 MODULE_DEVICE_TABLE(of, adc5_match_table);
0803 
0804 static int adc5_get_dt_data(struct adc5_chip *adc, struct device_node *node)
0805 {
0806     const struct adc5_channels *adc_chan;
0807     struct iio_chan_spec *iio_chan;
0808     struct adc5_channel_prop prop, *chan_props;
0809     struct device_node *child;
0810     unsigned int index = 0;
0811     int ret;
0812 
0813     adc->nchannels = of_get_available_child_count(node);
0814     if (!adc->nchannels)
0815         return -EINVAL;
0816 
0817     adc->iio_chans = devm_kcalloc(adc->dev, adc->nchannels,
0818                        sizeof(*adc->iio_chans), GFP_KERNEL);
0819     if (!adc->iio_chans)
0820         return -ENOMEM;
0821 
0822     adc->chan_props = devm_kcalloc(adc->dev, adc->nchannels,
0823                     sizeof(*adc->chan_props), GFP_KERNEL);
0824     if (!adc->chan_props)
0825         return -ENOMEM;
0826 
0827     chan_props = adc->chan_props;
0828     iio_chan = adc->iio_chans;
0829     adc->data = of_device_get_match_data(adc->dev);
0830     if (!adc->data)
0831         adc->data = &adc5_data_pmic;
0832 
0833     for_each_available_child_of_node(node, child) {
0834         ret = adc5_get_dt_channel_data(adc, &prop, child, adc->data);
0835         if (ret) {
0836             of_node_put(child);
0837             return ret;
0838         }
0839 
0840         prop.scale_fn_type =
0841             adc->data->adc_chans[prop.channel].scale_fn_type;
0842         *chan_props = prop;
0843         adc_chan = &adc->data->adc_chans[prop.channel];
0844 
0845         iio_chan->channel = prop.channel;
0846         iio_chan->datasheet_name = prop.datasheet_name;
0847         iio_chan->extend_name = prop.datasheet_name;
0848         iio_chan->info_mask_separate = adc_chan->info_mask;
0849         iio_chan->type = adc_chan->type;
0850         iio_chan->address = index;
0851         iio_chan++;
0852         chan_props++;
0853         index++;
0854     }
0855 
0856     return 0;
0857 }
0858 
0859 static int adc5_probe(struct platform_device *pdev)
0860 {
0861     struct device_node *node = pdev->dev.of_node;
0862     struct device *dev = &pdev->dev;
0863     struct iio_dev *indio_dev;
0864     struct adc5_chip *adc;
0865     struct regmap *regmap;
0866     int ret, irq_eoc;
0867     u32 reg;
0868 
0869     regmap = dev_get_regmap(dev->parent, NULL);
0870     if (!regmap)
0871         return -ENODEV;
0872 
0873     ret = of_property_read_u32(node, "reg", &reg);
0874     if (ret < 0)
0875         return ret;
0876 
0877     indio_dev = devm_iio_device_alloc(dev, sizeof(*adc));
0878     if (!indio_dev)
0879         return -ENOMEM;
0880 
0881     adc = iio_priv(indio_dev);
0882     adc->regmap = regmap;
0883     adc->dev = dev;
0884     adc->base = reg;
0885 
0886     init_completion(&adc->complete);
0887     mutex_init(&adc->lock);
0888 
0889     ret = adc5_get_dt_data(adc, node);
0890     if (ret) {
0891         dev_err(dev, "adc get dt data failed\n");
0892         return ret;
0893     }
0894 
0895     irq_eoc = platform_get_irq(pdev, 0);
0896     if (irq_eoc < 0) {
0897         if (irq_eoc == -EPROBE_DEFER || irq_eoc == -EINVAL)
0898             return irq_eoc;
0899         adc->poll_eoc = true;
0900     } else {
0901         ret = devm_request_irq(dev, irq_eoc, adc5_isr, 0,
0902                        "pm-adc5", adc);
0903         if (ret)
0904             return ret;
0905     }
0906 
0907     indio_dev->name = pdev->name;
0908     indio_dev->modes = INDIO_DIRECT_MODE;
0909     indio_dev->info = adc->data->info;
0910     indio_dev->channels = adc->iio_chans;
0911     indio_dev->num_channels = adc->nchannels;
0912 
0913     return devm_iio_device_register(dev, indio_dev);
0914 }
0915 
0916 static struct platform_driver adc5_driver = {
0917     .driver = {
0918         .name = "qcom-spmi-adc5",
0919         .of_match_table = adc5_match_table,
0920     },
0921     .probe = adc5_probe,
0922 };
0923 module_platform_driver(adc5_driver);
0924 
0925 MODULE_ALIAS("platform:qcom-spmi-adc5");
0926 MODULE_DESCRIPTION("Qualcomm Technologies Inc. PMIC5 ADC driver");
0927 MODULE_LICENSE("GPL v2");
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