iio/adc/npcm_adc.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 // Copyright (c) 2019 Nuvoton Technology corporation.
0003
0004 #include <linux/clk.h>
0005 #include <linux/device.h>
0006 #include <linux/mfd/syscon.h>
0007 #include <linux/io.h>
0008 #include <linux/iio/iio.h>
0009 #include <linux/interrupt.h>
0010 #include <linux/kernel.h>
0011 #include <linux/mod_devicetable.h>
0012 #include <linux/module.h>
0013 #include <linux/platform_device.h>
0014 #include <linux/property.h>
0015 #include <linux/regmap.h>
0016 #include <linux/regulator/consumer.h>
0017 #include <linux/spinlock.h>
0018 #include <linux/uaccess.h>
0019 #include <linux/reset.h>
0020
0021 struct npcm_adc_info {
0022     u32 data_mask;
0023     u32 internal_vref;
0024     u32 res_bits;
0025 };
0026
0027 struct npcm_adc {
0028     bool int_status;
0029     u32 adc_sample_hz;
0030     struct device *dev;
0031     void __iomem *regs;
0032     struct clk *adc_clk;
0033     wait_queue_head_t wq;
0034     struct regulator *vref;
0035     struct reset_control *reset;
0036     /*
0037      * Lock to protect the device state during a potential concurrent
0038      * read access from userspace. Reading a raw value requires a sequence
0039      * of register writes, then a wait for a event and finally a register
0040      * read, during which userspace could issue another read request.
0041      * This lock protects a read access from ocurring before another one
0042      * has finished.
0043      */
0044     struct mutex lock;
0045     const struct npcm_adc_info *data;
0046 };
0047
0048 /* ADC registers */
0049 #define NPCM_ADCCON  0x00
0050 #define NPCM_ADCDATA     0x04
0051
0052 /* ADCCON Register Bits */
0053 #define NPCM_ADCCON_ADC_INT_EN      BIT(21)
0054 #define NPCM_ADCCON_REFSEL      BIT(19)
0055 #define NPCM_ADCCON_ADC_INT_ST      BIT(18)
0056 #define NPCM_ADCCON_ADC_EN      BIT(17)
0057 #define NPCM_ADCCON_ADC_RST     BIT(16)
0058 #define NPCM_ADCCON_ADC_CONV        BIT(13)
0059
0060 #define NPCM_ADCCON_CH_MASK     GENMASK(27, 24)
0061 #define NPCM_ADCCON_CH(x)       ((x) << 24)
0062 #define NPCM_ADCCON_DIV_SHIFT       1
0063 #define NPCM_ADCCON_DIV_MASK        GENMASK(8, 1)
0064
0065 #define NPCM_ADC_ENABLE     (NPCM_ADCCON_ADC_EN | NPCM_ADCCON_ADC_INT_EN)
0066
0067 /* ADC General Definition */
0068 static const struct npcm_adc_info npxm7xx_adc_info = {
0069     .data_mask = GENMASK(9, 0),
0070     .internal_vref = 2048,
0071     .res_bits = 10,
0072 };
0073
0074 static const struct npcm_adc_info npxm8xx_adc_info = {
0075     .data_mask = GENMASK(11, 0),
0076     .internal_vref = 1229,
0077     .res_bits = 12,
0078 };
0079
0080 #define NPCM_ADC_CHAN(ch) {                 \
0081     .type = IIO_VOLTAGE,                    \
0082     .indexed = 1,                       \
0083     .channel = ch,                      \
0084     .info_mask_separate = BIT(IIO_CHAN_INFO_RAW),       \
0085     .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) |  \
0086                 BIT(IIO_CHAN_INFO_SAMP_FREQ),   \
0087 }
0088
0089 static const struct iio_chan_spec npcm_adc_iio_channels[] = {
0090     NPCM_ADC_CHAN(0),
0091     NPCM_ADC_CHAN(1),
0092     NPCM_ADC_CHAN(2),
0093     NPCM_ADC_CHAN(3),
0094     NPCM_ADC_CHAN(4),
0095     NPCM_ADC_CHAN(5),
0096     NPCM_ADC_CHAN(6),
0097     NPCM_ADC_CHAN(7),
0098 };
0099
0100 static irqreturn_t npcm_adc_isr(int irq, void *data)
0101 {
0102     u32 regtemp;
0103     struct iio_dev *indio_dev = data;
0104     struct npcm_adc *info = iio_priv(indio_dev);
0105
0106     regtemp = ioread32(info->regs + NPCM_ADCCON);
0107     if (regtemp & NPCM_ADCCON_ADC_INT_ST) {
0108         iowrite32(regtemp, info->regs + NPCM_ADCCON);
0109         wake_up_interruptible(&info->wq);
0110         info->int_status = true;
0111     }
0112
0113     return IRQ_HANDLED;
0114 }
0115
0116 static int npcm_adc_read(struct npcm_adc *info, int *val, u8 channel)
0117 {
0118     int ret;
0119     u32 regtemp;
0120
0121     /* Select ADC channel */
0122     regtemp = ioread32(info->regs + NPCM_ADCCON);
0123     regtemp &= ~NPCM_ADCCON_CH_MASK;
0124     info->int_status = false;
0125     iowrite32(regtemp | NPCM_ADCCON_CH(channel) |
0126           NPCM_ADCCON_ADC_CONV, info->regs + NPCM_ADCCON);
0127
0128     ret = wait_event_interruptible_timeout(info->wq, info->int_status,
0129                            msecs_to_jiffies(10));
0130     if (ret == 0) {
0131         regtemp = ioread32(info->regs + NPCM_ADCCON);
0132         if (regtemp & NPCM_ADCCON_ADC_CONV) {
0133             /* if conversion failed - reset ADC module */
0134             reset_control_assert(info->reset);
0135             msleep(100);
0136             reset_control_deassert(info->reset);
0137             msleep(100);
0138
0139             /* Enable ADC and start conversion module */
0140             iowrite32(NPCM_ADC_ENABLE | NPCM_ADCCON_ADC_CONV,
0141                   info->regs + NPCM_ADCCON);
0142             dev_err(info->dev, "RESET ADC Complete\n");
0143         }
0144         return -ETIMEDOUT;
0145     }
0146     if (ret < 0)
0147         return ret;
0148
0149     *val = ioread32(info->regs + NPCM_ADCDATA);
0150     *val &= info->data->data_mask;
0151
0152     return 0;
0153 }
0154
0155 static int npcm_adc_read_raw(struct iio_dev *indio_dev,
0156                  struct iio_chan_spec const *chan, int *val,
0157                  int *val2, long mask)
0158 {
0159     int ret;
0160     int vref_uv;
0161     struct npcm_adc *info = iio_priv(indio_dev);
0162
0163     switch (mask) {
0164     case IIO_CHAN_INFO_RAW:
0165         mutex_lock(&info->lock);
0166         ret = npcm_adc_read(info, val, chan->channel);
0167         mutex_unlock(&info->lock);
0168         if (ret) {
0169             dev_err(info->dev, "NPCM ADC read failed\n");
0170             return ret;
0171         }
0172         return IIO_VAL_INT;
0173     case IIO_CHAN_INFO_SCALE:
0174         if (!IS_ERR(info->vref)) {
0175             vref_uv = regulator_get_voltage(info->vref);
0176             *val = vref_uv / 1000;
0177         } else {
0178             *val = info->data->internal_vref;
0179         }
0180         *val2 = info->data->res_bits;
0181         return IIO_VAL_FRACTIONAL_LOG2;
0182     case IIO_CHAN_INFO_SAMP_FREQ:
0183         *val = info->adc_sample_hz;
0184         return IIO_VAL_INT;
0185     default:
0186         return -EINVAL;
0187     }
0188
0189     return 0;
0190 }
0191
0192 static const struct iio_info npcm_adc_iio_info = {
0193     .read_raw = &npcm_adc_read_raw,
0194 };
0195
0196 static const struct of_device_id npcm_adc_match[] = {
0197     { .compatible = "nuvoton,npcm750-adc", .data = &npxm7xx_adc_info},
0198     { .compatible = "nuvoton,npcm845-adc", .data = &npxm8xx_adc_info},
0199     { /* sentinel */ }
0200 };
0201 MODULE_DEVICE_TABLE(of, npcm_adc_match);
0202
0203 static int npcm_adc_probe(struct platform_device *pdev)
0204 {
0205     int ret;
0206     int irq;
0207     u32 div;
0208     u32 reg_con;
0209     struct npcm_adc *info;
0210     struct iio_dev *indio_dev;
0211     struct device *dev = &pdev->dev;
0212
0213     indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*info));
0214     if (!indio_dev)
0215         return -ENOMEM;
0216     info = iio_priv(indio_dev);
0217
0218     info->data = device_get_match_data(dev);
0219     if (!info->data)
0220         return -EINVAL;
0221
0222     mutex_init(&info->lock);
0223
0224     info->dev = &pdev->dev;
0225
0226     info->regs = devm_platform_ioremap_resource(pdev, 0);
0227     if (IS_ERR(info->regs))
0228         return PTR_ERR(info->regs);
0229
0230     info->reset = devm_reset_control_get(&pdev->dev, NULL);
0231     if (IS_ERR(info->reset))
0232         return PTR_ERR(info->reset);
0233
0234     info->adc_clk = devm_clk_get(&pdev->dev, NULL);
0235     if (IS_ERR(info->adc_clk)) {
0236         dev_warn(&pdev->dev, "ADC clock failed: can't read clk\n");
0237         return PTR_ERR(info->adc_clk);
0238     }
0239
0240     /* calculate ADC clock sample rate */
0241     reg_con = ioread32(info->regs + NPCM_ADCCON);
0242     div = reg_con & NPCM_ADCCON_DIV_MASK;
0243     div = div >> NPCM_ADCCON_DIV_SHIFT;
0244     info->adc_sample_hz = clk_get_rate(info->adc_clk) / ((div + 1) * 2);
0245
0246     irq = platform_get_irq(pdev, 0);
0247     if (irq <= 0) {
0248         ret = -EINVAL;
0249         goto err_disable_clk;
0250     }
0251
0252     ret = devm_request_irq(&pdev->dev, irq, npcm_adc_isr, 0,
0253                    "NPCM_ADC", indio_dev);
0254     if (ret < 0) {
0255         dev_err(dev, "failed requesting interrupt\n");
0256         goto err_disable_clk;
0257     }
0258
0259     reg_con = ioread32(info->regs + NPCM_ADCCON);
0260     info->vref = devm_regulator_get_optional(&pdev->dev, "vref");
0261     if (!IS_ERR(info->vref)) {
0262         ret = regulator_enable(info->vref);
0263         if (ret) {
0264             dev_err(&pdev->dev, "Can't enable ADC reference voltage\n");
0265             goto err_disable_clk;
0266         }
0267
0268         iowrite32(reg_con & ~NPCM_ADCCON_REFSEL,
0269               info->regs + NPCM_ADCCON);
0270     } else {
0271         /*
0272          * Any error which is not ENODEV indicates the regulator
0273          * has been specified and so is a failure case.
0274          */
0275         if (PTR_ERR(info->vref) != -ENODEV) {
0276             ret = PTR_ERR(info->vref);
0277             goto err_disable_clk;
0278         }
0279
0280         /* Use internal reference */
0281         iowrite32(reg_con | NPCM_ADCCON_REFSEL,
0282               info->regs + NPCM_ADCCON);
0283     }
0284
0285     init_waitqueue_head(&info->wq);
0286
0287     reg_con = ioread32(info->regs + NPCM_ADCCON);
0288     reg_con |= NPCM_ADC_ENABLE;
0289
0290     /* Enable the ADC Module */
0291     iowrite32(reg_con, info->regs + NPCM_ADCCON);
0292
0293     /* Start ADC conversion */
0294     iowrite32(reg_con | NPCM_ADCCON_ADC_CONV, info->regs + NPCM_ADCCON);
0295
0296     platform_set_drvdata(pdev, indio_dev);
0297     indio_dev->name = dev_name(&pdev->dev);
0298     indio_dev->info = &npcm_adc_iio_info;
0299     indio_dev->modes = INDIO_DIRECT_MODE;
0300     indio_dev->channels = npcm_adc_iio_channels;
0301     indio_dev->num_channels = ARRAY_SIZE(npcm_adc_iio_channels);
0302
0303     ret = iio_device_register(indio_dev);
0304     if (ret) {
0305         dev_err(&pdev->dev, "Couldn't register the device.\n");
0306         goto err_iio_register;
0307     }
0308
0309     pr_info("NPCM ADC driver probed\n");
0310
0311     return 0;
0312
0313 err_iio_register:
0314     iowrite32(reg_con & ~NPCM_ADCCON_ADC_EN, info->regs + NPCM_ADCCON);
0315     if (!IS_ERR(info->vref))
0316         regulator_disable(info->vref);
0317 err_disable_clk:
0318     clk_disable_unprepare(info->adc_clk);
0319
0320     return ret;
0321 }
0322
0323 static int npcm_adc_remove(struct platform_device *pdev)
0324 {
0325     struct iio_dev *indio_dev = platform_get_drvdata(pdev);
0326     struct npcm_adc *info = iio_priv(indio_dev);
0327     u32 regtemp;
0328
0329     iio_device_unregister(indio_dev);
0330
0331     regtemp = ioread32(info->regs + NPCM_ADCCON);
0332     iowrite32(regtemp & ~NPCM_ADCCON_ADC_EN, info->regs + NPCM_ADCCON);
0333     if (!IS_ERR(info->vref))
0334         regulator_disable(info->vref);
0335     clk_disable_unprepare(info->adc_clk);
0336
0337     return 0;
0338 }
0339
0340 static struct platform_driver npcm_adc_driver = {
0341     .probe      = npcm_adc_probe,
0342     .remove     = npcm_adc_remove,
0343     .driver     = {
0344         .name   = "npcm_adc",
0345         .of_match_table = npcm_adc_match,
0346     },
0347 };
0348
0349 module_platform_driver(npcm_adc_driver);
0350
0351 MODULE_DESCRIPTION("Nuvoton NPCM ADC Driver");
0352 MODULE_AUTHOR("Tomer Maimon <tomer.maimon@nuvoton.com>");
0353 MODULE_LICENSE("GPL v2");