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0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Freescale MXS LRADC ADC driver
0004  *
0005  * Copyright (c) 2012 DENX Software Engineering, GmbH.
0006  * Copyright (c) 2017 Ksenija Stanojevic <ksenija.stanojevic@gmail.com>
0007  *
0008  * Authors:
0009  *  Marek Vasut <marex@denx.de>
0010  *  Ksenija Stanojevic <ksenija.stanojevic@gmail.com>
0011  */
0012 
0013 #include <linux/completion.h>
0014 #include <linux/device.h>
0015 #include <linux/err.h>
0016 #include <linux/interrupt.h>
0017 #include <linux/mfd/core.h>
0018 #include <linux/mfd/mxs-lradc.h>
0019 #include <linux/module.h>
0020 #include <linux/of_irq.h>
0021 #include <linux/platform_device.h>
0022 #include <linux/sysfs.h>
0023 
0024 #include <linux/iio/buffer.h>
0025 #include <linux/iio/iio.h>
0026 #include <linux/iio/trigger.h>
0027 #include <linux/iio/trigger_consumer.h>
0028 #include <linux/iio/triggered_buffer.h>
0029 #include <linux/iio/sysfs.h>
0030 
0031 /*
0032  * Make this runtime configurable if necessary. Currently, if the buffered mode
0033  * is enabled, the LRADC takes LRADC_DELAY_TIMER_LOOP samples of data before
0034  * triggering IRQ. The sampling happens every (LRADC_DELAY_TIMER_PER / 2000)
0035  * seconds. The result is that the samples arrive every 500mS.
0036  */
0037 #define LRADC_DELAY_TIMER_PER   200
0038 #define LRADC_DELAY_TIMER_LOOP  5
0039 
0040 #define VREF_MV_BASE 1850
0041 
0042 static const char *mx23_lradc_adc_irq_names[] = {
0043     "mxs-lradc-channel0",
0044     "mxs-lradc-channel1",
0045     "mxs-lradc-channel2",
0046     "mxs-lradc-channel3",
0047     "mxs-lradc-channel4",
0048     "mxs-lradc-channel5",
0049 };
0050 
0051 static const char *mx28_lradc_adc_irq_names[] = {
0052     "mxs-lradc-thresh0",
0053     "mxs-lradc-thresh1",
0054     "mxs-lradc-channel0",
0055     "mxs-lradc-channel1",
0056     "mxs-lradc-channel2",
0057     "mxs-lradc-channel3",
0058     "mxs-lradc-channel4",
0059     "mxs-lradc-channel5",
0060     "mxs-lradc-button0",
0061     "mxs-lradc-button1",
0062 };
0063 
0064 static const u32 mxs_lradc_adc_vref_mv[][LRADC_MAX_TOTAL_CHANS] = {
0065     [IMX23_LRADC] = {
0066         VREF_MV_BASE,       /* CH0 */
0067         VREF_MV_BASE,       /* CH1 */
0068         VREF_MV_BASE,       /* CH2 */
0069         VREF_MV_BASE,       /* CH3 */
0070         VREF_MV_BASE,       /* CH4 */
0071         VREF_MV_BASE,       /* CH5 */
0072         VREF_MV_BASE * 2,   /* CH6 VDDIO */
0073         VREF_MV_BASE * 4,   /* CH7 VBATT */
0074         VREF_MV_BASE,       /* CH8 Temp sense 0 */
0075         VREF_MV_BASE,       /* CH9 Temp sense 1 */
0076         VREF_MV_BASE,       /* CH10 */
0077         VREF_MV_BASE,       /* CH11 */
0078         VREF_MV_BASE,       /* CH12 USB_DP */
0079         VREF_MV_BASE,       /* CH13 USB_DN */
0080         VREF_MV_BASE,       /* CH14 VBG */
0081         VREF_MV_BASE * 4,   /* CH15 VDD5V */
0082     },
0083     [IMX28_LRADC] = {
0084         VREF_MV_BASE,       /* CH0 */
0085         VREF_MV_BASE,       /* CH1 */
0086         VREF_MV_BASE,       /* CH2 */
0087         VREF_MV_BASE,       /* CH3 */
0088         VREF_MV_BASE,       /* CH4 */
0089         VREF_MV_BASE,       /* CH5 */
0090         VREF_MV_BASE,       /* CH6 */
0091         VREF_MV_BASE * 4,   /* CH7 VBATT */
0092         VREF_MV_BASE,       /* CH8 Temp sense 0 */
0093         VREF_MV_BASE,       /* CH9 Temp sense 1 */
0094         VREF_MV_BASE * 2,   /* CH10 VDDIO */
0095         VREF_MV_BASE,       /* CH11 VTH */
0096         VREF_MV_BASE * 2,   /* CH12 VDDA */
0097         VREF_MV_BASE,       /* CH13 VDDD */
0098         VREF_MV_BASE,       /* CH14 VBG */
0099         VREF_MV_BASE * 4,   /* CH15 VDD5V */
0100     },
0101 };
0102 
0103 enum mxs_lradc_divbytwo {
0104     MXS_LRADC_DIV_DISABLED = 0,
0105     MXS_LRADC_DIV_ENABLED,
0106 };
0107 
0108 struct mxs_lradc_scale {
0109     unsigned int        integer;
0110     unsigned int        nano;
0111 };
0112 
0113 struct mxs_lradc_adc {
0114     struct mxs_lradc    *lradc;
0115     struct device       *dev;
0116 
0117     void __iomem        *base;
0118     /* Maximum of 8 channels + 8 byte ts */
0119     u32         buffer[10] __aligned(8);
0120     struct iio_trigger  *trig;
0121     struct completion   completion;
0122     spinlock_t      lock;
0123 
0124     const u32       *vref_mv;
0125     struct mxs_lradc_scale  scale_avail[LRADC_MAX_TOTAL_CHANS][2];
0126     unsigned long       is_divided;
0127 };
0128 
0129 
0130 /* Raw I/O operations */
0131 static int mxs_lradc_adc_read_single(struct iio_dev *iio_dev, int chan,
0132                      int *val)
0133 {
0134     struct mxs_lradc_adc *adc = iio_priv(iio_dev);
0135     struct mxs_lradc *lradc = adc->lradc;
0136     int ret;
0137 
0138     /*
0139      * See if there is no buffered operation in progress. If there is simply
0140      * bail out. This can be improved to support both buffered and raw IO at
0141      * the same time, yet the code becomes horribly complicated. Therefore I
0142      * applied KISS principle here.
0143      */
0144     ret = iio_device_claim_direct_mode(iio_dev);
0145     if (ret)
0146         return ret;
0147 
0148     reinit_completion(&adc->completion);
0149 
0150     /*
0151      * No buffered operation in progress, map the channel and trigger it.
0152      * Virtual channel 0 is always used here as the others are always not
0153      * used if doing raw sampling.
0154      */
0155     if (lradc->soc == IMX28_LRADC)
0156         writel(LRADC_CTRL1_LRADC_IRQ_EN(0),
0157                adc->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR);
0158     writel(0x1, adc->base + LRADC_CTRL0 + STMP_OFFSET_REG_CLR);
0159 
0160     /* Enable / disable the divider per requirement */
0161     if (test_bit(chan, &adc->is_divided))
0162         writel(1 << LRADC_CTRL2_DIVIDE_BY_TWO_OFFSET,
0163                adc->base + LRADC_CTRL2 + STMP_OFFSET_REG_SET);
0164     else
0165         writel(1 << LRADC_CTRL2_DIVIDE_BY_TWO_OFFSET,
0166                adc->base + LRADC_CTRL2 + STMP_OFFSET_REG_CLR);
0167 
0168     /* Clean the slot's previous content, then set new one. */
0169     writel(LRADC_CTRL4_LRADCSELECT_MASK(0),
0170            adc->base + LRADC_CTRL4 + STMP_OFFSET_REG_CLR);
0171     writel(chan, adc->base + LRADC_CTRL4 + STMP_OFFSET_REG_SET);
0172 
0173     writel(0, adc->base + LRADC_CH(0));
0174 
0175     /* Enable the IRQ and start sampling the channel. */
0176     writel(LRADC_CTRL1_LRADC_IRQ_EN(0),
0177            adc->base + LRADC_CTRL1 + STMP_OFFSET_REG_SET);
0178     writel(BIT(0), adc->base + LRADC_CTRL0 + STMP_OFFSET_REG_SET);
0179 
0180     /* Wait for completion on the channel, 1 second max. */
0181     ret = wait_for_completion_killable_timeout(&adc->completion, HZ);
0182     if (!ret)
0183         ret = -ETIMEDOUT;
0184     if (ret < 0)
0185         goto err;
0186 
0187     /* Read the data. */
0188     *val = readl(adc->base + LRADC_CH(0)) & LRADC_CH_VALUE_MASK;
0189     ret = IIO_VAL_INT;
0190 
0191 err:
0192     writel(LRADC_CTRL1_LRADC_IRQ_EN(0),
0193            adc->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR);
0194 
0195     iio_device_release_direct_mode(iio_dev);
0196 
0197     return ret;
0198 }
0199 
0200 static int mxs_lradc_adc_read_temp(struct iio_dev *iio_dev, int *val)
0201 {
0202     int ret, min, max;
0203 
0204     ret = mxs_lradc_adc_read_single(iio_dev, 8, &min);
0205     if (ret != IIO_VAL_INT)
0206         return ret;
0207 
0208     ret = mxs_lradc_adc_read_single(iio_dev, 9, &max);
0209     if (ret != IIO_VAL_INT)
0210         return ret;
0211 
0212     *val = max - min;
0213 
0214     return IIO_VAL_INT;
0215 }
0216 
0217 static int mxs_lradc_adc_read_raw(struct iio_dev *iio_dev,
0218                   const struct iio_chan_spec *chan,
0219                   int *val, int *val2, long m)
0220 {
0221     struct mxs_lradc_adc *adc = iio_priv(iio_dev);
0222 
0223     switch (m) {
0224     case IIO_CHAN_INFO_RAW:
0225         if (chan->type == IIO_TEMP)
0226             return mxs_lradc_adc_read_temp(iio_dev, val);
0227 
0228         return mxs_lradc_adc_read_single(iio_dev, chan->channel, val);
0229 
0230     case IIO_CHAN_INFO_SCALE:
0231         if (chan->type == IIO_TEMP) {
0232             /*
0233              * From the datasheet, we have to multiply by 1.012 and
0234              * divide by 4
0235              */
0236             *val = 0;
0237             *val2 = 253000;
0238             return IIO_VAL_INT_PLUS_MICRO;
0239         }
0240 
0241         *val = adc->vref_mv[chan->channel];
0242         *val2 = chan->scan_type.realbits -
0243             test_bit(chan->channel, &adc->is_divided);
0244         return IIO_VAL_FRACTIONAL_LOG2;
0245 
0246     case IIO_CHAN_INFO_OFFSET:
0247         if (chan->type == IIO_TEMP) {
0248             /*
0249              * The calculated value from the ADC is in Kelvin, we
0250              * want Celsius for hwmon so the offset is -273.15
0251              * The offset is applied before scaling so it is
0252              * actually -213.15 * 4 / 1.012 = -1079.644268
0253              */
0254             *val = -1079;
0255             *val2 = 644268;
0256 
0257             return IIO_VAL_INT_PLUS_MICRO;
0258         }
0259 
0260         return -EINVAL;
0261 
0262     default:
0263         break;
0264     }
0265 
0266     return -EINVAL;
0267 }
0268 
0269 static int mxs_lradc_adc_write_raw(struct iio_dev *iio_dev,
0270                    const struct iio_chan_spec *chan,
0271                    int val, int val2, long m)
0272 {
0273     struct mxs_lradc_adc *adc = iio_priv(iio_dev);
0274     struct mxs_lradc_scale *scale_avail =
0275             adc->scale_avail[chan->channel];
0276     int ret;
0277 
0278     ret = iio_device_claim_direct_mode(iio_dev);
0279     if (ret)
0280         return ret;
0281 
0282     switch (m) {
0283     case IIO_CHAN_INFO_SCALE:
0284         ret = -EINVAL;
0285         if (val == scale_avail[MXS_LRADC_DIV_DISABLED].integer &&
0286             val2 == scale_avail[MXS_LRADC_DIV_DISABLED].nano) {
0287             /* divider by two disabled */
0288             clear_bit(chan->channel, &adc->is_divided);
0289             ret = 0;
0290         } else if (val == scale_avail[MXS_LRADC_DIV_ENABLED].integer &&
0291                val2 == scale_avail[MXS_LRADC_DIV_ENABLED].nano) {
0292             /* divider by two enabled */
0293             set_bit(chan->channel, &adc->is_divided);
0294             ret = 0;
0295         }
0296 
0297         break;
0298     default:
0299         ret = -EINVAL;
0300         break;
0301     }
0302 
0303     iio_device_release_direct_mode(iio_dev);
0304 
0305     return ret;
0306 }
0307 
0308 static int mxs_lradc_adc_write_raw_get_fmt(struct iio_dev *iio_dev,
0309                        const struct iio_chan_spec *chan,
0310                        long m)
0311 {
0312     return IIO_VAL_INT_PLUS_NANO;
0313 }
0314 
0315 static ssize_t mxs_lradc_adc_show_scale_avail(struct device *dev,
0316                          struct device_attribute *attr,
0317                          char *buf)
0318 {
0319     struct iio_dev *iio = dev_to_iio_dev(dev);
0320     struct mxs_lradc_adc *adc = iio_priv(iio);
0321     struct iio_dev_attr *iio_attr = to_iio_dev_attr(attr);
0322     int i, ch, len = 0;
0323 
0324     ch = iio_attr->address;
0325     for (i = 0; i < ARRAY_SIZE(adc->scale_avail[ch]); i++)
0326         len += sprintf(buf + len, "%u.%09u ",
0327                    adc->scale_avail[ch][i].integer,
0328                    adc->scale_avail[ch][i].nano);
0329 
0330     len += sprintf(buf + len, "\n");
0331 
0332     return len;
0333 }
0334 
0335 #define SHOW_SCALE_AVAILABLE_ATTR(ch)\
0336     IIO_DEVICE_ATTR(in_voltage##ch##_scale_available, 0444,\
0337             mxs_lradc_adc_show_scale_avail, NULL, ch)
0338 
0339 static SHOW_SCALE_AVAILABLE_ATTR(0);
0340 static SHOW_SCALE_AVAILABLE_ATTR(1);
0341 static SHOW_SCALE_AVAILABLE_ATTR(2);
0342 static SHOW_SCALE_AVAILABLE_ATTR(3);
0343 static SHOW_SCALE_AVAILABLE_ATTR(4);
0344 static SHOW_SCALE_AVAILABLE_ATTR(5);
0345 static SHOW_SCALE_AVAILABLE_ATTR(6);
0346 static SHOW_SCALE_AVAILABLE_ATTR(7);
0347 static SHOW_SCALE_AVAILABLE_ATTR(10);
0348 static SHOW_SCALE_AVAILABLE_ATTR(11);
0349 static SHOW_SCALE_AVAILABLE_ATTR(12);
0350 static SHOW_SCALE_AVAILABLE_ATTR(13);
0351 static SHOW_SCALE_AVAILABLE_ATTR(14);
0352 static SHOW_SCALE_AVAILABLE_ATTR(15);
0353 
0354 static struct attribute *mxs_lradc_adc_attributes[] = {
0355     &iio_dev_attr_in_voltage0_scale_available.dev_attr.attr,
0356     &iio_dev_attr_in_voltage1_scale_available.dev_attr.attr,
0357     &iio_dev_attr_in_voltage2_scale_available.dev_attr.attr,
0358     &iio_dev_attr_in_voltage3_scale_available.dev_attr.attr,
0359     &iio_dev_attr_in_voltage4_scale_available.dev_attr.attr,
0360     &iio_dev_attr_in_voltage5_scale_available.dev_attr.attr,
0361     &iio_dev_attr_in_voltage6_scale_available.dev_attr.attr,
0362     &iio_dev_attr_in_voltage7_scale_available.dev_attr.attr,
0363     &iio_dev_attr_in_voltage10_scale_available.dev_attr.attr,
0364     &iio_dev_attr_in_voltage11_scale_available.dev_attr.attr,
0365     &iio_dev_attr_in_voltage12_scale_available.dev_attr.attr,
0366     &iio_dev_attr_in_voltage13_scale_available.dev_attr.attr,
0367     &iio_dev_attr_in_voltage14_scale_available.dev_attr.attr,
0368     &iio_dev_attr_in_voltage15_scale_available.dev_attr.attr,
0369     NULL
0370 };
0371 
0372 static const struct attribute_group mxs_lradc_adc_attribute_group = {
0373     .attrs = mxs_lradc_adc_attributes,
0374 };
0375 
0376 static const struct iio_info mxs_lradc_adc_iio_info = {
0377     .read_raw       = mxs_lradc_adc_read_raw,
0378     .write_raw      = mxs_lradc_adc_write_raw,
0379     .write_raw_get_fmt  = mxs_lradc_adc_write_raw_get_fmt,
0380     .attrs          = &mxs_lradc_adc_attribute_group,
0381 };
0382 
0383 /* IRQ Handling */
0384 static irqreturn_t mxs_lradc_adc_handle_irq(int irq, void *data)
0385 {
0386     struct iio_dev *iio = data;
0387     struct mxs_lradc_adc *adc = iio_priv(iio);
0388     struct mxs_lradc *lradc = adc->lradc;
0389     unsigned long reg = readl(adc->base + LRADC_CTRL1);
0390     unsigned long flags;
0391 
0392     if (!(reg & mxs_lradc_irq_mask(lradc)))
0393         return IRQ_NONE;
0394 
0395     if (iio_buffer_enabled(iio)) {
0396         if (reg & lradc->buffer_vchans) {
0397             spin_lock_irqsave(&adc->lock, flags);
0398             iio_trigger_poll(iio->trig);
0399             spin_unlock_irqrestore(&adc->lock, flags);
0400         }
0401     } else if (reg & LRADC_CTRL1_LRADC_IRQ(0)) {
0402         complete(&adc->completion);
0403     }
0404 
0405     writel(reg & mxs_lradc_irq_mask(lradc),
0406            adc->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR);
0407 
0408     return IRQ_HANDLED;
0409 }
0410 
0411 
0412 /* Trigger handling */
0413 static irqreturn_t mxs_lradc_adc_trigger_handler(int irq, void *p)
0414 {
0415     struct iio_poll_func *pf = p;
0416     struct iio_dev *iio = pf->indio_dev;
0417     struct mxs_lradc_adc *adc = iio_priv(iio);
0418     const u32 chan_value = LRADC_CH_ACCUMULATE |
0419         ((LRADC_DELAY_TIMER_LOOP - 1) << LRADC_CH_NUM_SAMPLES_OFFSET);
0420     unsigned int i, j = 0;
0421 
0422     for_each_set_bit(i, iio->active_scan_mask, LRADC_MAX_TOTAL_CHANS) {
0423         adc->buffer[j] = readl(adc->base + LRADC_CH(j));
0424         writel(chan_value, adc->base + LRADC_CH(j));
0425         adc->buffer[j] &= LRADC_CH_VALUE_MASK;
0426         adc->buffer[j] /= LRADC_DELAY_TIMER_LOOP;
0427         j++;
0428     }
0429 
0430     iio_push_to_buffers_with_timestamp(iio, adc->buffer, pf->timestamp);
0431 
0432     iio_trigger_notify_done(iio->trig);
0433 
0434     return IRQ_HANDLED;
0435 }
0436 
0437 static int mxs_lradc_adc_configure_trigger(struct iio_trigger *trig, bool state)
0438 {
0439     struct iio_dev *iio = iio_trigger_get_drvdata(trig);
0440     struct mxs_lradc_adc *adc = iio_priv(iio);
0441     const u32 st = state ? STMP_OFFSET_REG_SET : STMP_OFFSET_REG_CLR;
0442 
0443     writel(LRADC_DELAY_KICK, adc->base + (LRADC_DELAY(0) + st));
0444 
0445     return 0;
0446 }
0447 
0448 static const struct iio_trigger_ops mxs_lradc_adc_trigger_ops = {
0449     .set_trigger_state = &mxs_lradc_adc_configure_trigger,
0450 };
0451 
0452 static int mxs_lradc_adc_trigger_init(struct iio_dev *iio)
0453 {
0454     int ret;
0455     struct iio_trigger *trig;
0456     struct mxs_lradc_adc *adc = iio_priv(iio);
0457 
0458     trig = devm_iio_trigger_alloc(&iio->dev, "%s-dev%i", iio->name,
0459                       iio_device_id(iio));
0460     if (!trig)
0461         return -ENOMEM;
0462 
0463     trig->dev.parent = adc->dev;
0464     iio_trigger_set_drvdata(trig, iio);
0465     trig->ops = &mxs_lradc_adc_trigger_ops;
0466 
0467     ret = iio_trigger_register(trig);
0468     if (ret)
0469         return ret;
0470 
0471     adc->trig = trig;
0472 
0473     return 0;
0474 }
0475 
0476 static void mxs_lradc_adc_trigger_remove(struct iio_dev *iio)
0477 {
0478     struct mxs_lradc_adc *adc = iio_priv(iio);
0479 
0480     iio_trigger_unregister(adc->trig);
0481 }
0482 
0483 static int mxs_lradc_adc_buffer_preenable(struct iio_dev *iio)
0484 {
0485     struct mxs_lradc_adc *adc = iio_priv(iio);
0486     struct mxs_lradc *lradc = adc->lradc;
0487     int chan, ofs = 0;
0488     unsigned long enable = 0;
0489     u32 ctrl4_set = 0;
0490     u32 ctrl4_clr = 0;
0491     u32 ctrl1_irq = 0;
0492     const u32 chan_value = LRADC_CH_ACCUMULATE |
0493         ((LRADC_DELAY_TIMER_LOOP - 1) << LRADC_CH_NUM_SAMPLES_OFFSET);
0494 
0495     if (lradc->soc == IMX28_LRADC)
0496         writel(lradc->buffer_vchans << LRADC_CTRL1_LRADC_IRQ_EN_OFFSET,
0497                adc->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR);
0498     writel(lradc->buffer_vchans,
0499            adc->base + LRADC_CTRL0 + STMP_OFFSET_REG_CLR);
0500 
0501     for_each_set_bit(chan, iio->active_scan_mask, LRADC_MAX_TOTAL_CHANS) {
0502         ctrl4_set |= chan << LRADC_CTRL4_LRADCSELECT_OFFSET(ofs);
0503         ctrl4_clr |= LRADC_CTRL4_LRADCSELECT_MASK(ofs);
0504         ctrl1_irq |= LRADC_CTRL1_LRADC_IRQ_EN(ofs);
0505         writel(chan_value, adc->base + LRADC_CH(ofs));
0506         bitmap_set(&enable, ofs, 1);
0507         ofs++;
0508     }
0509 
0510     writel(LRADC_DELAY_TRIGGER_LRADCS_MASK | LRADC_DELAY_KICK,
0511            adc->base + LRADC_DELAY(0) + STMP_OFFSET_REG_CLR);
0512     writel(ctrl4_clr, adc->base + LRADC_CTRL4 + STMP_OFFSET_REG_CLR);
0513     writel(ctrl4_set, adc->base + LRADC_CTRL4 + STMP_OFFSET_REG_SET);
0514     writel(ctrl1_irq, adc->base + LRADC_CTRL1 + STMP_OFFSET_REG_SET);
0515     writel(enable << LRADC_DELAY_TRIGGER_LRADCS_OFFSET,
0516            adc->base + LRADC_DELAY(0) + STMP_OFFSET_REG_SET);
0517 
0518     return 0;
0519 }
0520 
0521 static int mxs_lradc_adc_buffer_postdisable(struct iio_dev *iio)
0522 {
0523     struct mxs_lradc_adc *adc = iio_priv(iio);
0524     struct mxs_lradc *lradc = adc->lradc;
0525 
0526     writel(LRADC_DELAY_TRIGGER_LRADCS_MASK | LRADC_DELAY_KICK,
0527            adc->base + LRADC_DELAY(0) + STMP_OFFSET_REG_CLR);
0528 
0529     writel(lradc->buffer_vchans,
0530            adc->base + LRADC_CTRL0 + STMP_OFFSET_REG_CLR);
0531     if (lradc->soc == IMX28_LRADC)
0532         writel(lradc->buffer_vchans << LRADC_CTRL1_LRADC_IRQ_EN_OFFSET,
0533                adc->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR);
0534 
0535     return 0;
0536 }
0537 
0538 static bool mxs_lradc_adc_validate_scan_mask(struct iio_dev *iio,
0539                          const unsigned long *mask)
0540 {
0541     struct mxs_lradc_adc *adc = iio_priv(iio);
0542     struct mxs_lradc *lradc = adc->lradc;
0543     const int map_chans = bitmap_weight(mask, LRADC_MAX_TOTAL_CHANS);
0544     int rsvd_chans = 0;
0545     unsigned long rsvd_mask = 0;
0546 
0547     if (lradc->use_touchbutton)
0548         rsvd_mask |= CHAN_MASK_TOUCHBUTTON;
0549     if (lradc->touchscreen_wire == MXS_LRADC_TOUCHSCREEN_4WIRE)
0550         rsvd_mask |= CHAN_MASK_TOUCHSCREEN_4WIRE;
0551     if (lradc->touchscreen_wire == MXS_LRADC_TOUCHSCREEN_5WIRE)
0552         rsvd_mask |= CHAN_MASK_TOUCHSCREEN_5WIRE;
0553 
0554     if (lradc->use_touchbutton)
0555         rsvd_chans++;
0556     if (lradc->touchscreen_wire)
0557         rsvd_chans += 2;
0558 
0559     /* Test for attempts to map channels with special mode of operation. */
0560     if (bitmap_intersects(mask, &rsvd_mask, LRADC_MAX_TOTAL_CHANS))
0561         return false;
0562 
0563     /* Test for attempts to map more channels then available slots. */
0564     if (map_chans + rsvd_chans > LRADC_MAX_MAPPED_CHANS)
0565         return false;
0566 
0567     return true;
0568 }
0569 
0570 static const struct iio_buffer_setup_ops mxs_lradc_adc_buffer_ops = {
0571     .preenable = &mxs_lradc_adc_buffer_preenable,
0572     .postdisable = &mxs_lradc_adc_buffer_postdisable,
0573     .validate_scan_mask = &mxs_lradc_adc_validate_scan_mask,
0574 };
0575 
0576 /* Driver initialization */
0577 #define MXS_ADC_CHAN(idx, chan_type, name) {            \
0578     .type = (chan_type),                    \
0579     .indexed = 1,                       \
0580     .scan_index = (idx),                    \
0581     .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |      \
0582                   BIT(IIO_CHAN_INFO_SCALE),     \
0583     .channel = (idx),                   \
0584     .address = (idx),                   \
0585     .scan_type = {                      \
0586         .sign = 'u',                    \
0587         .realbits = LRADC_RESOLUTION,           \
0588         .storagebits = 32,              \
0589     },                          \
0590     .datasheet_name = (name),               \
0591 }
0592 
0593 static const struct iio_chan_spec mx23_lradc_chan_spec[] = {
0594     MXS_ADC_CHAN(0, IIO_VOLTAGE, "LRADC0"),
0595     MXS_ADC_CHAN(1, IIO_VOLTAGE, "LRADC1"),
0596     MXS_ADC_CHAN(2, IIO_VOLTAGE, "LRADC2"),
0597     MXS_ADC_CHAN(3, IIO_VOLTAGE, "LRADC3"),
0598     MXS_ADC_CHAN(4, IIO_VOLTAGE, "LRADC4"),
0599     MXS_ADC_CHAN(5, IIO_VOLTAGE, "LRADC5"),
0600     MXS_ADC_CHAN(6, IIO_VOLTAGE, "VDDIO"),
0601     MXS_ADC_CHAN(7, IIO_VOLTAGE, "VBATT"),
0602     /* Combined Temperature sensors */
0603     {
0604         .type = IIO_TEMP,
0605         .indexed = 1,
0606         .scan_index = 8,
0607         .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
0608                       BIT(IIO_CHAN_INFO_OFFSET) |
0609                       BIT(IIO_CHAN_INFO_SCALE),
0610         .channel = 8,
0611         .scan_type = {.sign = 'u', .realbits = 18, .storagebits = 32,},
0612         .datasheet_name = "TEMP_DIE",
0613     },
0614     /* Hidden channel to keep indexes */
0615     {
0616         .type = IIO_TEMP,
0617         .indexed = 1,
0618         .scan_index = -1,
0619         .channel = 9,
0620     },
0621     MXS_ADC_CHAN(10, IIO_VOLTAGE, NULL),
0622     MXS_ADC_CHAN(11, IIO_VOLTAGE, NULL),
0623     MXS_ADC_CHAN(12, IIO_VOLTAGE, "USB_DP"),
0624     MXS_ADC_CHAN(13, IIO_VOLTAGE, "USB_DN"),
0625     MXS_ADC_CHAN(14, IIO_VOLTAGE, "VBG"),
0626     MXS_ADC_CHAN(15, IIO_VOLTAGE, "VDD5V"),
0627 };
0628 
0629 static const struct iio_chan_spec mx28_lradc_chan_spec[] = {
0630     MXS_ADC_CHAN(0, IIO_VOLTAGE, "LRADC0"),
0631     MXS_ADC_CHAN(1, IIO_VOLTAGE, "LRADC1"),
0632     MXS_ADC_CHAN(2, IIO_VOLTAGE, "LRADC2"),
0633     MXS_ADC_CHAN(3, IIO_VOLTAGE, "LRADC3"),
0634     MXS_ADC_CHAN(4, IIO_VOLTAGE, "LRADC4"),
0635     MXS_ADC_CHAN(5, IIO_VOLTAGE, "LRADC5"),
0636     MXS_ADC_CHAN(6, IIO_VOLTAGE, "LRADC6"),
0637     MXS_ADC_CHAN(7, IIO_VOLTAGE, "VBATT"),
0638     /* Combined Temperature sensors */
0639     {
0640         .type = IIO_TEMP,
0641         .indexed = 1,
0642         .scan_index = 8,
0643         .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
0644                       BIT(IIO_CHAN_INFO_OFFSET) |
0645                       BIT(IIO_CHAN_INFO_SCALE),
0646         .channel = 8,
0647         .scan_type = {.sign = 'u', .realbits = 18, .storagebits = 32,},
0648         .datasheet_name = "TEMP_DIE",
0649     },
0650     /* Hidden channel to keep indexes */
0651     {
0652         .type = IIO_TEMP,
0653         .indexed = 1,
0654         .scan_index = -1,
0655         .channel = 9,
0656     },
0657     MXS_ADC_CHAN(10, IIO_VOLTAGE, "VDDIO"),
0658     MXS_ADC_CHAN(11, IIO_VOLTAGE, "VTH"),
0659     MXS_ADC_CHAN(12, IIO_VOLTAGE, "VDDA"),
0660     MXS_ADC_CHAN(13, IIO_VOLTAGE, "VDDD"),
0661     MXS_ADC_CHAN(14, IIO_VOLTAGE, "VBG"),
0662     MXS_ADC_CHAN(15, IIO_VOLTAGE, "VDD5V"),
0663 };
0664 
0665 static void mxs_lradc_adc_hw_init(struct mxs_lradc_adc *adc)
0666 {
0667     /* The ADC always uses DELAY CHANNEL 0. */
0668     const u32 adc_cfg =
0669         (1 << (LRADC_DELAY_TRIGGER_DELAYS_OFFSET + 0)) |
0670         (LRADC_DELAY_TIMER_PER << LRADC_DELAY_DELAY_OFFSET);
0671 
0672     /* Configure DELAY CHANNEL 0 for generic ADC sampling. */
0673     writel(adc_cfg, adc->base + LRADC_DELAY(0));
0674 
0675     /*
0676      * Start internal temperature sensing by clearing bit
0677      * HW_LRADC_CTRL2_TEMPSENSE_PWD. This bit can be left cleared
0678      * after power up.
0679      */
0680     writel(0, adc->base + LRADC_CTRL2);
0681 }
0682 
0683 static void mxs_lradc_adc_hw_stop(struct mxs_lradc_adc *adc)
0684 {
0685     writel(0, adc->base + LRADC_DELAY(0));
0686 }
0687 
0688 static int mxs_lradc_adc_probe(struct platform_device *pdev)
0689 {
0690     struct device *dev = &pdev->dev;
0691     struct mxs_lradc *lradc = dev_get_drvdata(dev->parent);
0692     struct mxs_lradc_adc *adc;
0693     struct iio_dev *iio;
0694     struct resource *iores;
0695     int ret, irq, virq, i, s, n;
0696     u64 scale_uv;
0697     const char **irq_name;
0698 
0699     /* Allocate the IIO device. */
0700     iio = devm_iio_device_alloc(dev, sizeof(*adc));
0701     if (!iio) {
0702         dev_err(dev, "Failed to allocate IIO device\n");
0703         return -ENOMEM;
0704     }
0705 
0706     adc = iio_priv(iio);
0707     adc->lradc = lradc;
0708     adc->dev = dev;
0709 
0710     iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
0711     if (!iores)
0712         return -EINVAL;
0713 
0714     adc->base = devm_ioremap(dev, iores->start, resource_size(iores));
0715     if (!adc->base)
0716         return -ENOMEM;
0717 
0718     init_completion(&adc->completion);
0719     spin_lock_init(&adc->lock);
0720 
0721     platform_set_drvdata(pdev, iio);
0722 
0723     iio->name = pdev->name;
0724     iio->dev.of_node = dev->parent->of_node;
0725     iio->info = &mxs_lradc_adc_iio_info;
0726     iio->modes = INDIO_DIRECT_MODE;
0727     iio->masklength = LRADC_MAX_TOTAL_CHANS;
0728 
0729     if (lradc->soc == IMX23_LRADC) {
0730         iio->channels = mx23_lradc_chan_spec;
0731         iio->num_channels = ARRAY_SIZE(mx23_lradc_chan_spec);
0732         irq_name = mx23_lradc_adc_irq_names;
0733         n = ARRAY_SIZE(mx23_lradc_adc_irq_names);
0734     } else {
0735         iio->channels = mx28_lradc_chan_spec;
0736         iio->num_channels = ARRAY_SIZE(mx28_lradc_chan_spec);
0737         irq_name = mx28_lradc_adc_irq_names;
0738         n = ARRAY_SIZE(mx28_lradc_adc_irq_names);
0739     }
0740 
0741     ret = stmp_reset_block(adc->base);
0742     if (ret)
0743         return ret;
0744 
0745     for (i = 0; i < n; i++) {
0746         irq = platform_get_irq_byname(pdev, irq_name[i]);
0747         if (irq < 0)
0748             return irq;
0749 
0750         virq = irq_of_parse_and_map(dev->parent->of_node, irq);
0751 
0752         ret = devm_request_irq(dev, virq, mxs_lradc_adc_handle_irq,
0753                        0, irq_name[i], iio);
0754         if (ret)
0755             return ret;
0756     }
0757 
0758     ret = mxs_lradc_adc_trigger_init(iio);
0759     if (ret)
0760         goto err_trig;
0761 
0762     ret = iio_triggered_buffer_setup(iio, &iio_pollfunc_store_time,
0763                      &mxs_lradc_adc_trigger_handler,
0764                      &mxs_lradc_adc_buffer_ops);
0765     if (ret)
0766         return ret;
0767 
0768     adc->vref_mv = mxs_lradc_adc_vref_mv[lradc->soc];
0769 
0770     /* Populate available ADC input ranges */
0771     for (i = 0; i < LRADC_MAX_TOTAL_CHANS; i++) {
0772         for (s = 0; s < ARRAY_SIZE(adc->scale_avail[i]); s++) {
0773             /*
0774              * [s=0] = optional divider by two disabled (default)
0775              * [s=1] = optional divider by two enabled
0776              *
0777              * The scale is calculated by doing:
0778              *   Vref >> (realbits - s)
0779              * which multiplies by two on the second component
0780              * of the array.
0781              */
0782             scale_uv = ((u64)adc->vref_mv[i] * 100000000) >>
0783                    (LRADC_RESOLUTION - s);
0784             adc->scale_avail[i][s].nano =
0785                     do_div(scale_uv, 100000000) * 10;
0786             adc->scale_avail[i][s].integer = scale_uv;
0787         }
0788     }
0789 
0790     /* Configure the hardware. */
0791     mxs_lradc_adc_hw_init(adc);
0792 
0793     /* Register IIO device. */
0794     ret = iio_device_register(iio);
0795     if (ret) {
0796         dev_err(dev, "Failed to register IIO device\n");
0797         goto err_dev;
0798     }
0799 
0800     return 0;
0801 
0802 err_dev:
0803     mxs_lradc_adc_hw_stop(adc);
0804     mxs_lradc_adc_trigger_remove(iio);
0805 err_trig:
0806     iio_triggered_buffer_cleanup(iio);
0807     return ret;
0808 }
0809 
0810 static int mxs_lradc_adc_remove(struct platform_device *pdev)
0811 {
0812     struct iio_dev *iio = platform_get_drvdata(pdev);
0813     struct mxs_lradc_adc *adc = iio_priv(iio);
0814 
0815     iio_device_unregister(iio);
0816     mxs_lradc_adc_hw_stop(adc);
0817     mxs_lradc_adc_trigger_remove(iio);
0818     iio_triggered_buffer_cleanup(iio);
0819 
0820     return 0;
0821 }
0822 
0823 static struct platform_driver mxs_lradc_adc_driver = {
0824     .driver = {
0825         .name   = "mxs-lradc-adc",
0826     },
0827     .probe  = mxs_lradc_adc_probe,
0828     .remove = mxs_lradc_adc_remove,
0829 };
0830 module_platform_driver(mxs_lradc_adc_driver);
0831 
0832 MODULE_AUTHOR("Marek Vasut <marex@denx.de>");
0833 MODULE_DESCRIPTION("Freescale MXS LRADC driver general purpose ADC driver");
0834 MODULE_LICENSE("GPL");
0835 MODULE_ALIAS("platform:mxs-lradc-adc");
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