iio/adc/mcp3422.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * mcp3422.c - driver for the Microchip mcp3421/2/3/4/5/6/7/8 chip family
0004  *
0005  * Copyright (C) 2013, Angelo Compagnucci
0006  * Author: Angelo Compagnucci <angelo.compagnucci@gmail.com>
0007  *
0008  * Datasheet: http://ww1.microchip.com/downloads/en/devicedoc/22088b.pdf
0009  *            https://ww1.microchip.com/downloads/en/DeviceDoc/22226a.pdf
0010  *            https://ww1.microchip.com/downloads/en/DeviceDoc/22072b.pdf
0011  *
0012  * This driver exports the value of analog input voltage to sysfs, the
0013  * voltage unit is nV.
0014  */
0015
0016 #include <linux/err.h>
0017 #include <linux/i2c.h>
0018 #include <linux/module.h>
0019 #include <linux/mod_devicetable.h>
0020 #include <linux/delay.h>
0021 #include <linux/sysfs.h>
0022 #include <asm/unaligned.h>
0023
0024 #include <linux/iio/iio.h>
0025 #include <linux/iio/sysfs.h>
0026
0027 /* Masks */
0028 #define MCP3422_CHANNEL_MASK    0x60
0029 #define MCP3422_PGA_MASK    0x03
0030 #define MCP3422_SRATE_MASK  0x0C
0031 #define MCP3422_SRATE_240   0x0
0032 #define MCP3422_SRATE_60    0x1
0033 #define MCP3422_SRATE_15    0x2
0034 #define MCP3422_SRATE_3 0x3
0035 #define MCP3422_PGA_1   0
0036 #define MCP3422_PGA_2   1
0037 #define MCP3422_PGA_4   2
0038 #define MCP3422_PGA_8   3
0039 #define MCP3422_CONT_SAMPLING   0x10
0040
0041 #define MCP3422_CHANNEL(config) (((config) & MCP3422_CHANNEL_MASK) >> 5)
0042 #define MCP3422_PGA(config) ((config) & MCP3422_PGA_MASK)
0043 #define MCP3422_SAMPLE_RATE(config) (((config) & MCP3422_SRATE_MASK) >> 2)
0044
0045 #define MCP3422_CHANNEL_VALUE(value) (((value) << 5) & MCP3422_CHANNEL_MASK)
0046 #define MCP3422_PGA_VALUE(value) ((value) & MCP3422_PGA_MASK)
0047 #define MCP3422_SAMPLE_RATE_VALUE(value) ((value << 2) & MCP3422_SRATE_MASK)
0048
0049 #define MCP3422_CHAN(_index) \
0050     { \
0051         .type = IIO_VOLTAGE, \
0052         .indexed = 1, \
0053         .channel = _index, \
0054         .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) \
0055                 | BIT(IIO_CHAN_INFO_SCALE), \
0056         .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SAMP_FREQ), \
0057     }
0058
0059 static const int mcp3422_scales[4][4] = {
0060     { 1000000, 500000, 250000, 125000 },
0061     { 250000,  125000, 62500,  31250  },
0062     { 62500,   31250,  15625,  7812   },
0063     { 15625,   7812,   3906,   1953   } };
0064
0065 /* Constant msleep times for data acquisitions */
0066 static const int mcp3422_read_times[4] = {
0067     [MCP3422_SRATE_240] = 1000 / 240,
0068     [MCP3422_SRATE_60] = 1000 / 60,
0069     [MCP3422_SRATE_15] = 1000 / 15,
0070     [MCP3422_SRATE_3] = 1000 / 3 };
0071
0072 /* sample rates to integer conversion table */
0073 static const int mcp3422_sample_rates[4] = {
0074     [MCP3422_SRATE_240] = 240,
0075     [MCP3422_SRATE_60] = 60,
0076     [MCP3422_SRATE_15] = 15,
0077     [MCP3422_SRATE_3] = 3 };
0078
0079 /* sample rates to sign extension table */
0080 static const int mcp3422_sign_extend[4] = {
0081     [MCP3422_SRATE_240] = 11,
0082     [MCP3422_SRATE_60] = 13,
0083     [MCP3422_SRATE_15] = 15,
0084     [MCP3422_SRATE_3] = 17 };
0085
0086 /* Client data (each client gets its own) */
0087 struct mcp3422 {
0088     struct i2c_client *i2c;
0089     u8 id;
0090     u8 config;
0091     u8 pga[4];
0092     struct mutex lock;
0093 };
0094
0095 static int mcp3422_update_config(struct mcp3422 *adc, u8 newconfig)
0096 {
0097     int ret;
0098
0099     ret = i2c_master_send(adc->i2c, &newconfig, 1);
0100     if (ret > 0) {
0101         adc->config = newconfig;
0102         ret = 0;
0103     }
0104
0105     return ret;
0106 }
0107
0108 static int mcp3422_read(struct mcp3422 *adc, int *value, u8 *config)
0109 {
0110     int ret = 0;
0111     u8 sample_rate = MCP3422_SAMPLE_RATE(adc->config);
0112     u8 buf[4] = {0, 0, 0, 0};
0113     u32 temp;
0114
0115     if (sample_rate == MCP3422_SRATE_3) {
0116         ret = i2c_master_recv(adc->i2c, buf, 4);
0117         temp = get_unaligned_be24(&buf[0]);
0118         *config = buf[3];
0119     } else {
0120         ret = i2c_master_recv(adc->i2c, buf, 3);
0121         temp = get_unaligned_be16(&buf[0]);
0122         *config = buf[2];
0123     }
0124
0125     *value = sign_extend32(temp, mcp3422_sign_extend[sample_rate]);
0126
0127     return ret;
0128 }
0129
0130 static int mcp3422_read_channel(struct mcp3422 *adc,
0131                 struct iio_chan_spec const *channel, int *value)
0132 {
0133     int ret;
0134     u8 config;
0135     u8 req_channel = channel->channel;
0136
0137     mutex_lock(&adc->lock);
0138
0139     if (req_channel != MCP3422_CHANNEL(adc->config)) {
0140         config = adc->config;
0141         config &= ~MCP3422_CHANNEL_MASK;
0142         config |= MCP3422_CHANNEL_VALUE(req_channel);
0143         config &= ~MCP3422_PGA_MASK;
0144         config |= MCP3422_PGA_VALUE(adc->pga[req_channel]);
0145         ret = mcp3422_update_config(adc, config);
0146         if (ret < 0) {
0147             mutex_unlock(&adc->lock);
0148             return ret;
0149         }
0150         msleep(mcp3422_read_times[MCP3422_SAMPLE_RATE(adc->config)]);
0151     }
0152
0153     ret = mcp3422_read(adc, value, &config);
0154
0155     mutex_unlock(&adc->lock);
0156
0157     return ret;
0158 }
0159
0160 static int mcp3422_read_raw(struct iio_dev *iio,
0161             struct iio_chan_spec const *channel, int *val1,
0162             int *val2, long mask)
0163 {
0164     struct mcp3422 *adc = iio_priv(iio);
0165     int err;
0166
0167     u8 sample_rate = MCP3422_SAMPLE_RATE(adc->config);
0168     u8 pga       = MCP3422_PGA(adc->config);
0169
0170     switch (mask) {
0171     case IIO_CHAN_INFO_RAW:
0172         err = mcp3422_read_channel(adc, channel, val1);
0173         if (err < 0)
0174             return -EINVAL;
0175         return IIO_VAL_INT;
0176
0177     case IIO_CHAN_INFO_SCALE:
0178
0179         *val1 = 0;
0180         *val2 = mcp3422_scales[sample_rate][pga];
0181         return IIO_VAL_INT_PLUS_NANO;
0182
0183     case IIO_CHAN_INFO_SAMP_FREQ:
0184         *val1 = mcp3422_sample_rates[MCP3422_SAMPLE_RATE(adc->config)];
0185         return IIO_VAL_INT;
0186
0187     default:
0188         break;
0189     }
0190
0191     return -EINVAL;
0192 }
0193
0194 static int mcp3422_write_raw(struct iio_dev *iio,
0195             struct iio_chan_spec const *channel, int val1,
0196             int val2, long mask)
0197 {
0198     struct mcp3422 *adc = iio_priv(iio);
0199     u8 temp;
0200     u8 config = adc->config;
0201     u8 req_channel = channel->channel;
0202     u8 sample_rate = MCP3422_SAMPLE_RATE(config);
0203     u8 i;
0204
0205     switch (mask) {
0206     case IIO_CHAN_INFO_SCALE:
0207         if (val1 != 0)
0208             return -EINVAL;
0209
0210         for (i = 0; i < ARRAY_SIZE(mcp3422_scales[0]); i++) {
0211             if (val2 == mcp3422_scales[sample_rate][i]) {
0212                 adc->pga[req_channel] = i;
0213
0214                 config &= ~MCP3422_CHANNEL_MASK;
0215                 config |= MCP3422_CHANNEL_VALUE(req_channel);
0216                 config &= ~MCP3422_PGA_MASK;
0217                 config |= MCP3422_PGA_VALUE(adc->pga[req_channel]);
0218
0219                 return mcp3422_update_config(adc, config);
0220             }
0221         }
0222         return -EINVAL;
0223
0224     case IIO_CHAN_INFO_SAMP_FREQ:
0225         switch (val1) {
0226         case 240:
0227             temp = MCP3422_SRATE_240;
0228             break;
0229         case 60:
0230             temp = MCP3422_SRATE_60;
0231             break;
0232         case 15:
0233             temp = MCP3422_SRATE_15;
0234             break;
0235         case 3:
0236             if (adc->id > 4)
0237                 return -EINVAL;
0238             temp = MCP3422_SRATE_3;
0239             break;
0240         default:
0241             return -EINVAL;
0242         }
0243
0244         config &= ~MCP3422_CHANNEL_MASK;
0245         config |= MCP3422_CHANNEL_VALUE(req_channel);
0246         config &= ~MCP3422_SRATE_MASK;
0247         config |= MCP3422_SAMPLE_RATE_VALUE(temp);
0248
0249         return mcp3422_update_config(adc, config);
0250
0251     default:
0252         break;
0253     }
0254
0255     return -EINVAL;
0256 }
0257
0258 static int mcp3422_write_raw_get_fmt(struct iio_dev *indio_dev,
0259         struct iio_chan_spec const *chan, long mask)
0260 {
0261     switch (mask) {
0262     case IIO_CHAN_INFO_SCALE:
0263         return IIO_VAL_INT_PLUS_NANO;
0264     case IIO_CHAN_INFO_SAMP_FREQ:
0265         return IIO_VAL_INT_PLUS_MICRO;
0266     default:
0267         return -EINVAL;
0268     }
0269 }
0270
0271 static ssize_t mcp3422_show_samp_freqs(struct device *dev,
0272         struct device_attribute *attr, char *buf)
0273 {
0274     struct mcp3422 *adc = iio_priv(dev_to_iio_dev(dev));
0275
0276     if (adc->id > 4)
0277         return sprintf(buf, "240 60 15\n");
0278
0279     return sprintf(buf, "240 60 15 3\n");
0280 }
0281
0282 static ssize_t mcp3422_show_scales(struct device *dev,
0283         struct device_attribute *attr, char *buf)
0284 {
0285     struct mcp3422 *adc = iio_priv(dev_to_iio_dev(dev));
0286     u8 sample_rate = MCP3422_SAMPLE_RATE(adc->config);
0287
0288     return sprintf(buf, "0.%09u 0.%09u 0.%09u 0.%09u\n",
0289         mcp3422_scales[sample_rate][0],
0290         mcp3422_scales[sample_rate][1],
0291         mcp3422_scales[sample_rate][2],
0292         mcp3422_scales[sample_rate][3]);
0293 }
0294
0295 static IIO_DEVICE_ATTR(sampling_frequency_available, S_IRUGO,
0296         mcp3422_show_samp_freqs, NULL, 0);
0297 static IIO_DEVICE_ATTR(in_voltage_scale_available, S_IRUGO,
0298         mcp3422_show_scales, NULL, 0);
0299
0300 static struct attribute *mcp3422_attributes[] = {
0301     &iio_dev_attr_sampling_frequency_available.dev_attr.attr,
0302     &iio_dev_attr_in_voltage_scale_available.dev_attr.attr,
0303     NULL,
0304 };
0305
0306 static const struct attribute_group mcp3422_attribute_group = {
0307     .attrs = mcp3422_attributes,
0308 };
0309
0310 static const struct iio_chan_spec mcp3421_channels[] = {
0311     MCP3422_CHAN(0),
0312 };
0313
0314 static const struct iio_chan_spec mcp3422_channels[] = {
0315     MCP3422_CHAN(0),
0316     MCP3422_CHAN(1),
0317 };
0318
0319 static const struct iio_chan_spec mcp3424_channels[] = {
0320     MCP3422_CHAN(0),
0321     MCP3422_CHAN(1),
0322     MCP3422_CHAN(2),
0323     MCP3422_CHAN(3),
0324 };
0325
0326 static const struct iio_info mcp3422_info = {
0327     .read_raw = mcp3422_read_raw,
0328     .write_raw = mcp3422_write_raw,
0329     .write_raw_get_fmt = mcp3422_write_raw_get_fmt,
0330     .attrs = &mcp3422_attribute_group,
0331 };
0332
0333 static int mcp3422_probe(struct i2c_client *client,
0334              const struct i2c_device_id *id)
0335 {
0336     struct iio_dev *indio_dev;
0337     struct mcp3422 *adc;
0338     int err;
0339     u8 config;
0340
0341     if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C))
0342         return -EOPNOTSUPP;
0343
0344     indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*adc));
0345     if (!indio_dev)
0346         return -ENOMEM;
0347
0348     adc = iio_priv(indio_dev);
0349     adc->i2c = client;
0350     adc->id = (u8)(id->driver_data);
0351
0352     mutex_init(&adc->lock);
0353
0354     indio_dev->name = dev_name(&client->dev);
0355     indio_dev->modes = INDIO_DIRECT_MODE;
0356     indio_dev->info = &mcp3422_info;
0357
0358     switch (adc->id) {
0359     case 1:
0360     case 5:
0361         indio_dev->channels = mcp3421_channels;
0362         indio_dev->num_channels = ARRAY_SIZE(mcp3421_channels);
0363         break;
0364     case 2:
0365     case 3:
0366     case 6:
0367     case 7:
0368         indio_dev->channels = mcp3422_channels;
0369         indio_dev->num_channels = ARRAY_SIZE(mcp3422_channels);
0370         break;
0371     case 4:
0372     case 8:
0373         indio_dev->channels = mcp3424_channels;
0374         indio_dev->num_channels = ARRAY_SIZE(mcp3424_channels);
0375         break;
0376     }
0377
0378     /* meaningful default configuration */
0379     config = (MCP3422_CONT_SAMPLING
0380         | MCP3422_CHANNEL_VALUE(0)
0381         | MCP3422_PGA_VALUE(MCP3422_PGA_1)
0382         | MCP3422_SAMPLE_RATE_VALUE(MCP3422_SRATE_240));
0383     err = mcp3422_update_config(adc, config);
0384     if (err < 0)
0385         return err;
0386
0387     err = devm_iio_device_register(&client->dev, indio_dev);
0388     if (err < 0)
0389         return err;
0390
0391     i2c_set_clientdata(client, indio_dev);
0392
0393     return 0;
0394 }
0395
0396 static const struct i2c_device_id mcp3422_id[] = {
0397     { "mcp3421", 1 },
0398     { "mcp3422", 2 },
0399     { "mcp3423", 3 },
0400     { "mcp3424", 4 },
0401     { "mcp3425", 5 },
0402     { "mcp3426", 6 },
0403     { "mcp3427", 7 },
0404     { "mcp3428", 8 },
0405     { }
0406 };
0407 MODULE_DEVICE_TABLE(i2c, mcp3422_id);
0408
0409 static const struct of_device_id mcp3422_of_match[] = {
0410     { .compatible = "mcp3422" },
0411     { }
0412 };
0413 MODULE_DEVICE_TABLE(of, mcp3422_of_match);
0414
0415 static struct i2c_driver mcp3422_driver = {
0416     .driver = {
0417         .name = "mcp3422",
0418         .of_match_table = mcp3422_of_match,
0419     },
0420     .probe = mcp3422_probe,
0421     .id_table = mcp3422_id,
0422 };
0423 module_i2c_driver(mcp3422_driver);
0424
0425 MODULE_AUTHOR("Angelo Compagnucci <angelo.compagnucci@gmail.com>");
0426 MODULE_DESCRIPTION("Microchip mcp3421/2/3/4/5/6/7/8 driver");
0427 MODULE_LICENSE("GPL v2");