iio/adc/mcp320x.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (C) 2013 Oskar Andero <oskar.andero@gmail.com>
0004  * Copyright (C) 2014 Rose Technology
0005  *     Allan Bendorff Jensen <abj@rosetechnology.dk>
0006  *     Soren Andersen <san@rosetechnology.dk>
0007  *
0008  * Driver for following ADC chips from Microchip Technology's:
0009  * 10 Bit converter
0010  * MCP3001
0011  * MCP3002
0012  * MCP3004
0013  * MCP3008
0014  * ------------
0015  * 12 bit converter
0016  * MCP3201
0017  * MCP3202
0018  * MCP3204
0019  * MCP3208
0020  * ------------
0021  * 13 bit converter
0022  * MCP3301
0023  * ------------
0024  * 22 bit converter
0025  * MCP3550
0026  * MCP3551
0027  * MCP3553
0028  *
0029  * Datasheet can be found here:
0030  * https://ww1.microchip.com/downloads/en/DeviceDoc/21293C.pdf  mcp3001
0031  * https://ww1.microchip.com/downloads/en/DeviceDoc/21294E.pdf  mcp3002
0032  * https://ww1.microchip.com/downloads/en/DeviceDoc/21295d.pdf  mcp3004/08
0033  * http://ww1.microchip.com/downloads/en/DeviceDoc/21290D.pdf  mcp3201
0034  * http://ww1.microchip.com/downloads/en/DeviceDoc/21034D.pdf  mcp3202
0035  * http://ww1.microchip.com/downloads/en/DeviceDoc/21298c.pdf  mcp3204/08
0036  * https://ww1.microchip.com/downloads/en/DeviceDoc/21700E.pdf  mcp3301
0037  * http://ww1.microchip.com/downloads/en/DeviceDoc/21950D.pdf  mcp3550/1/3
0038  */
0039
0040 #include <linux/err.h>
0041 #include <linux/delay.h>
0042 #include <linux/spi/spi.h>
0043 #include <linux/module.h>
0044 #include <linux/mod_devicetable.h>
0045 #include <linux/iio/iio.h>
0046 #include <linux/regulator/consumer.h>
0047
0048 enum {
0049     mcp3001,
0050     mcp3002,
0051     mcp3004,
0052     mcp3008,
0053     mcp3201,
0054     mcp3202,
0055     mcp3204,
0056     mcp3208,
0057     mcp3301,
0058     mcp3550_50,
0059     mcp3550_60,
0060     mcp3551,
0061     mcp3553,
0062 };
0063
0064 struct mcp320x_chip_info {
0065     const struct iio_chan_spec *channels;
0066     unsigned int num_channels;
0067     unsigned int resolution;
0068     unsigned int conv_time; /* usec */
0069 };
0070
0071 /**
0072  * struct mcp320x - Microchip SPI ADC instance
0073  * @spi: SPI slave (parent of the IIO device)
0074  * @msg: SPI message to select a channel and receive a value from the ADC
0075  * @transfer: SPI transfers used by @msg
0076  * @start_conv_msg: SPI message to start a conversion by briefly asserting CS
0077  * @start_conv_transfer: SPI transfer used by @start_conv_msg
0078  * @reg: regulator generating Vref
0079  * @lock: protects read sequences
0080  * @chip_info: ADC properties
0081  * @tx_buf: buffer for @transfer[0] (not used on single-channel converters)
0082  * @rx_buf: buffer for @transfer[1]
0083  */
0084 struct mcp320x {
0085     struct spi_device *spi;
0086     struct spi_message msg;
0087     struct spi_transfer transfer[2];
0088     struct spi_message start_conv_msg;
0089     struct spi_transfer start_conv_transfer;
0090
0091     struct regulator *reg;
0092     struct mutex lock;
0093     const struct mcp320x_chip_info *chip_info;
0094
0095     u8 tx_buf __aligned(IIO_DMA_MINALIGN);
0096     u8 rx_buf[4];
0097 };
0098
0099 static int mcp320x_channel_to_tx_data(int device_index,
0100             const unsigned int channel, bool differential)
0101 {
0102     int start_bit = 1;
0103
0104     switch (device_index) {
0105     case mcp3002:
0106     case mcp3202:
0107         return ((start_bit << 4) | (!differential << 3) |
0108                             (channel << 2));
0109     case mcp3004:
0110     case mcp3204:
0111     case mcp3008:
0112     case mcp3208:
0113         return ((start_bit << 6) | (!differential << 5) |
0114                             (channel << 2));
0115     default:
0116         return -EINVAL;
0117     }
0118 }
0119
0120 static int mcp320x_adc_conversion(struct mcp320x *adc, u8 channel,
0121                   bool differential, int device_index, int *val)
0122 {
0123     int ret;
0124
0125     if (adc->chip_info->conv_time) {
0126         ret = spi_sync(adc->spi, &adc->start_conv_msg);
0127         if (ret < 0)
0128             return ret;
0129
0130         usleep_range(adc->chip_info->conv_time,
0131                  adc->chip_info->conv_time + 100);
0132     }
0133
0134     memset(&adc->rx_buf, 0, sizeof(adc->rx_buf));
0135     if (adc->chip_info->num_channels > 1)
0136         adc->tx_buf = mcp320x_channel_to_tx_data(device_index, channel,
0137                              differential);
0138
0139     ret = spi_sync(adc->spi, &adc->msg);
0140     if (ret < 0)
0141         return ret;
0142
0143     switch (device_index) {
0144     case mcp3001:
0145         *val = (adc->rx_buf[0] << 5 | adc->rx_buf[1] >> 3);
0146         return 0;
0147     case mcp3002:
0148     case mcp3004:
0149     case mcp3008:
0150         *val = (adc->rx_buf[0] << 2 | adc->rx_buf[1] >> 6);
0151         return 0;
0152     case mcp3201:
0153         *val = (adc->rx_buf[0] << 7 | adc->rx_buf[1] >> 1);
0154         return 0;
0155     case mcp3202:
0156     case mcp3204:
0157     case mcp3208:
0158         *val = (adc->rx_buf[0] << 4 | adc->rx_buf[1] >> 4);
0159         return 0;
0160     case mcp3301:
0161         *val = sign_extend32((adc->rx_buf[0] & 0x1f) << 8
0162                     | adc->rx_buf[1], 12);
0163         return 0;
0164     case mcp3550_50:
0165     case mcp3550_60:
0166     case mcp3551:
0167     case mcp3553: {
0168         u32 raw = be32_to_cpup((__be32 *)adc->rx_buf);
0169
0170         if (!(adc->spi->mode & SPI_CPOL))
0171             raw <<= 1; /* strip Data Ready bit in SPI mode 0,0 */
0172
0173         /*
0174          * If the input is within -vref and vref, bit 21 is the sign.
0175          * Up to 12% overrange or underrange are allowed, in which case
0176          * bit 23 is the sign and bit 0 to 21 is the value.
0177          */
0178         raw >>= 8;
0179         if (raw & BIT(22) && raw & BIT(23))
0180             return -EIO; /* cannot have overrange AND underrange */
0181         else if (raw & BIT(22))
0182             raw &= ~BIT(22); /* overrange */
0183         else if (raw & BIT(23) || raw & BIT(21))
0184             raw |= GENMASK(31, 22); /* underrange or negative */
0185
0186         *val = (s32)raw;
0187         return 0;
0188         }
0189     default:
0190         return -EINVAL;
0191     }
0192 }
0193
0194 static int mcp320x_read_raw(struct iio_dev *indio_dev,
0195                 struct iio_chan_spec const *channel, int *val,
0196                 int *val2, long mask)
0197 {
0198     struct mcp320x *adc = iio_priv(indio_dev);
0199     int ret = -EINVAL;
0200     int device_index = 0;
0201
0202     mutex_lock(&adc->lock);
0203
0204     device_index = spi_get_device_id(adc->spi)->driver_data;
0205
0206     switch (mask) {
0207     case IIO_CHAN_INFO_RAW:
0208         ret = mcp320x_adc_conversion(adc, channel->address,
0209             channel->differential, device_index, val);
0210         if (ret < 0)
0211             goto out;
0212
0213         ret = IIO_VAL_INT;
0214         break;
0215
0216     case IIO_CHAN_INFO_SCALE:
0217         ret = regulator_get_voltage(adc->reg);
0218         if (ret < 0)
0219             goto out;
0220
0221         /* convert regulator output voltage to mV */
0222         *val = ret / 1000;
0223         *val2 = adc->chip_info->resolution;
0224         ret = IIO_VAL_FRACTIONAL_LOG2;
0225         break;
0226     }
0227
0228 out:
0229     mutex_unlock(&adc->lock);
0230
0231     return ret;
0232 }
0233
0234 #define MCP320X_VOLTAGE_CHANNEL(num)                \
0235     {                           \
0236         .type = IIO_VOLTAGE,                \
0237         .indexed = 1,                   \
0238         .channel = (num),               \
0239         .address = (num),               \
0240         .info_mask_separate = BIT(IIO_CHAN_INFO_RAW),   \
0241         .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) \
0242     }
0243
0244 #define MCP320X_VOLTAGE_CHANNEL_DIFF(chan1, chan2)      \
0245     {                           \
0246         .type = IIO_VOLTAGE,                \
0247         .indexed = 1,                   \
0248         .channel = (chan1),             \
0249         .channel2 = (chan2),                \
0250         .address = (chan1),             \
0251         .differential = 1,              \
0252         .info_mask_separate = BIT(IIO_CHAN_INFO_RAW),   \
0253         .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) \
0254     }
0255
0256 static const struct iio_chan_spec mcp3201_channels[] = {
0257     MCP320X_VOLTAGE_CHANNEL_DIFF(0, 1),
0258 };
0259
0260 static const struct iio_chan_spec mcp3202_channels[] = {
0261     MCP320X_VOLTAGE_CHANNEL(0),
0262     MCP320X_VOLTAGE_CHANNEL(1),
0263     MCP320X_VOLTAGE_CHANNEL_DIFF(0, 1),
0264     MCP320X_VOLTAGE_CHANNEL_DIFF(1, 0),
0265 };
0266
0267 static const struct iio_chan_spec mcp3204_channels[] = {
0268     MCP320X_VOLTAGE_CHANNEL(0),
0269     MCP320X_VOLTAGE_CHANNEL(1),
0270     MCP320X_VOLTAGE_CHANNEL(2),
0271     MCP320X_VOLTAGE_CHANNEL(3),
0272     MCP320X_VOLTAGE_CHANNEL_DIFF(0, 1),
0273     MCP320X_VOLTAGE_CHANNEL_DIFF(1, 0),
0274     MCP320X_VOLTAGE_CHANNEL_DIFF(2, 3),
0275     MCP320X_VOLTAGE_CHANNEL_DIFF(3, 2),
0276 };
0277
0278 static const struct iio_chan_spec mcp3208_channels[] = {
0279     MCP320X_VOLTAGE_CHANNEL(0),
0280     MCP320X_VOLTAGE_CHANNEL(1),
0281     MCP320X_VOLTAGE_CHANNEL(2),
0282     MCP320X_VOLTAGE_CHANNEL(3),
0283     MCP320X_VOLTAGE_CHANNEL(4),
0284     MCP320X_VOLTAGE_CHANNEL(5),
0285     MCP320X_VOLTAGE_CHANNEL(6),
0286     MCP320X_VOLTAGE_CHANNEL(7),
0287     MCP320X_VOLTAGE_CHANNEL_DIFF(0, 1),
0288     MCP320X_VOLTAGE_CHANNEL_DIFF(1, 0),
0289     MCP320X_VOLTAGE_CHANNEL_DIFF(2, 3),
0290     MCP320X_VOLTAGE_CHANNEL_DIFF(3, 2),
0291     MCP320X_VOLTAGE_CHANNEL_DIFF(4, 5),
0292     MCP320X_VOLTAGE_CHANNEL_DIFF(5, 4),
0293     MCP320X_VOLTAGE_CHANNEL_DIFF(6, 7),
0294     MCP320X_VOLTAGE_CHANNEL_DIFF(7, 6),
0295 };
0296
0297 static const struct iio_info mcp320x_info = {
0298     .read_raw = mcp320x_read_raw,
0299 };
0300
0301 static const struct mcp320x_chip_info mcp320x_chip_infos[] = {
0302     [mcp3001] = {
0303         .channels = mcp3201_channels,
0304         .num_channels = ARRAY_SIZE(mcp3201_channels),
0305         .resolution = 10
0306     },
0307     [mcp3002] = {
0308         .channels = mcp3202_channels,
0309         .num_channels = ARRAY_SIZE(mcp3202_channels),
0310         .resolution = 10
0311     },
0312     [mcp3004] = {
0313         .channels = mcp3204_channels,
0314         .num_channels = ARRAY_SIZE(mcp3204_channels),
0315         .resolution = 10
0316     },
0317     [mcp3008] = {
0318         .channels = mcp3208_channels,
0319         .num_channels = ARRAY_SIZE(mcp3208_channels),
0320         .resolution = 10
0321     },
0322     [mcp3201] = {
0323         .channels = mcp3201_channels,
0324         .num_channels = ARRAY_SIZE(mcp3201_channels),
0325         .resolution = 12
0326     },
0327     [mcp3202] = {
0328         .channels = mcp3202_channels,
0329         .num_channels = ARRAY_SIZE(mcp3202_channels),
0330         .resolution = 12
0331     },
0332     [mcp3204] = {
0333         .channels = mcp3204_channels,
0334         .num_channels = ARRAY_SIZE(mcp3204_channels),
0335         .resolution = 12
0336     },
0337     [mcp3208] = {
0338         .channels = mcp3208_channels,
0339         .num_channels = ARRAY_SIZE(mcp3208_channels),
0340         .resolution = 12
0341     },
0342     [mcp3301] = {
0343         .channels = mcp3201_channels,
0344         .num_channels = ARRAY_SIZE(mcp3201_channels),
0345         .resolution = 13
0346     },
0347     [mcp3550_50] = {
0348         .channels = mcp3201_channels,
0349         .num_channels = ARRAY_SIZE(mcp3201_channels),
0350         .resolution = 21,
0351         /* 2% max deviation + 144 clock periods to exit shutdown */
0352         .conv_time = 80000 * 1.02 + 144000 / 102.4,
0353     },
0354     [mcp3550_60] = {
0355         .channels = mcp3201_channels,
0356         .num_channels = ARRAY_SIZE(mcp3201_channels),
0357         .resolution = 21,
0358         .conv_time = 66670 * 1.02 + 144000 / 122.88,
0359     },
0360     [mcp3551] = {
0361         .channels = mcp3201_channels,
0362         .num_channels = ARRAY_SIZE(mcp3201_channels),
0363         .resolution = 21,
0364         .conv_time = 73100 * 1.02 + 144000 / 112.64,
0365     },
0366     [mcp3553] = {
0367         .channels = mcp3201_channels,
0368         .num_channels = ARRAY_SIZE(mcp3201_channels),
0369         .resolution = 21,
0370         .conv_time = 16670 * 1.02 + 144000 / 122.88,
0371     },
0372 };
0373
0374 static int mcp320x_probe(struct spi_device *spi)
0375 {
0376     struct iio_dev *indio_dev;
0377     struct mcp320x *adc;
0378     const struct mcp320x_chip_info *chip_info;
0379     int ret, device_index;
0380
0381     indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*adc));
0382     if (!indio_dev)
0383         return -ENOMEM;
0384
0385     adc = iio_priv(indio_dev);
0386     adc->spi = spi;
0387
0388     indio_dev->name = spi_get_device_id(spi)->name;
0389     indio_dev->modes = INDIO_DIRECT_MODE;
0390     indio_dev->info = &mcp320x_info;
0391     spi_set_drvdata(spi, indio_dev);
0392
0393     device_index = spi_get_device_id(spi)->driver_data;
0394     chip_info = &mcp320x_chip_infos[device_index];
0395     indio_dev->channels = chip_info->channels;
0396     indio_dev->num_channels = chip_info->num_channels;
0397
0398     adc->chip_info = chip_info;
0399
0400     adc->transfer[0].tx_buf = &adc->tx_buf;
0401     adc->transfer[0].len = sizeof(adc->tx_buf);
0402     adc->transfer[1].rx_buf = adc->rx_buf;
0403     adc->transfer[1].len = DIV_ROUND_UP(chip_info->resolution, 8);
0404
0405     if (chip_info->num_channels == 1)
0406         /* single-channel converters are rx only (no MOSI pin) */
0407         spi_message_init_with_transfers(&adc->msg,
0408                         &adc->transfer[1], 1);
0409     else
0410         spi_message_init_with_transfers(&adc->msg, adc->transfer,
0411                         ARRAY_SIZE(adc->transfer));
0412
0413     switch (device_index) {
0414     case mcp3550_50:
0415     case mcp3550_60:
0416     case mcp3551:
0417     case mcp3553:
0418         /* rx len increases from 24 to 25 bit in SPI mode 0,0 */
0419         if (!(spi->mode & SPI_CPOL))
0420             adc->transfer[1].len++;
0421
0422         /* conversions are started by asserting CS pin for 8 usec */
0423         adc->start_conv_transfer.delay.value = 8;
0424         adc->start_conv_transfer.delay.unit = SPI_DELAY_UNIT_USECS;
0425         spi_message_init_with_transfers(&adc->start_conv_msg,
0426                         &adc->start_conv_transfer, 1);
0427
0428         /*
0429          * If CS was previously kept low (continuous conversion mode)
0430          * and then changed to high, the chip is in shutdown.
0431          * Sometimes it fails to wake from shutdown and clocks out
0432          * only 0xffffff.  The magic sequence of performing two
0433          * conversions without delay between them resets the chip
0434          * and ensures all subsequent conversions succeed.
0435          */
0436         mcp320x_adc_conversion(adc, 0, 1, device_index, &ret);
0437         mcp320x_adc_conversion(adc, 0, 1, device_index, &ret);
0438     }
0439
0440     adc->reg = devm_regulator_get(&spi->dev, "vref");
0441     if (IS_ERR(adc->reg))
0442         return PTR_ERR(adc->reg);
0443
0444     ret = regulator_enable(adc->reg);
0445     if (ret < 0)
0446         return ret;
0447
0448     mutex_init(&adc->lock);
0449
0450     ret = iio_device_register(indio_dev);
0451     if (ret < 0)
0452         goto reg_disable;
0453
0454     return 0;
0455
0456 reg_disable:
0457     regulator_disable(adc->reg);
0458
0459     return ret;
0460 }
0461
0462 static void mcp320x_remove(struct spi_device *spi)
0463 {
0464     struct iio_dev *indio_dev = spi_get_drvdata(spi);
0465     struct mcp320x *adc = iio_priv(indio_dev);
0466
0467     iio_device_unregister(indio_dev);
0468     regulator_disable(adc->reg);
0469 }
0470
0471 static const struct of_device_id mcp320x_dt_ids[] = {
0472     /* NOTE: The use of compatibles with no vendor prefix is deprecated. */
0473     { .compatible = "mcp3001" },
0474     { .compatible = "mcp3002" },
0475     { .compatible = "mcp3004" },
0476     { .compatible = "mcp3008" },
0477     { .compatible = "mcp3201" },
0478     { .compatible = "mcp3202" },
0479     { .compatible = "mcp3204" },
0480     { .compatible = "mcp3208" },
0481     { .compatible = "mcp3301" },
0482     { .compatible = "microchip,mcp3001" },
0483     { .compatible = "microchip,mcp3002" },
0484     { .compatible = "microchip,mcp3004" },
0485     { .compatible = "microchip,mcp3008" },
0486     { .compatible = "microchip,mcp3201" },
0487     { .compatible = "microchip,mcp3202" },
0488     { .compatible = "microchip,mcp3204" },
0489     { .compatible = "microchip,mcp3208" },
0490     { .compatible = "microchip,mcp3301" },
0491     { .compatible = "microchip,mcp3550-50" },
0492     { .compatible = "microchip,mcp3550-60" },
0493     { .compatible = "microchip,mcp3551" },
0494     { .compatible = "microchip,mcp3553" },
0495     { }
0496 };
0497 MODULE_DEVICE_TABLE(of, mcp320x_dt_ids);
0498
0499 static const struct spi_device_id mcp320x_id[] = {
0500     { "mcp3001", mcp3001 },
0501     { "mcp3002", mcp3002 },
0502     { "mcp3004", mcp3004 },
0503     { "mcp3008", mcp3008 },
0504     { "mcp3201", mcp3201 },
0505     { "mcp3202", mcp3202 },
0506     { "mcp3204", mcp3204 },
0507     { "mcp3208", mcp3208 },
0508     { "mcp3301", mcp3301 },
0509     { "mcp3550-50", mcp3550_50 },
0510     { "mcp3550-60", mcp3550_60 },
0511     { "mcp3551", mcp3551 },
0512     { "mcp3553", mcp3553 },
0513     { }
0514 };
0515 MODULE_DEVICE_TABLE(spi, mcp320x_id);
0516
0517 static struct spi_driver mcp320x_driver = {
0518     .driver = {
0519         .name = "mcp320x",
0520         .of_match_table = mcp320x_dt_ids,
0521     },
0522     .probe = mcp320x_probe,
0523     .remove = mcp320x_remove,
0524     .id_table = mcp320x_id,
0525 };
0526 module_spi_driver(mcp320x_driver);
0527
0528 MODULE_AUTHOR("Oskar Andero <oskar.andero@gmail.com>");
0529 MODULE_DESCRIPTION("Microchip Technology MCP3x01/02/04/08 and MCP3550/1/3");
0530 MODULE_LICENSE("GPL v2");