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0001 // SPDX-License-Identifier: GPL-2.0-only
0002  /*
0003   * iio/adc/max1363.c
0004   * Copyright (C) 2008-2010 Jonathan Cameron
0005   *
0006   * based on linux/drivers/i2c/chips/max123x
0007   * Copyright (C) 2002-2004 Stefan Eletzhofer
0008   *
0009   * based on linux/drivers/acron/char/pcf8583.c
0010   * Copyright (C) 2000 Russell King
0011   *
0012   * Driver for max1363 and similar chips.
0013   */
0014 
0015 #include <linux/interrupt.h>
0016 #include <linux/device.h>
0017 #include <linux/kernel.h>
0018 #include <linux/sysfs.h>
0019 #include <linux/list.h>
0020 #include <linux/i2c.h>
0021 #include <linux/regulator/consumer.h>
0022 #include <linux/slab.h>
0023 #include <linux/err.h>
0024 #include <linux/module.h>
0025 #include <linux/mod_devicetable.h>
0026 #include <linux/property.h>
0027 
0028 #include <linux/iio/iio.h>
0029 #include <linux/iio/sysfs.h>
0030 #include <linux/iio/events.h>
0031 #include <linux/iio/buffer.h>
0032 #include <linux/iio/driver.h>
0033 #include <linux/iio/kfifo_buf.h>
0034 #include <linux/iio/trigger_consumer.h>
0035 #include <linux/iio/triggered_buffer.h>
0036 
0037 #define MAX1363_SETUP_BYTE(a) ((a) | 0x80)
0038 
0039 /* There is a fair bit more defined here than currently
0040  * used, but the intention is to support everything these
0041  * chips do in the long run */
0042 
0043 /* see data sheets */
0044 /* max1363 and max1236, max1237, max1238, max1239 */
0045 #define MAX1363_SETUP_AIN3_IS_AIN3_REF_IS_VDD   0x00
0046 #define MAX1363_SETUP_AIN3_IS_REF_EXT_TO_REF    0x20
0047 #define MAX1363_SETUP_AIN3_IS_AIN3_REF_IS_INT   0x40
0048 #define MAX1363_SETUP_AIN3_IS_REF_REF_IS_INT    0x60
0049 #define MAX1363_SETUP_POWER_UP_INT_REF      0x10
0050 #define MAX1363_SETUP_POWER_DOWN_INT_REF    0x00
0051 
0052 /* think about including max11600 etc - more settings */
0053 #define MAX1363_SETUP_EXT_CLOCK         0x08
0054 #define MAX1363_SETUP_INT_CLOCK         0x00
0055 #define MAX1363_SETUP_UNIPOLAR          0x00
0056 #define MAX1363_SETUP_BIPOLAR           0x04
0057 #define MAX1363_SETUP_RESET         0x00
0058 #define MAX1363_SETUP_NORESET           0x02
0059 /* max1363 only - though don't care on others.
0060  * For now monitor modes are not implemented as the relevant
0061  * line is not connected on my test board.
0062  * The definitions are here as I intend to add this soon.
0063  */
0064 #define MAX1363_SETUP_MONITOR_SETUP     0x01
0065 
0066 /* Specific to the max1363 */
0067 #define MAX1363_MON_RESET_CHAN(a) (1 << ((a) + 4))
0068 #define MAX1363_MON_INT_ENABLE          0x01
0069 
0070 /* defined for readability reasons */
0071 /* All chips */
0072 #define MAX1363_CONFIG_BYTE(a) ((a))
0073 
0074 #define MAX1363_CONFIG_SE           0x01
0075 #define MAX1363_CONFIG_DE           0x00
0076 #define MAX1363_CONFIG_SCAN_TO_CS       0x00
0077 #define MAX1363_CONFIG_SCAN_SINGLE_8        0x20
0078 #define MAX1363_CONFIG_SCAN_MONITOR_MODE    0x40
0079 #define MAX1363_CONFIG_SCAN_SINGLE_1        0x60
0080 /* max123{6-9} only */
0081 #define MAX1236_SCAN_MID_TO_CHANNEL     0x40
0082 
0083 /* max1363 only - merely part of channel selects or don't care for others */
0084 #define MAX1363_CONFIG_EN_MON_MODE_READ 0x18
0085 
0086 #define MAX1363_CHANNEL_SEL(a) ((a) << 1)
0087 
0088 /* max1363 strictly 0x06 - but doesn't matter */
0089 #define MAX1363_CHANNEL_SEL_MASK        0x1E
0090 #define MAX1363_SCAN_MASK           0x60
0091 #define MAX1363_SE_DE_MASK          0x01
0092 
0093 #define MAX1363_MAX_CHANNELS 25
0094 /**
0095  * struct max1363_mode - scan mode information
0096  * @conf:   The corresponding value of the configuration register
0097  * @modemask:   Bit mask corresponding to channels enabled in this mode
0098  */
0099 struct max1363_mode {
0100     int8_t      conf;
0101     DECLARE_BITMAP(modemask, MAX1363_MAX_CHANNELS);
0102 };
0103 
0104 /* This must be maintained along side the max1363_mode_table in max1363_core */
0105 enum max1363_modes {
0106     /* Single read of a single channel */
0107     _s0, _s1, _s2, _s3, _s4, _s5, _s6, _s7, _s8, _s9, _s10, _s11,
0108     /* Differential single read */
0109     d0m1, d2m3, d4m5, d6m7, d8m9, d10m11,
0110     d1m0, d3m2, d5m4, d7m6, d9m8, d11m10,
0111     /* Scan to channel and mid to channel where overlapping */
0112     s0to1, s0to2, s2to3, s0to3, s0to4, s0to5, s0to6,
0113     s6to7, s0to7, s6to8, s0to8, s6to9,
0114     s0to9, s6to10, s0to10, s6to11, s0to11,
0115     /* Differential scan to channel and mid to channel where overlapping */
0116     d0m1to2m3, d0m1to4m5, d0m1to6m7, d6m7to8m9,
0117     d0m1to8m9, d6m7to10m11, d0m1to10m11, d1m0to3m2,
0118     d1m0to5m4, d1m0to7m6, d7m6to9m8, d1m0to9m8,
0119     d7m6to11m10, d1m0to11m10,
0120 };
0121 
0122 /**
0123  * struct max1363_chip_info - chip specifc information
0124  * @info:       iio core function callbacks structure
0125  * @channels:       channel specification
0126  * @num_channels:       number of channels
0127  * @mode_list:      array of available scan modes
0128  * @default_mode:   the scan mode in which the chip starts up
0129  * @int_vref_mv:    the internal reference voltage
0130  * @num_modes:      number of modes
0131  * @bits:       accuracy of the adc in bits
0132  */
0133 struct max1363_chip_info {
0134     const struct iio_info       *info;
0135     const struct iio_chan_spec  *channels;
0136     int             num_channels;
0137     const enum max1363_modes    *mode_list;
0138     enum max1363_modes      default_mode;
0139     u16             int_vref_mv;
0140     u8              num_modes;
0141     u8              bits;
0142 };
0143 
0144 /**
0145  * struct max1363_state - driver instance specific data
0146  * @client:     i2c_client
0147  * @setupbyte:      cache of current device setup byte
0148  * @configbyte:     cache of current device config byte
0149  * @chip_info:      chip model specific constants, available modes, etc.
0150  * @current_mode:   the scan mode of this chip
0151  * @requestedmask:  a valid requested set of channels
0152  * @reg:        supply regulator
0153  * @lock:       lock to ensure state is consistent
0154  * @monitor_on:     whether monitor mode is enabled
0155  * @monitor_speed:  parameter corresponding to device monitor speed setting
0156  * @mask_high:      bitmask for enabled high thresholds
0157  * @mask_low:       bitmask for enabled low thresholds
0158  * @thresh_high:    high threshold values
0159  * @thresh_low:     low threshold values
0160  * @vref:       Reference voltage regulator
0161  * @vref_uv:        Actual (external or internal) reference voltage
0162  * @send:       function used to send data to the chip
0163  * @recv:       function used to receive data from the chip
0164  */
0165 struct max1363_state {
0166     struct i2c_client       *client;
0167     u8              setupbyte;
0168     u8              configbyte;
0169     const struct max1363_chip_info  *chip_info;
0170     const struct max1363_mode   *current_mode;
0171     u32             requestedmask;
0172     struct regulator        *reg;
0173     struct mutex            lock;
0174 
0175     /* Using monitor modes and buffer at the same time is
0176        currently not supported */
0177     bool                monitor_on;
0178     unsigned int            monitor_speed:3;
0179     u8              mask_high;
0180     u8              mask_low;
0181     /* 4x unipolar first then the fours bipolar ones */
0182     s16             thresh_high[8];
0183     s16             thresh_low[8];
0184     struct regulator        *vref;
0185     u32             vref_uv;
0186     int             (*send)(const struct i2c_client *client,
0187                         const char *buf, int count);
0188     int             (*recv)(const struct i2c_client *client,
0189                         char *buf, int count);
0190 };
0191 
0192 #define MAX1363_MODE_SINGLE(_num, _mask) {              \
0193         .conf = MAX1363_CHANNEL_SEL(_num)           \
0194             | MAX1363_CONFIG_SCAN_SINGLE_1          \
0195             | MAX1363_CONFIG_SE,                \
0196             .modemask[0] = _mask,               \
0197             }
0198 
0199 #define MAX1363_MODE_SCAN_TO_CHANNEL(_num, _mask) {         \
0200         .conf = MAX1363_CHANNEL_SEL(_num)           \
0201             | MAX1363_CONFIG_SCAN_TO_CS         \
0202             | MAX1363_CONFIG_SE,                \
0203             .modemask[0] = _mask,               \
0204             }
0205 
0206 /* note not available for max1363 hence naming */
0207 #define MAX1236_MODE_SCAN_MID_TO_CHANNEL(_mid, _num, _mask) {       \
0208         .conf = MAX1363_CHANNEL_SEL(_num)           \
0209             | MAX1236_SCAN_MID_TO_CHANNEL           \
0210             | MAX1363_CONFIG_SE,                \
0211             .modemask[0] = _mask                \
0212 }
0213 
0214 #define MAX1363_MODE_DIFF_SINGLE(_nump, _numm, _mask) {         \
0215         .conf = MAX1363_CHANNEL_SEL(_nump)          \
0216             | MAX1363_CONFIG_SCAN_SINGLE_1          \
0217             | MAX1363_CONFIG_DE,                \
0218             .modemask[0] = _mask                \
0219             }
0220 
0221 /* Can't think how to automate naming so specify for now */
0222 #define MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(_num, _numvals, _mask) {  \
0223         .conf = MAX1363_CHANNEL_SEL(_num)           \
0224             | MAX1363_CONFIG_SCAN_TO_CS         \
0225             | MAX1363_CONFIG_DE,                \
0226             .modemask[0] = _mask                \
0227             }
0228 
0229 /* note only available for max1363 hence naming */
0230 #define MAX1236_MODE_DIFF_SCAN_MID_TO_CHANNEL(_num, _numvals, _mask) {  \
0231         .conf = MAX1363_CHANNEL_SEL(_num)           \
0232             | MAX1236_SCAN_MID_TO_CHANNEL           \
0233             | MAX1363_CONFIG_SE,                \
0234             .modemask[0] = _mask                \
0235 }
0236 
0237 static const struct max1363_mode max1363_mode_table[] = {
0238     /* All of the single channel options first */
0239     MAX1363_MODE_SINGLE(0, 1 << 0),
0240     MAX1363_MODE_SINGLE(1, 1 << 1),
0241     MAX1363_MODE_SINGLE(2, 1 << 2),
0242     MAX1363_MODE_SINGLE(3, 1 << 3),
0243     MAX1363_MODE_SINGLE(4, 1 << 4),
0244     MAX1363_MODE_SINGLE(5, 1 << 5),
0245     MAX1363_MODE_SINGLE(6, 1 << 6),
0246     MAX1363_MODE_SINGLE(7, 1 << 7),
0247     MAX1363_MODE_SINGLE(8, 1 << 8),
0248     MAX1363_MODE_SINGLE(9, 1 << 9),
0249     MAX1363_MODE_SINGLE(10, 1 << 10),
0250     MAX1363_MODE_SINGLE(11, 1 << 11),
0251 
0252     MAX1363_MODE_DIFF_SINGLE(0, 1, 1 << 12),
0253     MAX1363_MODE_DIFF_SINGLE(2, 3, 1 << 13),
0254     MAX1363_MODE_DIFF_SINGLE(4, 5, 1 << 14),
0255     MAX1363_MODE_DIFF_SINGLE(6, 7, 1 << 15),
0256     MAX1363_MODE_DIFF_SINGLE(8, 9, 1 << 16),
0257     MAX1363_MODE_DIFF_SINGLE(10, 11, 1 << 17),
0258     MAX1363_MODE_DIFF_SINGLE(1, 0, 1 << 18),
0259     MAX1363_MODE_DIFF_SINGLE(3, 2, 1 << 19),
0260     MAX1363_MODE_DIFF_SINGLE(5, 4, 1 << 20),
0261     MAX1363_MODE_DIFF_SINGLE(7, 6, 1 << 21),
0262     MAX1363_MODE_DIFF_SINGLE(9, 8, 1 << 22),
0263     MAX1363_MODE_DIFF_SINGLE(11, 10, 1 << 23),
0264 
0265     /* The multichannel scans next */
0266     MAX1363_MODE_SCAN_TO_CHANNEL(1, 0x003),
0267     MAX1363_MODE_SCAN_TO_CHANNEL(2, 0x007),
0268     MAX1236_MODE_SCAN_MID_TO_CHANNEL(2, 3, 0x00C),
0269     MAX1363_MODE_SCAN_TO_CHANNEL(3, 0x00F),
0270     MAX1363_MODE_SCAN_TO_CHANNEL(4, 0x01F),
0271     MAX1363_MODE_SCAN_TO_CHANNEL(5, 0x03F),
0272     MAX1363_MODE_SCAN_TO_CHANNEL(6, 0x07F),
0273     MAX1236_MODE_SCAN_MID_TO_CHANNEL(6, 7, 0x0C0),
0274     MAX1363_MODE_SCAN_TO_CHANNEL(7, 0x0FF),
0275     MAX1236_MODE_SCAN_MID_TO_CHANNEL(6, 8, 0x1C0),
0276     MAX1363_MODE_SCAN_TO_CHANNEL(8, 0x1FF),
0277     MAX1236_MODE_SCAN_MID_TO_CHANNEL(6, 9, 0x3C0),
0278     MAX1363_MODE_SCAN_TO_CHANNEL(9, 0x3FF),
0279     MAX1236_MODE_SCAN_MID_TO_CHANNEL(6, 10, 0x7C0),
0280     MAX1363_MODE_SCAN_TO_CHANNEL(10, 0x7FF),
0281     MAX1236_MODE_SCAN_MID_TO_CHANNEL(6, 11, 0xFC0),
0282     MAX1363_MODE_SCAN_TO_CHANNEL(11, 0xFFF),
0283 
0284     MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(2, 2, 0x003000),
0285     MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(4, 3, 0x007000),
0286     MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(6, 4, 0x00F000),
0287     MAX1236_MODE_DIFF_SCAN_MID_TO_CHANNEL(8, 2, 0x018000),
0288     MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(8, 5, 0x01F000),
0289     MAX1236_MODE_DIFF_SCAN_MID_TO_CHANNEL(10, 3, 0x038000),
0290     MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(10, 6, 0x3F000),
0291     MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(3, 2, 0x0C0000),
0292     MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(5, 3, 0x1C0000),
0293     MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(7, 4, 0x3C0000),
0294     MAX1236_MODE_DIFF_SCAN_MID_TO_CHANNEL(9, 2, 0x600000),
0295     MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(9, 5, 0x7C0000),
0296     MAX1236_MODE_DIFF_SCAN_MID_TO_CHANNEL(11, 3, 0xE00000),
0297     MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(11, 6, 0xFC0000),
0298 };
0299 
0300 static const struct max1363_mode
0301 *max1363_match_mode(const unsigned long *mask,
0302     const struct max1363_chip_info *ci)
0303 {
0304     int i;
0305     if (mask)
0306         for (i = 0; i < ci->num_modes; i++)
0307             if (bitmap_subset(mask,
0308                       max1363_mode_table[ci->mode_list[i]].
0309                       modemask,
0310                       MAX1363_MAX_CHANNELS))
0311                 return &max1363_mode_table[ci->mode_list[i]];
0312     return NULL;
0313 }
0314 
0315 static int max1363_smbus_send(const struct i2c_client *client, const char *buf,
0316         int count)
0317 {
0318     int i, err;
0319 
0320     for (i = err = 0; err == 0 && i < count; ++i)
0321         err = i2c_smbus_write_byte(client, buf[i]);
0322 
0323     return err ? err : count;
0324 }
0325 
0326 static int max1363_smbus_recv(const struct i2c_client *client, char *buf,
0327         int count)
0328 {
0329     int i, ret;
0330 
0331     for (i = 0; i < count; ++i) {
0332         ret = i2c_smbus_read_byte(client);
0333         if (ret < 0)
0334             return ret;
0335         buf[i] = ret;
0336     }
0337 
0338     return count;
0339 }
0340 
0341 static int max1363_write_basic_config(struct max1363_state *st)
0342 {
0343     u8 tx_buf[2] = { st->setupbyte, st->configbyte };
0344 
0345     return st->send(st->client, tx_buf, 2);
0346 }
0347 
0348 static int max1363_set_scan_mode(struct max1363_state *st)
0349 {
0350     st->configbyte &= ~(MAX1363_CHANNEL_SEL_MASK
0351                 | MAX1363_SCAN_MASK
0352                 | MAX1363_SE_DE_MASK);
0353     st->configbyte |= st->current_mode->conf;
0354 
0355     return max1363_write_basic_config(st);
0356 }
0357 
0358 static int max1363_read_single_chan(struct iio_dev *indio_dev,
0359                     struct iio_chan_spec const *chan,
0360                     int *val,
0361                     long m)
0362 {
0363     int ret = 0;
0364     s32 data;
0365     u8 rxbuf[2];
0366     struct max1363_state *st = iio_priv(indio_dev);
0367     struct i2c_client *client = st->client;
0368 
0369     ret = iio_device_claim_direct_mode(indio_dev);
0370     if (ret)
0371         return ret;
0372     mutex_lock(&st->lock);
0373 
0374     /*
0375      * If monitor mode is enabled, the method for reading a single
0376      * channel will have to be rather different and has not yet
0377      * been implemented.
0378      *
0379      * Also, cannot read directly if buffered capture enabled.
0380      */
0381     if (st->monitor_on) {
0382         ret = -EBUSY;
0383         goto error_ret;
0384     }
0385 
0386     /* Check to see if current scan mode is correct */
0387     if (st->current_mode != &max1363_mode_table[chan->address]) {
0388         /* Update scan mode if needed */
0389         st->current_mode = &max1363_mode_table[chan->address];
0390         ret = max1363_set_scan_mode(st);
0391         if (ret < 0)
0392             goto error_ret;
0393     }
0394     if (st->chip_info->bits != 8) {
0395         /* Get reading */
0396         data = st->recv(client, rxbuf, 2);
0397         if (data < 0) {
0398             ret = data;
0399             goto error_ret;
0400         }
0401         data = (rxbuf[1] | rxbuf[0] << 8) &
0402           ((1 << st->chip_info->bits) - 1);
0403     } else {
0404         /* Get reading */
0405         data = st->recv(client, rxbuf, 1);
0406         if (data < 0) {
0407             ret = data;
0408             goto error_ret;
0409         }
0410         data = rxbuf[0];
0411     }
0412     *val = data;
0413 
0414 error_ret:
0415     mutex_unlock(&st->lock);
0416     iio_device_release_direct_mode(indio_dev);
0417     return ret;
0418 
0419 }
0420 
0421 static int max1363_read_raw(struct iio_dev *indio_dev,
0422                 struct iio_chan_spec const *chan,
0423                 int *val,
0424                 int *val2,
0425                 long m)
0426 {
0427     struct max1363_state *st = iio_priv(indio_dev);
0428     int ret;
0429 
0430     switch (m) {
0431     case IIO_CHAN_INFO_RAW:
0432         ret = max1363_read_single_chan(indio_dev, chan, val, m);
0433         if (ret < 0)
0434             return ret;
0435         return IIO_VAL_INT;
0436     case IIO_CHAN_INFO_SCALE:
0437         *val = st->vref_uv / 1000;
0438         *val2 = st->chip_info->bits;
0439         return IIO_VAL_FRACTIONAL_LOG2;
0440     default:
0441         return -EINVAL;
0442     }
0443     return 0;
0444 }
0445 
0446 /* Applies to max1363 */
0447 static const enum max1363_modes max1363_mode_list[] = {
0448     _s0, _s1, _s2, _s3,
0449     s0to1, s0to2, s0to3,
0450     d0m1, d2m3, d1m0, d3m2,
0451     d0m1to2m3, d1m0to3m2,
0452 };
0453 
0454 static const struct iio_event_spec max1363_events[] = {
0455     {
0456         .type = IIO_EV_TYPE_THRESH,
0457         .dir = IIO_EV_DIR_RISING,
0458         .mask_separate = BIT(IIO_EV_INFO_VALUE) |
0459             BIT(IIO_EV_INFO_ENABLE),
0460     }, {
0461         .type = IIO_EV_TYPE_THRESH,
0462         .dir = IIO_EV_DIR_FALLING,
0463         .mask_separate = BIT(IIO_EV_INFO_VALUE) |
0464             BIT(IIO_EV_INFO_ENABLE),
0465     },
0466 };
0467 
0468 #define MAX1363_CHAN_U(num, addr, si, bits, ev_spec, num_ev_spec)   \
0469     {                               \
0470         .type = IIO_VOLTAGE,                    \
0471         .indexed = 1,                       \
0472         .channel = num,                     \
0473         .address = addr,                    \
0474         .info_mask_separate = BIT(IIO_CHAN_INFO_RAW),       \
0475         .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),   \
0476         .datasheet_name = "AIN"#num,                \
0477         .scan_type = {                      \
0478             .sign = 'u',                    \
0479             .realbits = bits,               \
0480             .storagebits = (bits > 8) ? 16 : 8,     \
0481             .endianness = IIO_BE,               \
0482         },                          \
0483         .scan_index = si,                   \
0484         .event_spec = ev_spec,                  \
0485         .num_event_specs = num_ev_spec,             \
0486     }
0487 
0488 /* bipolar channel */
0489 #define MAX1363_CHAN_B(num, num2, addr, si, bits, ev_spec, num_ev_spec) \
0490     {                               \
0491         .type = IIO_VOLTAGE,                    \
0492         .differential = 1,                  \
0493         .indexed = 1,                       \
0494         .channel = num,                     \
0495         .channel2 = num2,                   \
0496         .address = addr,                    \
0497         .info_mask_separate = BIT(IIO_CHAN_INFO_RAW),       \
0498         .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),   \
0499         .datasheet_name = "AIN"#num"-AIN"#num2,         \
0500         .scan_type = {                      \
0501             .sign = 's',                    \
0502             .realbits = bits,               \
0503             .storagebits = (bits > 8) ? 16 : 8,     \
0504             .endianness = IIO_BE,               \
0505         },                          \
0506         .scan_index = si,                   \
0507         .event_spec = ev_spec,                  \
0508         .num_event_specs = num_ev_spec,             \
0509     }
0510 
0511 #define MAX1363_4X_CHANS(bits, ev_spec, num_ev_spec) {          \
0512     MAX1363_CHAN_U(0, _s0, 0, bits, ev_spec, num_ev_spec),      \
0513     MAX1363_CHAN_U(1, _s1, 1, bits, ev_spec, num_ev_spec),      \
0514     MAX1363_CHAN_U(2, _s2, 2, bits, ev_spec, num_ev_spec),      \
0515     MAX1363_CHAN_U(3, _s3, 3, bits, ev_spec, num_ev_spec),      \
0516     MAX1363_CHAN_B(0, 1, d0m1, 4, bits, ev_spec, num_ev_spec),  \
0517     MAX1363_CHAN_B(2, 3, d2m3, 5, bits, ev_spec, num_ev_spec),  \
0518     MAX1363_CHAN_B(1, 0, d1m0, 6, bits, ev_spec, num_ev_spec),  \
0519     MAX1363_CHAN_B(3, 2, d3m2, 7, bits, ev_spec, num_ev_spec),  \
0520     IIO_CHAN_SOFT_TIMESTAMP(8)                  \
0521     }
0522 
0523 static const struct iio_chan_spec max1036_channels[] =
0524     MAX1363_4X_CHANS(8, NULL, 0);
0525 static const struct iio_chan_spec max1136_channels[] =
0526     MAX1363_4X_CHANS(10, NULL, 0);
0527 static const struct iio_chan_spec max1236_channels[] =
0528     MAX1363_4X_CHANS(12, NULL, 0);
0529 static const struct iio_chan_spec max1361_channels[] =
0530     MAX1363_4X_CHANS(10, max1363_events, ARRAY_SIZE(max1363_events));
0531 static const struct iio_chan_spec max1363_channels[] =
0532     MAX1363_4X_CHANS(12, max1363_events, ARRAY_SIZE(max1363_events));
0533 
0534 /* Applies to max1236, max1237 */
0535 static const enum max1363_modes max1236_mode_list[] = {
0536     _s0, _s1, _s2, _s3,
0537     s0to1, s0to2, s0to3,
0538     d0m1, d2m3, d1m0, d3m2,
0539     d0m1to2m3, d1m0to3m2,
0540     s2to3,
0541 };
0542 
0543 /* Applies to max1238, max1239 */
0544 static const enum max1363_modes max1238_mode_list[] = {
0545     _s0, _s1, _s2, _s3, _s4, _s5, _s6, _s7, _s8, _s9, _s10, _s11,
0546     s0to1, s0to2, s0to3, s0to4, s0to5, s0to6,
0547     s0to7, s0to8, s0to9, s0to10, s0to11,
0548     d0m1, d2m3, d4m5, d6m7, d8m9, d10m11,
0549     d1m0, d3m2, d5m4, d7m6, d9m8, d11m10,
0550     d0m1to2m3, d0m1to4m5, d0m1to6m7, d0m1to8m9, d0m1to10m11,
0551     d1m0to3m2, d1m0to5m4, d1m0to7m6, d1m0to9m8, d1m0to11m10,
0552     s6to7, s6to8, s6to9, s6to10, s6to11,
0553     d6m7to8m9, d6m7to10m11, d7m6to9m8, d7m6to11m10,
0554 };
0555 
0556 #define MAX1363_12X_CHANS(bits) {               \
0557     MAX1363_CHAN_U(0, _s0, 0, bits, NULL, 0),       \
0558     MAX1363_CHAN_U(1, _s1, 1, bits, NULL, 0),       \
0559     MAX1363_CHAN_U(2, _s2, 2, bits, NULL, 0),       \
0560     MAX1363_CHAN_U(3, _s3, 3, bits, NULL, 0),       \
0561     MAX1363_CHAN_U(4, _s4, 4, bits, NULL, 0),       \
0562     MAX1363_CHAN_U(5, _s5, 5, bits, NULL, 0),       \
0563     MAX1363_CHAN_U(6, _s6, 6, bits, NULL, 0),       \
0564     MAX1363_CHAN_U(7, _s7, 7, bits, NULL, 0),       \
0565     MAX1363_CHAN_U(8, _s8, 8, bits, NULL, 0),       \
0566     MAX1363_CHAN_U(9, _s9, 9, bits, NULL, 0),       \
0567     MAX1363_CHAN_U(10, _s10, 10, bits, NULL, 0),        \
0568     MAX1363_CHAN_U(11, _s11, 11, bits, NULL, 0),        \
0569     MAX1363_CHAN_B(0, 1, d0m1, 12, bits, NULL, 0),      \
0570     MAX1363_CHAN_B(2, 3, d2m3, 13, bits, NULL, 0),      \
0571     MAX1363_CHAN_B(4, 5, d4m5, 14, bits, NULL, 0),      \
0572     MAX1363_CHAN_B(6, 7, d6m7, 15, bits, NULL, 0),      \
0573     MAX1363_CHAN_B(8, 9, d8m9, 16, bits, NULL, 0),      \
0574     MAX1363_CHAN_B(10, 11, d10m11, 17, bits, NULL, 0),  \
0575     MAX1363_CHAN_B(1, 0, d1m0, 18, bits, NULL, 0),      \
0576     MAX1363_CHAN_B(3, 2, d3m2, 19, bits, NULL, 0),      \
0577     MAX1363_CHAN_B(5, 4, d5m4, 20, bits, NULL, 0),      \
0578     MAX1363_CHAN_B(7, 6, d7m6, 21, bits, NULL, 0),      \
0579     MAX1363_CHAN_B(9, 8, d9m8, 22, bits, NULL, 0),      \
0580     MAX1363_CHAN_B(11, 10, d11m10, 23, bits, NULL, 0),  \
0581     IIO_CHAN_SOFT_TIMESTAMP(24)             \
0582     }
0583 static const struct iio_chan_spec max1038_channels[] = MAX1363_12X_CHANS(8);
0584 static const struct iio_chan_spec max1138_channels[] = MAX1363_12X_CHANS(10);
0585 static const struct iio_chan_spec max1238_channels[] = MAX1363_12X_CHANS(12);
0586 
0587 static const enum max1363_modes max11607_mode_list[] = {
0588     _s0, _s1, _s2, _s3,
0589     s0to1, s0to2, s0to3,
0590     s2to3,
0591     d0m1, d2m3, d1m0, d3m2,
0592     d0m1to2m3, d1m0to3m2,
0593 };
0594 
0595 static const enum max1363_modes max11608_mode_list[] = {
0596     _s0, _s1, _s2, _s3, _s4, _s5, _s6, _s7,
0597     s0to1, s0to2, s0to3, s0to4, s0to5, s0to6, s0to7,
0598     s6to7,
0599     d0m1, d2m3, d4m5, d6m7,
0600     d1m0, d3m2, d5m4, d7m6,
0601     d0m1to2m3, d0m1to4m5, d0m1to6m7,
0602     d1m0to3m2, d1m0to5m4, d1m0to7m6,
0603 };
0604 
0605 #define MAX1363_8X_CHANS(bits) {            \
0606     MAX1363_CHAN_U(0, _s0, 0, bits, NULL, 0),   \
0607     MAX1363_CHAN_U(1, _s1, 1, bits, NULL, 0),   \
0608     MAX1363_CHAN_U(2, _s2, 2, bits, NULL, 0),   \
0609     MAX1363_CHAN_U(3, _s3, 3, bits, NULL, 0),   \
0610     MAX1363_CHAN_U(4, _s4, 4, bits, NULL, 0),   \
0611     MAX1363_CHAN_U(5, _s5, 5, bits, NULL, 0),   \
0612     MAX1363_CHAN_U(6, _s6, 6, bits, NULL, 0),   \
0613     MAX1363_CHAN_U(7, _s7, 7, bits, NULL, 0),   \
0614     MAX1363_CHAN_B(0, 1, d0m1, 8, bits, NULL, 0),   \
0615     MAX1363_CHAN_B(2, 3, d2m3, 9, bits, NULL, 0),   \
0616     MAX1363_CHAN_B(4, 5, d4m5, 10, bits, NULL, 0),  \
0617     MAX1363_CHAN_B(6, 7, d6m7, 11, bits, NULL, 0),  \
0618     MAX1363_CHAN_B(1, 0, d1m0, 12, bits, NULL, 0),  \
0619     MAX1363_CHAN_B(3, 2, d3m2, 13, bits, NULL, 0),  \
0620     MAX1363_CHAN_B(5, 4, d5m4, 14, bits, NULL, 0),  \
0621     MAX1363_CHAN_B(7, 6, d7m6, 15, bits, NULL, 0),  \
0622     IIO_CHAN_SOFT_TIMESTAMP(16)         \
0623 }
0624 static const struct iio_chan_spec max11602_channels[] = MAX1363_8X_CHANS(8);
0625 static const struct iio_chan_spec max11608_channels[] = MAX1363_8X_CHANS(10);
0626 static const struct iio_chan_spec max11614_channels[] = MAX1363_8X_CHANS(12);
0627 
0628 static const enum max1363_modes max11644_mode_list[] = {
0629     _s0, _s1, s0to1, d0m1, d1m0,
0630 };
0631 
0632 #define MAX1363_2X_CHANS(bits) {            \
0633     MAX1363_CHAN_U(0, _s0, 0, bits, NULL, 0),   \
0634     MAX1363_CHAN_U(1, _s1, 1, bits, NULL, 0),   \
0635     MAX1363_CHAN_B(0, 1, d0m1, 2, bits, NULL, 0),   \
0636     MAX1363_CHAN_B(1, 0, d1m0, 3, bits, NULL, 0),   \
0637     IIO_CHAN_SOFT_TIMESTAMP(4)          \
0638     }
0639 
0640 static const struct iio_chan_spec max11646_channels[] = MAX1363_2X_CHANS(10);
0641 static const struct iio_chan_spec max11644_channels[] = MAX1363_2X_CHANS(12);
0642 
0643 enum { max1361,
0644        max1362,
0645        max1363,
0646        max1364,
0647        max1036,
0648        max1037,
0649        max1038,
0650        max1039,
0651        max1136,
0652        max1137,
0653        max1138,
0654        max1139,
0655        max1236,
0656        max1237,
0657        max1238,
0658        max1239,
0659        max11600,
0660        max11601,
0661        max11602,
0662        max11603,
0663        max11604,
0664        max11605,
0665        max11606,
0666        max11607,
0667        max11608,
0668        max11609,
0669        max11610,
0670        max11611,
0671        max11612,
0672        max11613,
0673        max11614,
0674        max11615,
0675        max11616,
0676        max11617,
0677        max11644,
0678        max11645,
0679        max11646,
0680        max11647
0681 };
0682 
0683 static const int max1363_monitor_speeds[] = { 133000, 665000, 33300, 16600,
0684                           8300, 4200, 2000, 1000 };
0685 
0686 static ssize_t max1363_monitor_show_freq(struct device *dev,
0687                     struct device_attribute *attr,
0688                     char *buf)
0689 {
0690     struct max1363_state *st = iio_priv(dev_to_iio_dev(dev));
0691     return sprintf(buf, "%d\n", max1363_monitor_speeds[st->monitor_speed]);
0692 }
0693 
0694 static ssize_t max1363_monitor_store_freq(struct device *dev,
0695                     struct device_attribute *attr,
0696                     const char *buf,
0697                     size_t len)
0698 {
0699     struct iio_dev *indio_dev = dev_to_iio_dev(dev);
0700     struct max1363_state *st = iio_priv(indio_dev);
0701     int i, ret;
0702     unsigned long val;
0703     bool found = false;
0704 
0705     ret = kstrtoul(buf, 10, &val);
0706     if (ret)
0707         return -EINVAL;
0708     for (i = 0; i < ARRAY_SIZE(max1363_monitor_speeds); i++)
0709         if (val == max1363_monitor_speeds[i]) {
0710             found = true;
0711             break;
0712         }
0713     if (!found)
0714         return -EINVAL;
0715 
0716     mutex_lock(&st->lock);
0717     st->monitor_speed = i;
0718     mutex_unlock(&st->lock);
0719 
0720     return 0;
0721 }
0722 
0723 static IIO_DEV_ATTR_SAMP_FREQ(S_IRUGO | S_IWUSR,
0724             max1363_monitor_show_freq,
0725             max1363_monitor_store_freq);
0726 
0727 static IIO_CONST_ATTR(sampling_frequency_available,
0728         "133000 665000 33300 16600 8300 4200 2000 1000");
0729 
0730 static int max1363_read_thresh(struct iio_dev *indio_dev,
0731     const struct iio_chan_spec *chan, enum iio_event_type type,
0732     enum iio_event_direction dir, enum iio_event_info info, int *val,
0733     int *val2)
0734 {
0735     struct max1363_state *st = iio_priv(indio_dev);
0736     if (dir == IIO_EV_DIR_FALLING)
0737         *val = st->thresh_low[chan->channel];
0738     else
0739         *val = st->thresh_high[chan->channel];
0740     return IIO_VAL_INT;
0741 }
0742 
0743 static int max1363_write_thresh(struct iio_dev *indio_dev,
0744     const struct iio_chan_spec *chan, enum iio_event_type type,
0745     enum iio_event_direction dir, enum iio_event_info info, int val,
0746     int val2)
0747 {
0748     struct max1363_state *st = iio_priv(indio_dev);
0749     /* make it handle signed correctly as well */
0750     switch (st->chip_info->bits) {
0751     case 10:
0752         if (val > 0x3FF)
0753             return -EINVAL;
0754         break;
0755     case 12:
0756         if (val > 0xFFF)
0757             return -EINVAL;
0758         break;
0759     }
0760 
0761     switch (dir) {
0762     case IIO_EV_DIR_FALLING:
0763         st->thresh_low[chan->channel] = val;
0764         break;
0765     case IIO_EV_DIR_RISING:
0766         st->thresh_high[chan->channel] = val;
0767         break;
0768     default:
0769         return -EINVAL;
0770     }
0771 
0772     return 0;
0773 }
0774 
0775 static const u64 max1363_event_codes[] = {
0776     IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 0,
0777                  IIO_EV_TYPE_THRESH, IIO_EV_DIR_FALLING),
0778     IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 1,
0779                  IIO_EV_TYPE_THRESH, IIO_EV_DIR_FALLING),
0780     IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 2,
0781                  IIO_EV_TYPE_THRESH, IIO_EV_DIR_FALLING),
0782     IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 3,
0783                  IIO_EV_TYPE_THRESH, IIO_EV_DIR_FALLING),
0784     IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 0,
0785                  IIO_EV_TYPE_THRESH, IIO_EV_DIR_RISING),
0786     IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 1,
0787                  IIO_EV_TYPE_THRESH, IIO_EV_DIR_RISING),
0788     IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 2,
0789                  IIO_EV_TYPE_THRESH, IIO_EV_DIR_RISING),
0790     IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 3,
0791                  IIO_EV_TYPE_THRESH, IIO_EV_DIR_RISING),
0792 };
0793 
0794 static irqreturn_t max1363_event_handler(int irq, void *private)
0795 {
0796     struct iio_dev *indio_dev = private;
0797     struct max1363_state *st = iio_priv(indio_dev);
0798     s64 timestamp = iio_get_time_ns(indio_dev);
0799     unsigned long mask, loc;
0800     u8 rx;
0801     u8 tx[2] = { st->setupbyte,
0802              MAX1363_MON_INT_ENABLE | (st->monitor_speed << 1) | 0xF0 };
0803 
0804     st->recv(st->client, &rx, 1);
0805     mask = rx;
0806     for_each_set_bit(loc, &mask, 8)
0807         iio_push_event(indio_dev, max1363_event_codes[loc], timestamp);
0808     st->send(st->client, tx, 2);
0809 
0810     return IRQ_HANDLED;
0811 }
0812 
0813 static int max1363_read_event_config(struct iio_dev *indio_dev,
0814     const struct iio_chan_spec *chan, enum iio_event_type type,
0815     enum iio_event_direction dir)
0816 {
0817     struct max1363_state *st = iio_priv(indio_dev);
0818     int val;
0819     int number = chan->channel;
0820 
0821     mutex_lock(&st->lock);
0822     if (dir == IIO_EV_DIR_FALLING)
0823         val = (1 << number) & st->mask_low;
0824     else
0825         val = (1 << number) & st->mask_high;
0826     mutex_unlock(&st->lock);
0827 
0828     return val;
0829 }
0830 
0831 static int max1363_monitor_mode_update(struct max1363_state *st, int enabled)
0832 {
0833     u8 *tx_buf;
0834     int ret, i = 3, j;
0835     unsigned long numelements;
0836     int len;
0837     const long *modemask;
0838 
0839     if (!enabled) {
0840         /* transition to buffered capture is not currently supported */
0841         st->setupbyte &= ~MAX1363_SETUP_MONITOR_SETUP;
0842         st->configbyte &= ~MAX1363_SCAN_MASK;
0843         st->monitor_on = false;
0844         return max1363_write_basic_config(st);
0845     }
0846 
0847     /* Ensure we are in the relevant mode */
0848     st->setupbyte |= MAX1363_SETUP_MONITOR_SETUP;
0849     st->configbyte &= ~(MAX1363_CHANNEL_SEL_MASK
0850                 | MAX1363_SCAN_MASK
0851             | MAX1363_SE_DE_MASK);
0852     st->configbyte |= MAX1363_CONFIG_SCAN_MONITOR_MODE;
0853     if ((st->mask_low | st->mask_high) & 0x0F) {
0854         st->configbyte |= max1363_mode_table[s0to3].conf;
0855         modemask = max1363_mode_table[s0to3].modemask;
0856     } else if ((st->mask_low | st->mask_high) & 0x30) {
0857         st->configbyte |= max1363_mode_table[d0m1to2m3].conf;
0858         modemask = max1363_mode_table[d0m1to2m3].modemask;
0859     } else {
0860         st->configbyte |= max1363_mode_table[d1m0to3m2].conf;
0861         modemask = max1363_mode_table[d1m0to3m2].modemask;
0862     }
0863     numelements = bitmap_weight(modemask, MAX1363_MAX_CHANNELS);
0864     len = 3 * numelements + 3;
0865     tx_buf = kmalloc(len, GFP_KERNEL);
0866     if (!tx_buf) {
0867         ret = -ENOMEM;
0868         goto error_ret;
0869     }
0870     tx_buf[0] = st->configbyte;
0871     tx_buf[1] = st->setupbyte;
0872     tx_buf[2] = (st->monitor_speed << 1);
0873 
0874     /*
0875      * So we need to do yet another bit of nefarious scan mode
0876      * setup to match what we need.
0877      */
0878     for (j = 0; j < 8; j++)
0879         if (test_bit(j, modemask)) {
0880             /* Establish the mode is in the scan */
0881             if (st->mask_low & (1 << j)) {
0882                 tx_buf[i] = (st->thresh_low[j] >> 4) & 0xFF;
0883                 tx_buf[i + 1] = (st->thresh_low[j] << 4) & 0xF0;
0884             } else if (j < 4) {
0885                 tx_buf[i] = 0;
0886                 tx_buf[i + 1] = 0;
0887             } else {
0888                 tx_buf[i] = 0x80;
0889                 tx_buf[i + 1] = 0;
0890             }
0891             if (st->mask_high & (1 << j)) {
0892                 tx_buf[i + 1] |=
0893                     (st->thresh_high[j] >> 8) & 0x0F;
0894                 tx_buf[i + 2] = st->thresh_high[j] & 0xFF;
0895             } else if (j < 4) {
0896                 tx_buf[i + 1] |= 0x0F;
0897                 tx_buf[i + 2] = 0xFF;
0898             } else {
0899                 tx_buf[i + 1] |= 0x07;
0900                 tx_buf[i + 2] = 0xFF;
0901             }
0902             i += 3;
0903         }
0904 
0905 
0906     ret = st->send(st->client, tx_buf, len);
0907     if (ret < 0)
0908         goto error_ret;
0909     if (ret != len) {
0910         ret = -EIO;
0911         goto error_ret;
0912     }
0913 
0914     /*
0915      * Now that we hopefully have sensible thresholds in place it is
0916      * time to turn the interrupts on.
0917      * It is unclear from the data sheet if this should be necessary
0918      * (i.e. whether monitor mode setup is atomic) but it appears to
0919      * be in practice.
0920      */
0921     tx_buf[0] = st->setupbyte;
0922     tx_buf[1] = MAX1363_MON_INT_ENABLE | (st->monitor_speed << 1) | 0xF0;
0923     ret = st->send(st->client, tx_buf, 2);
0924     if (ret < 0)
0925         goto error_ret;
0926     if (ret != 2) {
0927         ret = -EIO;
0928         goto error_ret;
0929     }
0930     ret = 0;
0931     st->monitor_on = true;
0932 error_ret:
0933 
0934     kfree(tx_buf);
0935 
0936     return ret;
0937 }
0938 
0939 /*
0940  * To keep this manageable we always use one of 3 scan modes.
0941  * Scan 0...3, 0-1,2-3 and 1-0,3-2
0942  */
0943 
0944 static inline int __max1363_check_event_mask(int thismask, int checkmask)
0945 {
0946     int ret = 0;
0947     /* Is it unipolar */
0948     if (thismask < 4) {
0949         if (checkmask & ~0x0F) {
0950             ret = -EBUSY;
0951             goto error_ret;
0952         }
0953     } else if (thismask < 6) {
0954         if (checkmask & ~0x30) {
0955             ret = -EBUSY;
0956             goto error_ret;
0957         }
0958     } else if (checkmask & ~0xC0)
0959         ret = -EBUSY;
0960 error_ret:
0961     return ret;
0962 }
0963 
0964 static int max1363_write_event_config(struct iio_dev *indio_dev,
0965     const struct iio_chan_spec *chan, enum iio_event_type type,
0966     enum iio_event_direction dir, int state)
0967 {
0968     int ret = 0;
0969     struct max1363_state *st = iio_priv(indio_dev);
0970     u16 unifiedmask;
0971     int number = chan->channel;
0972 
0973     ret = iio_device_claim_direct_mode(indio_dev);
0974     if (ret)
0975         return ret;
0976     mutex_lock(&st->lock);
0977 
0978     unifiedmask = st->mask_low | st->mask_high;
0979     if (dir == IIO_EV_DIR_FALLING) {
0980 
0981         if (state == 0)
0982             st->mask_low &= ~(1 << number);
0983         else {
0984             ret = __max1363_check_event_mask((1 << number),
0985                              unifiedmask);
0986             if (ret)
0987                 goto error_ret;
0988             st->mask_low |= (1 << number);
0989         }
0990     } else {
0991         if (state == 0)
0992             st->mask_high &= ~(1 << number);
0993         else {
0994             ret = __max1363_check_event_mask((1 << number),
0995                              unifiedmask);
0996             if (ret)
0997                 goto error_ret;
0998             st->mask_high |= (1 << number);
0999         }
1000     }
1001 
1002     max1363_monitor_mode_update(st, !!(st->mask_high | st->mask_low));
1003 error_ret:
1004     mutex_unlock(&st->lock);
1005     iio_device_release_direct_mode(indio_dev);
1006 
1007     return ret;
1008 }
1009 
1010 /*
1011  * As with scan_elements, only certain sets of these can
1012  * be combined.
1013  */
1014 static struct attribute *max1363_event_attributes[] = {
1015     &iio_dev_attr_sampling_frequency.dev_attr.attr,
1016     &iio_const_attr_sampling_frequency_available.dev_attr.attr,
1017     NULL,
1018 };
1019 
1020 static const struct attribute_group max1363_event_attribute_group = {
1021     .attrs = max1363_event_attributes,
1022 };
1023 
1024 static int max1363_update_scan_mode(struct iio_dev *indio_dev,
1025                     const unsigned long *scan_mask)
1026 {
1027     struct max1363_state *st = iio_priv(indio_dev);
1028 
1029     /*
1030      * Need to figure out the current mode based upon the requested
1031      * scan mask in iio_dev
1032      */
1033     st->current_mode = max1363_match_mode(scan_mask, st->chip_info);
1034     if (!st->current_mode)
1035         return -EINVAL;
1036     max1363_set_scan_mode(st);
1037     return 0;
1038 }
1039 
1040 static const struct iio_info max1238_info = {
1041     .read_raw = &max1363_read_raw,
1042     .update_scan_mode = &max1363_update_scan_mode,
1043 };
1044 
1045 static const struct iio_info max1363_info = {
1046     .read_event_value = &max1363_read_thresh,
1047     .write_event_value = &max1363_write_thresh,
1048     .read_event_config = &max1363_read_event_config,
1049     .write_event_config = &max1363_write_event_config,
1050     .read_raw = &max1363_read_raw,
1051     .update_scan_mode = &max1363_update_scan_mode,
1052     .event_attrs = &max1363_event_attribute_group,
1053 };
1054 
1055 /* max1363 and max1368 tested - rest from data sheet */
1056 static const struct max1363_chip_info max1363_chip_info_tbl[] = {
1057     [max1361] = {
1058         .bits = 10,
1059         .int_vref_mv = 2048,
1060         .mode_list = max1363_mode_list,
1061         .num_modes = ARRAY_SIZE(max1363_mode_list),
1062         .default_mode = s0to3,
1063         .channels = max1361_channels,
1064         .num_channels = ARRAY_SIZE(max1361_channels),
1065         .info = &max1363_info,
1066     },
1067     [max1362] = {
1068         .bits = 10,
1069         .int_vref_mv = 4096,
1070         .mode_list = max1363_mode_list,
1071         .num_modes = ARRAY_SIZE(max1363_mode_list),
1072         .default_mode = s0to3,
1073         .channels = max1361_channels,
1074         .num_channels = ARRAY_SIZE(max1361_channels),
1075         .info = &max1363_info,
1076     },
1077     [max1363] = {
1078         .bits = 12,
1079         .int_vref_mv = 2048,
1080         .mode_list = max1363_mode_list,
1081         .num_modes = ARRAY_SIZE(max1363_mode_list),
1082         .default_mode = s0to3,
1083         .channels = max1363_channels,
1084         .num_channels = ARRAY_SIZE(max1363_channels),
1085         .info = &max1363_info,
1086     },
1087     [max1364] = {
1088         .bits = 12,
1089         .int_vref_mv = 4096,
1090         .mode_list = max1363_mode_list,
1091         .num_modes = ARRAY_SIZE(max1363_mode_list),
1092         .default_mode = s0to3,
1093         .channels = max1363_channels,
1094         .num_channels = ARRAY_SIZE(max1363_channels),
1095         .info = &max1363_info,
1096     },
1097     [max1036] = {
1098         .bits = 8,
1099         .int_vref_mv = 4096,
1100         .mode_list = max1236_mode_list,
1101         .num_modes = ARRAY_SIZE(max1236_mode_list),
1102         .default_mode = s0to3,
1103         .info = &max1238_info,
1104         .channels = max1036_channels,
1105         .num_channels = ARRAY_SIZE(max1036_channels),
1106     },
1107     [max1037] = {
1108         .bits = 8,
1109         .int_vref_mv = 2048,
1110         .mode_list = max1236_mode_list,
1111         .num_modes = ARRAY_SIZE(max1236_mode_list),
1112         .default_mode = s0to3,
1113         .info = &max1238_info,
1114         .channels = max1036_channels,
1115         .num_channels = ARRAY_SIZE(max1036_channels),
1116     },
1117     [max1038] = {
1118         .bits = 8,
1119         .int_vref_mv = 4096,
1120         .mode_list = max1238_mode_list,
1121         .num_modes = ARRAY_SIZE(max1238_mode_list),
1122         .default_mode = s0to11,
1123         .info = &max1238_info,
1124         .channels = max1038_channels,
1125         .num_channels = ARRAY_SIZE(max1038_channels),
1126     },
1127     [max1039] = {
1128         .bits = 8,
1129         .int_vref_mv = 2048,
1130         .mode_list = max1238_mode_list,
1131         .num_modes = ARRAY_SIZE(max1238_mode_list),
1132         .default_mode = s0to11,
1133         .info = &max1238_info,
1134         .channels = max1038_channels,
1135         .num_channels = ARRAY_SIZE(max1038_channels),
1136     },
1137     [max1136] = {
1138         .bits = 10,
1139         .int_vref_mv = 4096,
1140         .mode_list = max1236_mode_list,
1141         .num_modes = ARRAY_SIZE(max1236_mode_list),
1142         .default_mode = s0to3,
1143         .info = &max1238_info,
1144         .channels = max1136_channels,
1145         .num_channels = ARRAY_SIZE(max1136_channels),
1146     },
1147     [max1137] = {
1148         .bits = 10,
1149         .int_vref_mv = 2048,
1150         .mode_list = max1236_mode_list,
1151         .num_modes = ARRAY_SIZE(max1236_mode_list),
1152         .default_mode = s0to3,
1153         .info = &max1238_info,
1154         .channels = max1136_channels,
1155         .num_channels = ARRAY_SIZE(max1136_channels),
1156     },
1157     [max1138] = {
1158         .bits = 10,
1159         .int_vref_mv = 4096,
1160         .mode_list = max1238_mode_list,
1161         .num_modes = ARRAY_SIZE(max1238_mode_list),
1162         .default_mode = s0to11,
1163         .info = &max1238_info,
1164         .channels = max1138_channels,
1165         .num_channels = ARRAY_SIZE(max1138_channels),
1166     },
1167     [max1139] = {
1168         .bits = 10,
1169         .int_vref_mv = 2048,
1170         .mode_list = max1238_mode_list,
1171         .num_modes = ARRAY_SIZE(max1238_mode_list),
1172         .default_mode = s0to11,
1173         .info = &max1238_info,
1174         .channels = max1138_channels,
1175         .num_channels = ARRAY_SIZE(max1138_channels),
1176     },
1177     [max1236] = {
1178         .bits = 12,
1179         .int_vref_mv = 4096,
1180         .mode_list = max1236_mode_list,
1181         .num_modes = ARRAY_SIZE(max1236_mode_list),
1182         .default_mode = s0to3,
1183         .info = &max1238_info,
1184         .channels = max1236_channels,
1185         .num_channels = ARRAY_SIZE(max1236_channels),
1186     },
1187     [max1237] = {
1188         .bits = 12,
1189         .int_vref_mv = 2048,
1190         .mode_list = max1236_mode_list,
1191         .num_modes = ARRAY_SIZE(max1236_mode_list),
1192         .default_mode = s0to3,
1193         .info = &max1238_info,
1194         .channels = max1236_channels,
1195         .num_channels = ARRAY_SIZE(max1236_channels),
1196     },
1197     [max1238] = {
1198         .bits = 12,
1199         .int_vref_mv = 4096,
1200         .mode_list = max1238_mode_list,
1201         .num_modes = ARRAY_SIZE(max1238_mode_list),
1202         .default_mode = s0to11,
1203         .info = &max1238_info,
1204         .channels = max1238_channels,
1205         .num_channels = ARRAY_SIZE(max1238_channels),
1206     },
1207     [max1239] = {
1208         .bits = 12,
1209         .int_vref_mv = 2048,
1210         .mode_list = max1238_mode_list,
1211         .num_modes = ARRAY_SIZE(max1238_mode_list),
1212         .default_mode = s0to11,
1213         .info = &max1238_info,
1214         .channels = max1238_channels,
1215         .num_channels = ARRAY_SIZE(max1238_channels),
1216     },
1217     [max11600] = {
1218         .bits = 8,
1219         .int_vref_mv = 4096,
1220         .mode_list = max11607_mode_list,
1221         .num_modes = ARRAY_SIZE(max11607_mode_list),
1222         .default_mode = s0to3,
1223         .info = &max1238_info,
1224         .channels = max1036_channels,
1225         .num_channels = ARRAY_SIZE(max1036_channels),
1226     },
1227     [max11601] = {
1228         .bits = 8,
1229         .int_vref_mv = 2048,
1230         .mode_list = max11607_mode_list,
1231         .num_modes = ARRAY_SIZE(max11607_mode_list),
1232         .default_mode = s0to3,
1233         .info = &max1238_info,
1234         .channels = max1036_channels,
1235         .num_channels = ARRAY_SIZE(max1036_channels),
1236     },
1237     [max11602] = {
1238         .bits = 8,
1239         .int_vref_mv = 4096,
1240         .mode_list = max11608_mode_list,
1241         .num_modes = ARRAY_SIZE(max11608_mode_list),
1242         .default_mode = s0to7,
1243         .info = &max1238_info,
1244         .channels = max11602_channels,
1245         .num_channels = ARRAY_SIZE(max11602_channels),
1246     },
1247     [max11603] = {
1248         .bits = 8,
1249         .int_vref_mv = 2048,
1250         .mode_list = max11608_mode_list,
1251         .num_modes = ARRAY_SIZE(max11608_mode_list),
1252         .default_mode = s0to7,
1253         .info = &max1238_info,
1254         .channels = max11602_channels,
1255         .num_channels = ARRAY_SIZE(max11602_channels),
1256     },
1257     [max11604] = {
1258         .bits = 8,
1259         .int_vref_mv = 4096,
1260         .mode_list = max1238_mode_list,
1261         .num_modes = ARRAY_SIZE(max1238_mode_list),
1262         .default_mode = s0to11,
1263         .info = &max1238_info,
1264         .channels = max1038_channels,
1265         .num_channels = ARRAY_SIZE(max1038_channels),
1266     },
1267     [max11605] = {
1268         .bits = 8,
1269         .int_vref_mv = 2048,
1270         .mode_list = max1238_mode_list,
1271         .num_modes = ARRAY_SIZE(max1238_mode_list),
1272         .default_mode = s0to11,
1273         .info = &max1238_info,
1274         .channels = max1038_channels,
1275         .num_channels = ARRAY_SIZE(max1038_channels),
1276     },
1277     [max11606] = {
1278         .bits = 10,
1279         .int_vref_mv = 4096,
1280         .mode_list = max11607_mode_list,
1281         .num_modes = ARRAY_SIZE(max11607_mode_list),
1282         .default_mode = s0to3,
1283         .info = &max1238_info,
1284         .channels = max1136_channels,
1285         .num_channels = ARRAY_SIZE(max1136_channels),
1286     },
1287     [max11607] = {
1288         .bits = 10,
1289         .int_vref_mv = 2048,
1290         .mode_list = max11607_mode_list,
1291         .num_modes = ARRAY_SIZE(max11607_mode_list),
1292         .default_mode = s0to3,
1293         .info = &max1238_info,
1294         .channels = max1136_channels,
1295         .num_channels = ARRAY_SIZE(max1136_channels),
1296     },
1297     [max11608] = {
1298         .bits = 10,
1299         .int_vref_mv = 4096,
1300         .mode_list = max11608_mode_list,
1301         .num_modes = ARRAY_SIZE(max11608_mode_list),
1302         .default_mode = s0to7,
1303         .info = &max1238_info,
1304         .channels = max11608_channels,
1305         .num_channels = ARRAY_SIZE(max11608_channels),
1306     },
1307     [max11609] = {
1308         .bits = 10,
1309         .int_vref_mv = 2048,
1310         .mode_list = max11608_mode_list,
1311         .num_modes = ARRAY_SIZE(max11608_mode_list),
1312         .default_mode = s0to7,
1313         .info = &max1238_info,
1314         .channels = max11608_channels,
1315         .num_channels = ARRAY_SIZE(max11608_channels),
1316     },
1317     [max11610] = {
1318         .bits = 10,
1319         .int_vref_mv = 4096,
1320         .mode_list = max1238_mode_list,
1321         .num_modes = ARRAY_SIZE(max1238_mode_list),
1322         .default_mode = s0to11,
1323         .info = &max1238_info,
1324         .channels = max1138_channels,
1325         .num_channels = ARRAY_SIZE(max1138_channels),
1326     },
1327     [max11611] = {
1328         .bits = 10,
1329         .int_vref_mv = 2048,
1330         .mode_list = max1238_mode_list,
1331         .num_modes = ARRAY_SIZE(max1238_mode_list),
1332         .default_mode = s0to11,
1333         .info = &max1238_info,
1334         .channels = max1138_channels,
1335         .num_channels = ARRAY_SIZE(max1138_channels),
1336     },
1337     [max11612] = {
1338         .bits = 12,
1339         .int_vref_mv = 4096,
1340         .mode_list = max11607_mode_list,
1341         .num_modes = ARRAY_SIZE(max11607_mode_list),
1342         .default_mode = s0to3,
1343         .info = &max1238_info,
1344         .channels = max1363_channels,
1345         .num_channels = ARRAY_SIZE(max1363_channels),
1346     },
1347     [max11613] = {
1348         .bits = 12,
1349         .int_vref_mv = 2048,
1350         .mode_list = max11607_mode_list,
1351         .num_modes = ARRAY_SIZE(max11607_mode_list),
1352         .default_mode = s0to3,
1353         .info = &max1238_info,
1354         .channels = max1363_channels,
1355         .num_channels = ARRAY_SIZE(max1363_channels),
1356     },
1357     [max11614] = {
1358         .bits = 12,
1359         .int_vref_mv = 4096,
1360         .mode_list = max11608_mode_list,
1361         .num_modes = ARRAY_SIZE(max11608_mode_list),
1362         .default_mode = s0to7,
1363         .info = &max1238_info,
1364         .channels = max11614_channels,
1365         .num_channels = ARRAY_SIZE(max11614_channels),
1366     },
1367     [max11615] = {
1368         .bits = 12,
1369         .int_vref_mv = 2048,
1370         .mode_list = max11608_mode_list,
1371         .num_modes = ARRAY_SIZE(max11608_mode_list),
1372         .default_mode = s0to7,
1373         .info = &max1238_info,
1374         .channels = max11614_channels,
1375         .num_channels = ARRAY_SIZE(max11614_channels),
1376     },
1377     [max11616] = {
1378         .bits = 12,
1379         .int_vref_mv = 4096,
1380         .mode_list = max1238_mode_list,
1381         .num_modes = ARRAY_SIZE(max1238_mode_list),
1382         .default_mode = s0to11,
1383         .info = &max1238_info,
1384         .channels = max1238_channels,
1385         .num_channels = ARRAY_SIZE(max1238_channels),
1386     },
1387     [max11617] = {
1388         .bits = 12,
1389         .int_vref_mv = 2048,
1390         .mode_list = max1238_mode_list,
1391         .num_modes = ARRAY_SIZE(max1238_mode_list),
1392         .default_mode = s0to11,
1393         .info = &max1238_info,
1394         .channels = max1238_channels,
1395         .num_channels = ARRAY_SIZE(max1238_channels),
1396     },
1397     [max11644] = {
1398         .bits = 12,
1399         .int_vref_mv = 4096,
1400         .mode_list = max11644_mode_list,
1401         .num_modes = ARRAY_SIZE(max11644_mode_list),
1402         .default_mode = s0to1,
1403         .info = &max1238_info,
1404         .channels = max11644_channels,
1405         .num_channels = ARRAY_SIZE(max11644_channels),
1406     },
1407     [max11645] = {
1408         .bits = 12,
1409         .int_vref_mv = 2048,
1410         .mode_list = max11644_mode_list,
1411         .num_modes = ARRAY_SIZE(max11644_mode_list),
1412         .default_mode = s0to1,
1413         .info = &max1238_info,
1414         .channels = max11644_channels,
1415         .num_channels = ARRAY_SIZE(max11644_channels),
1416     },
1417     [max11646] = {
1418         .bits = 10,
1419         .int_vref_mv = 4096,
1420         .mode_list = max11644_mode_list,
1421         .num_modes = ARRAY_SIZE(max11644_mode_list),
1422         .default_mode = s0to1,
1423         .info = &max1238_info,
1424         .channels = max11646_channels,
1425         .num_channels = ARRAY_SIZE(max11646_channels),
1426     },
1427     [max11647] = {
1428         .bits = 10,
1429         .int_vref_mv = 2048,
1430         .mode_list = max11644_mode_list,
1431         .num_modes = ARRAY_SIZE(max11644_mode_list),
1432         .default_mode = s0to1,
1433         .info = &max1238_info,
1434         .channels = max11646_channels,
1435         .num_channels = ARRAY_SIZE(max11646_channels),
1436     },
1437 };
1438 
1439 static int max1363_initial_setup(struct max1363_state *st)
1440 {
1441     st->setupbyte = MAX1363_SETUP_INT_CLOCK
1442         | MAX1363_SETUP_UNIPOLAR
1443         | MAX1363_SETUP_NORESET;
1444 
1445     if (st->vref)
1446         st->setupbyte |= MAX1363_SETUP_AIN3_IS_REF_EXT_TO_REF;
1447     else
1448         st->setupbyte |= MAX1363_SETUP_POWER_UP_INT_REF
1449           | MAX1363_SETUP_AIN3_IS_AIN3_REF_IS_INT;
1450 
1451     /* Set scan mode writes the config anyway so wait until then */
1452     st->setupbyte = MAX1363_SETUP_BYTE(st->setupbyte);
1453     st->current_mode = &max1363_mode_table[st->chip_info->default_mode];
1454     st->configbyte = MAX1363_CONFIG_BYTE(st->configbyte);
1455 
1456     return max1363_set_scan_mode(st);
1457 }
1458 
1459 static int max1363_alloc_scan_masks(struct iio_dev *indio_dev)
1460 {
1461     struct max1363_state *st = iio_priv(indio_dev);
1462     unsigned long *masks;
1463     int i;
1464 
1465     masks = devm_kzalloc(&indio_dev->dev,
1466             array3_size(BITS_TO_LONGS(MAX1363_MAX_CHANNELS),
1467                     sizeof(long),
1468                     st->chip_info->num_modes + 1),
1469             GFP_KERNEL);
1470     if (!masks)
1471         return -ENOMEM;
1472 
1473     for (i = 0; i < st->chip_info->num_modes; i++)
1474         bitmap_copy(masks + BITS_TO_LONGS(MAX1363_MAX_CHANNELS)*i,
1475                 max1363_mode_table[st->chip_info->mode_list[i]]
1476                 .modemask, MAX1363_MAX_CHANNELS);
1477 
1478     indio_dev->available_scan_masks = masks;
1479 
1480     return 0;
1481 }
1482 
1483 static irqreturn_t max1363_trigger_handler(int irq, void *p)
1484 {
1485     struct iio_poll_func *pf = p;
1486     struct iio_dev *indio_dev = pf->indio_dev;
1487     struct max1363_state *st = iio_priv(indio_dev);
1488     __u8 *rxbuf;
1489     int b_sent;
1490     size_t d_size;
1491     unsigned long numvals = bitmap_weight(st->current_mode->modemask,
1492                           MAX1363_MAX_CHANNELS);
1493 
1494     /* Ensure the timestamp is 8 byte aligned */
1495     if (st->chip_info->bits != 8)
1496         d_size = numvals*2;
1497     else
1498         d_size = numvals;
1499     if (indio_dev->scan_timestamp) {
1500         d_size += sizeof(s64);
1501         if (d_size % sizeof(s64))
1502             d_size += sizeof(s64) - (d_size % sizeof(s64));
1503     }
1504     /* Monitor mode prevents reading. Whilst not currently implemented
1505      * might as well have this test in here in the meantime as it does
1506      * no harm.
1507      */
1508     if (numvals == 0)
1509         goto done;
1510 
1511     rxbuf = kmalloc(d_size, GFP_KERNEL);
1512     if (rxbuf == NULL)
1513         goto done;
1514     if (st->chip_info->bits != 8)
1515         b_sent = st->recv(st->client, rxbuf, numvals * 2);
1516     else
1517         b_sent = st->recv(st->client, rxbuf, numvals);
1518     if (b_sent < 0)
1519         goto done_free;
1520 
1521     iio_push_to_buffers_with_timestamp(indio_dev, rxbuf,
1522                        iio_get_time_ns(indio_dev));
1523 
1524 done_free:
1525     kfree(rxbuf);
1526 done:
1527     iio_trigger_notify_done(indio_dev->trig);
1528 
1529     return IRQ_HANDLED;
1530 }
1531 
1532 #define MAX1363_COMPATIBLE(of_compatible, cfg) {        \
1533             .compatible = of_compatible,        \
1534             .data = &max1363_chip_info_tbl[cfg],    \
1535 }
1536 
1537 static const struct of_device_id max1363_of_match[] = {
1538     MAX1363_COMPATIBLE("maxim,max1361", max1361),
1539     MAX1363_COMPATIBLE("maxim,max1362", max1362),
1540     MAX1363_COMPATIBLE("maxim,max1363", max1363),
1541     MAX1363_COMPATIBLE("maxim,max1364", max1364),
1542     MAX1363_COMPATIBLE("maxim,max1036", max1036),
1543     MAX1363_COMPATIBLE("maxim,max1037", max1037),
1544     MAX1363_COMPATIBLE("maxim,max1038", max1038),
1545     MAX1363_COMPATIBLE("maxim,max1039", max1039),
1546     MAX1363_COMPATIBLE("maxim,max1136", max1136),
1547     MAX1363_COMPATIBLE("maxim,max1137", max1137),
1548     MAX1363_COMPATIBLE("maxim,max1138", max1138),
1549     MAX1363_COMPATIBLE("maxim,max1139", max1139),
1550     MAX1363_COMPATIBLE("maxim,max1236", max1236),
1551     MAX1363_COMPATIBLE("maxim,max1237", max1237),
1552     MAX1363_COMPATIBLE("maxim,max1238", max1238),
1553     MAX1363_COMPATIBLE("maxim,max1239", max1239),
1554     MAX1363_COMPATIBLE("maxim,max11600", max11600),
1555     MAX1363_COMPATIBLE("maxim,max11601", max11601),
1556     MAX1363_COMPATIBLE("maxim,max11602", max11602),
1557     MAX1363_COMPATIBLE("maxim,max11603", max11603),
1558     MAX1363_COMPATIBLE("maxim,max11604", max11604),
1559     MAX1363_COMPATIBLE("maxim,max11605", max11605),
1560     MAX1363_COMPATIBLE("maxim,max11606", max11606),
1561     MAX1363_COMPATIBLE("maxim,max11607", max11607),
1562     MAX1363_COMPATIBLE("maxim,max11608", max11608),
1563     MAX1363_COMPATIBLE("maxim,max11609", max11609),
1564     MAX1363_COMPATIBLE("maxim,max11610", max11610),
1565     MAX1363_COMPATIBLE("maxim,max11611", max11611),
1566     MAX1363_COMPATIBLE("maxim,max11612", max11612),
1567     MAX1363_COMPATIBLE("maxim,max11613", max11613),
1568     MAX1363_COMPATIBLE("maxim,max11614", max11614),
1569     MAX1363_COMPATIBLE("maxim,max11615", max11615),
1570     MAX1363_COMPATIBLE("maxim,max11616", max11616),
1571     MAX1363_COMPATIBLE("maxim,max11617", max11617),
1572     MAX1363_COMPATIBLE("maxim,max11644", max11644),
1573     MAX1363_COMPATIBLE("maxim,max11645", max11645),
1574     MAX1363_COMPATIBLE("maxim,max11646", max11646),
1575     MAX1363_COMPATIBLE("maxim,max11647", max11647),
1576     { /* sentinel */ }
1577 };
1578 MODULE_DEVICE_TABLE(of, max1363_of_match);
1579 
1580 static void max1363_reg_disable(void *reg)
1581 {
1582     regulator_disable(reg);
1583 }
1584 
1585 static int max1363_probe(struct i2c_client *client,
1586              const struct i2c_device_id *id)
1587 {
1588     int ret;
1589     struct max1363_state *st;
1590     struct iio_dev *indio_dev;
1591     struct regulator *vref;
1592 
1593     indio_dev = devm_iio_device_alloc(&client->dev,
1594                       sizeof(struct max1363_state));
1595     if (!indio_dev)
1596         return -ENOMEM;
1597 
1598     ret = devm_iio_map_array_register(&client->dev, indio_dev,
1599                       client->dev.platform_data);
1600     if (ret < 0)
1601         return ret;
1602 
1603     st = iio_priv(indio_dev);
1604 
1605     mutex_init(&st->lock);
1606     st->reg = devm_regulator_get(&client->dev, "vcc");
1607     if (IS_ERR(st->reg))
1608         return PTR_ERR(st->reg);
1609 
1610     ret = regulator_enable(st->reg);
1611     if (ret)
1612         return ret;
1613 
1614     ret = devm_add_action_or_reset(&client->dev, max1363_reg_disable, st->reg);
1615     if (ret)
1616         return ret;
1617 
1618     st->chip_info = device_get_match_data(&client->dev);
1619     if (!st->chip_info)
1620         st->chip_info = &max1363_chip_info_tbl[id->driver_data];
1621     st->client = client;
1622 
1623     st->vref_uv = st->chip_info->int_vref_mv * 1000;
1624     vref = devm_regulator_get_optional(&client->dev, "vref");
1625     if (!IS_ERR(vref)) {
1626         int vref_uv;
1627 
1628         ret = regulator_enable(vref);
1629         if (ret)
1630             return ret;
1631 
1632         ret = devm_add_action_or_reset(&client->dev, max1363_reg_disable, vref);
1633         if (ret)
1634             return ret;
1635 
1636         st->vref = vref;
1637         vref_uv = regulator_get_voltage(vref);
1638         if (vref_uv <= 0)
1639             return -EINVAL;
1640 
1641         st->vref_uv = vref_uv;
1642     }
1643 
1644     if (i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) {
1645         st->send = i2c_master_send;
1646         st->recv = i2c_master_recv;
1647     } else if (i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE)
1648             && st->chip_info->bits == 8) {
1649         st->send = max1363_smbus_send;
1650         st->recv = max1363_smbus_recv;
1651     } else {
1652         return -EOPNOTSUPP;
1653     }
1654 
1655     ret = max1363_alloc_scan_masks(indio_dev);
1656     if (ret)
1657         return ret;
1658 
1659     indio_dev->name = id->name;
1660     indio_dev->channels = st->chip_info->channels;
1661     indio_dev->num_channels = st->chip_info->num_channels;
1662     indio_dev->info = st->chip_info->info;
1663     indio_dev->modes = INDIO_DIRECT_MODE;
1664     ret = max1363_initial_setup(st);
1665     if (ret < 0)
1666         return ret;
1667 
1668     ret = devm_iio_triggered_buffer_setup(&client->dev, indio_dev, NULL,
1669                           &max1363_trigger_handler, NULL);
1670     if (ret)
1671         return ret;
1672 
1673     if (client->irq) {
1674         ret = devm_request_threaded_irq(&client->dev, st->client->irq,
1675                        NULL,
1676                        &max1363_event_handler,
1677                        IRQF_TRIGGER_RISING | IRQF_ONESHOT,
1678                        "max1363_event",
1679                        indio_dev);
1680 
1681         if (ret)
1682             return ret;
1683     }
1684 
1685     return devm_iio_device_register(&client->dev, indio_dev);
1686 }
1687 
1688 static const struct i2c_device_id max1363_id[] = {
1689     { "max1361", max1361 },
1690     { "max1362", max1362 },
1691     { "max1363", max1363 },
1692     { "max1364", max1364 },
1693     { "max1036", max1036 },
1694     { "max1037", max1037 },
1695     { "max1038", max1038 },
1696     { "max1039", max1039 },
1697     { "max1136", max1136 },
1698     { "max1137", max1137 },
1699     { "max1138", max1138 },
1700     { "max1139", max1139 },
1701     { "max1236", max1236 },
1702     { "max1237", max1237 },
1703     { "max1238", max1238 },
1704     { "max1239", max1239 },
1705     { "max11600", max11600 },
1706     { "max11601", max11601 },
1707     { "max11602", max11602 },
1708     { "max11603", max11603 },
1709     { "max11604", max11604 },
1710     { "max11605", max11605 },
1711     { "max11606", max11606 },
1712     { "max11607", max11607 },
1713     { "max11608", max11608 },
1714     { "max11609", max11609 },
1715     { "max11610", max11610 },
1716     { "max11611", max11611 },
1717     { "max11612", max11612 },
1718     { "max11613", max11613 },
1719     { "max11614", max11614 },
1720     { "max11615", max11615 },
1721     { "max11616", max11616 },
1722     { "max11617", max11617 },
1723     { "max11644", max11644 },
1724     { "max11645", max11645 },
1725     { "max11646", max11646 },
1726     { "max11647", max11647 },
1727     {}
1728 };
1729 
1730 MODULE_DEVICE_TABLE(i2c, max1363_id);
1731 
1732 static struct i2c_driver max1363_driver = {
1733     .driver = {
1734         .name = "max1363",
1735         .of_match_table = max1363_of_match,
1736     },
1737     .probe = max1363_probe,
1738     .id_table = max1363_id,
1739 };
1740 module_i2c_driver(max1363_driver);
1741 
1742 MODULE_AUTHOR("Jonathan Cameron <jic23@kernel.org>");
1743 MODULE_DESCRIPTION("Maxim 1363 ADC");
1744 MODULE_LICENSE("GPL v2");
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