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0001 // SPDX-License-Identifier: GPL-2.0-only
0002  /*
0003   * iio/adc/max1027.c
0004   * Copyright (C) 2014 Philippe Reynes
0005   *
0006   * based on linux/drivers/iio/ad7923.c
0007   * Copyright 2011 Analog Devices Inc (from AD7923 Driver)
0008   * Copyright 2012 CS Systemes d'Information
0009   *
0010   * max1027.c
0011   *
0012   * Partial support for max1027 and similar chips.
0013   */
0014 
0015 #include <linux/kernel.h>
0016 #include <linux/module.h>
0017 #include <linux/mod_devicetable.h>
0018 #include <linux/spi/spi.h>
0019 #include <linux/delay.h>
0020 
0021 #include <linux/iio/iio.h>
0022 #include <linux/iio/buffer.h>
0023 #include <linux/iio/trigger.h>
0024 #include <linux/iio/trigger_consumer.h>
0025 #include <linux/iio/triggered_buffer.h>
0026 
0027 #define MAX1027_CONV_REG  BIT(7)
0028 #define MAX1027_SETUP_REG BIT(6)
0029 #define MAX1027_AVG_REG   BIT(5)
0030 #define MAX1027_RST_REG   BIT(4)
0031 
0032 /* conversion register */
0033 #define MAX1027_TEMP      BIT(0)
0034 #define MAX1027_SCAN_0_N  (0x00 << 1)
0035 #define MAX1027_SCAN_N_M  (0x01 << 1)
0036 #define MAX1027_SCAN_N    (0x02 << 1)
0037 #define MAX1027_NOSCAN    (0x03 << 1)
0038 #define MAX1027_CHAN(n)   ((n) << 3)
0039 
0040 /* setup register */
0041 #define MAX1027_UNIPOLAR  0x02
0042 #define MAX1027_BIPOLAR   0x03
0043 #define MAX1027_REF_MODE0 (0x00 << 2)
0044 #define MAX1027_REF_MODE1 (0x01 << 2)
0045 #define MAX1027_REF_MODE2 (0x02 << 2)
0046 #define MAX1027_REF_MODE3 (0x03 << 2)
0047 #define MAX1027_CKS_MODE0 (0x00 << 4)
0048 #define MAX1027_CKS_MODE1 (0x01 << 4)
0049 #define MAX1027_CKS_MODE2 (0x02 << 4)
0050 #define MAX1027_CKS_MODE3 (0x03 << 4)
0051 
0052 /* averaging register */
0053 #define MAX1027_NSCAN_4   0x00
0054 #define MAX1027_NSCAN_8   0x01
0055 #define MAX1027_NSCAN_12  0x02
0056 #define MAX1027_NSCAN_16  0x03
0057 #define MAX1027_NAVG_4    (0x00 << 2)
0058 #define MAX1027_NAVG_8    (0x01 << 2)
0059 #define MAX1027_NAVG_16   (0x02 << 2)
0060 #define MAX1027_NAVG_32   (0x03 << 2)
0061 #define MAX1027_AVG_EN    BIT(4)
0062 
0063 /* Device can achieve 300ksps so we assume a 3.33us conversion delay */
0064 #define MAX1027_CONVERSION_UDELAY 4
0065 
0066 enum max1027_id {
0067     max1027,
0068     max1029,
0069     max1031,
0070     max1227,
0071     max1229,
0072     max1231,
0073 };
0074 
0075 static const struct spi_device_id max1027_id[] = {
0076     {"max1027", max1027},
0077     {"max1029", max1029},
0078     {"max1031", max1031},
0079     {"max1227", max1227},
0080     {"max1229", max1229},
0081     {"max1231", max1231},
0082     {}
0083 };
0084 MODULE_DEVICE_TABLE(spi, max1027_id);
0085 
0086 static const struct of_device_id max1027_adc_dt_ids[] = {
0087     { .compatible = "maxim,max1027" },
0088     { .compatible = "maxim,max1029" },
0089     { .compatible = "maxim,max1031" },
0090     { .compatible = "maxim,max1227" },
0091     { .compatible = "maxim,max1229" },
0092     { .compatible = "maxim,max1231" },
0093     {},
0094 };
0095 MODULE_DEVICE_TABLE(of, max1027_adc_dt_ids);
0096 
0097 #define MAX1027_V_CHAN(index, depth)                    \
0098     {                               \
0099         .type = IIO_VOLTAGE,                    \
0100         .indexed = 1,                       \
0101         .channel = index,                   \
0102         .info_mask_separate = BIT(IIO_CHAN_INFO_RAW),       \
0103         .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),   \
0104         .scan_index = index + 1,                \
0105         .scan_type = {                      \
0106             .sign = 'u',                    \
0107             .realbits = depth,              \
0108             .storagebits = 16,              \
0109             .shift = (depth == 10) ? 2 : 0,         \
0110             .endianness = IIO_BE,               \
0111         },                          \
0112     }
0113 
0114 #define MAX1027_T_CHAN                          \
0115     {                               \
0116         .type = IIO_TEMP,                   \
0117         .channel = 0,                       \
0118         .info_mask_separate = BIT(IIO_CHAN_INFO_RAW),       \
0119         .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),   \
0120         .scan_index = 0,                    \
0121         .scan_type = {                      \
0122             .sign = 'u',                    \
0123             .realbits = 12,                 \
0124             .storagebits = 16,              \
0125             .endianness = IIO_BE,               \
0126         },                          \
0127     }
0128 
0129 #define MAX1X27_CHANNELS(depth)         \
0130     MAX1027_T_CHAN,             \
0131     MAX1027_V_CHAN(0, depth),       \
0132     MAX1027_V_CHAN(1, depth),       \
0133     MAX1027_V_CHAN(2, depth),       \
0134     MAX1027_V_CHAN(3, depth),       \
0135     MAX1027_V_CHAN(4, depth),       \
0136     MAX1027_V_CHAN(5, depth),       \
0137     MAX1027_V_CHAN(6, depth),       \
0138     MAX1027_V_CHAN(7, depth)
0139 
0140 #define MAX1X29_CHANNELS(depth)         \
0141     MAX1X27_CHANNELS(depth),        \
0142     MAX1027_V_CHAN(8, depth),       \
0143     MAX1027_V_CHAN(9, depth),       \
0144     MAX1027_V_CHAN(10, depth),      \
0145     MAX1027_V_CHAN(11, depth)
0146 
0147 #define MAX1X31_CHANNELS(depth)         \
0148     MAX1X29_CHANNELS(depth),        \
0149     MAX1027_V_CHAN(12, depth),      \
0150     MAX1027_V_CHAN(13, depth),      \
0151     MAX1027_V_CHAN(14, depth),      \
0152     MAX1027_V_CHAN(15, depth)
0153 
0154 static const struct iio_chan_spec max1027_channels[] = {
0155     MAX1X27_CHANNELS(10),
0156 };
0157 
0158 static const struct iio_chan_spec max1029_channels[] = {
0159     MAX1X29_CHANNELS(10),
0160 };
0161 
0162 static const struct iio_chan_spec max1031_channels[] = {
0163     MAX1X31_CHANNELS(10),
0164 };
0165 
0166 static const struct iio_chan_spec max1227_channels[] = {
0167     MAX1X27_CHANNELS(12),
0168 };
0169 
0170 static const struct iio_chan_spec max1229_channels[] = {
0171     MAX1X29_CHANNELS(12),
0172 };
0173 
0174 static const struct iio_chan_spec max1231_channels[] = {
0175     MAX1X31_CHANNELS(12),
0176 };
0177 
0178 /*
0179  * These devices are able to scan from 0 to N, N being the highest voltage
0180  * channel requested by the user. The temperature can be included or not,
0181  * but cannot be retrieved alone. Based on the below
0182  * ->available_scan_masks, the core will select the most appropriate
0183  * ->active_scan_mask and the "minimum" number of channels will be
0184  * scanned and pushed to the buffers.
0185  *
0186  * For example, if the user wants channels 1, 4 and 5, all channels from
0187  * 0 to 5 will be scanned and pushed to the IIO buffers. The core will then
0188  * filter out the unneeded samples based on the ->active_scan_mask that has
0189  * been selected and only channels 1, 4 and 5 will be available to the user
0190  * in the shared buffer.
0191  */
0192 #define MAX1X27_SCAN_MASK_TEMP BIT(0)
0193 
0194 #define MAX1X27_SCAN_MASKS(temp)                    \
0195     GENMASK(1, 1 - (temp)), GENMASK(2, 1 - (temp)),         \
0196     GENMASK(3, 1 - (temp)), GENMASK(4, 1 - (temp)),         \
0197     GENMASK(5, 1 - (temp)), GENMASK(6, 1 - (temp)),         \
0198     GENMASK(7, 1 - (temp)), GENMASK(8, 1 - (temp))
0199 
0200 #define MAX1X29_SCAN_MASKS(temp)                    \
0201     MAX1X27_SCAN_MASKS(temp),                   \
0202     GENMASK(9, 1 - (temp)), GENMASK(10, 1 - (temp)),        \
0203     GENMASK(11, 1 - (temp)), GENMASK(12, 1 - (temp))
0204 
0205 #define MAX1X31_SCAN_MASKS(temp)                    \
0206     MAX1X29_SCAN_MASKS(temp),                   \
0207     GENMASK(13, 1 - (temp)), GENMASK(14, 1 - (temp)),       \
0208     GENMASK(15, 1 - (temp)), GENMASK(16, 1 - (temp))
0209 
0210 static const unsigned long max1027_available_scan_masks[] = {
0211     MAX1X27_SCAN_MASKS(0),
0212     MAX1X27_SCAN_MASKS(1),
0213     0x00000000,
0214 };
0215 
0216 static const unsigned long max1029_available_scan_masks[] = {
0217     MAX1X29_SCAN_MASKS(0),
0218     MAX1X29_SCAN_MASKS(1),
0219     0x00000000,
0220 };
0221 
0222 static const unsigned long max1031_available_scan_masks[] = {
0223     MAX1X31_SCAN_MASKS(0),
0224     MAX1X31_SCAN_MASKS(1),
0225     0x00000000,
0226 };
0227 
0228 struct max1027_chip_info {
0229     const struct iio_chan_spec *channels;
0230     unsigned int num_channels;
0231     const unsigned long *available_scan_masks;
0232 };
0233 
0234 static const struct max1027_chip_info max1027_chip_info_tbl[] = {
0235     [max1027] = {
0236         .channels = max1027_channels,
0237         .num_channels = ARRAY_SIZE(max1027_channels),
0238         .available_scan_masks = max1027_available_scan_masks,
0239     },
0240     [max1029] = {
0241         .channels = max1029_channels,
0242         .num_channels = ARRAY_SIZE(max1029_channels),
0243         .available_scan_masks = max1029_available_scan_masks,
0244     },
0245     [max1031] = {
0246         .channels = max1031_channels,
0247         .num_channels = ARRAY_SIZE(max1031_channels),
0248         .available_scan_masks = max1031_available_scan_masks,
0249     },
0250     [max1227] = {
0251         .channels = max1227_channels,
0252         .num_channels = ARRAY_SIZE(max1227_channels),
0253         .available_scan_masks = max1027_available_scan_masks,
0254     },
0255     [max1229] = {
0256         .channels = max1229_channels,
0257         .num_channels = ARRAY_SIZE(max1229_channels),
0258         .available_scan_masks = max1029_available_scan_masks,
0259     },
0260     [max1231] = {
0261         .channels = max1231_channels,
0262         .num_channels = ARRAY_SIZE(max1231_channels),
0263         .available_scan_masks = max1031_available_scan_masks,
0264     },
0265 };
0266 
0267 struct max1027_state {
0268     const struct max1027_chip_info  *info;
0269     struct spi_device       *spi;
0270     struct iio_trigger      *trig;
0271     __be16              *buffer;
0272     struct mutex            lock;
0273     struct completion       complete;
0274 
0275     u8              reg __aligned(IIO_DMA_MINALIGN);
0276 };
0277 
0278 static int max1027_wait_eoc(struct iio_dev *indio_dev)
0279 {
0280     struct max1027_state *st = iio_priv(indio_dev);
0281     unsigned int conversion_time = MAX1027_CONVERSION_UDELAY;
0282     int ret;
0283 
0284     if (st->spi->irq) {
0285         ret = wait_for_completion_timeout(&st->complete,
0286                           msecs_to_jiffies(1000));
0287         reinit_completion(&st->complete);
0288         if (!ret)
0289             return -ETIMEDOUT;
0290     } else {
0291         if (indio_dev->active_scan_mask)
0292             conversion_time *= hweight32(*indio_dev->active_scan_mask);
0293 
0294         usleep_range(conversion_time, conversion_time * 2);
0295     }
0296 
0297     return 0;
0298 }
0299 
0300 /* Scan from chan 0 to the highest requested channel. Include temperature on demand. */
0301 static int max1027_configure_chans_and_start(struct iio_dev *indio_dev)
0302 {
0303     struct max1027_state *st = iio_priv(indio_dev);
0304 
0305     st->reg = MAX1027_CONV_REG | MAX1027_SCAN_0_N;
0306     st->reg |= MAX1027_CHAN(fls(*indio_dev->active_scan_mask) - 2);
0307     if (*indio_dev->active_scan_mask & MAX1X27_SCAN_MASK_TEMP)
0308         st->reg |= MAX1027_TEMP;
0309 
0310     return spi_write(st->spi, &st->reg, 1);
0311 }
0312 
0313 static int max1027_enable_trigger(struct iio_dev *indio_dev, bool enable)
0314 {
0315     struct max1027_state *st = iio_priv(indio_dev);
0316 
0317     st->reg = MAX1027_SETUP_REG | MAX1027_REF_MODE2;
0318 
0319     /*
0320      * Start acquisition on:
0321      * MODE0: external hardware trigger wired to the cnvst input pin
0322      * MODE2: conversion register write
0323      */
0324     if (enable)
0325         st->reg |= MAX1027_CKS_MODE0;
0326     else
0327         st->reg |= MAX1027_CKS_MODE2;
0328 
0329     return spi_write(st->spi, &st->reg, 1);
0330 }
0331 
0332 static int max1027_read_single_value(struct iio_dev *indio_dev,
0333                      struct iio_chan_spec const *chan,
0334                      int *val)
0335 {
0336     int ret;
0337     struct max1027_state *st = iio_priv(indio_dev);
0338 
0339     ret = iio_device_claim_direct_mode(indio_dev);
0340     if (ret)
0341         return ret;
0342 
0343     /* Configure conversion register with the requested chan */
0344     st->reg = MAX1027_CONV_REG | MAX1027_CHAN(chan->channel) |
0345           MAX1027_NOSCAN;
0346     if (chan->type == IIO_TEMP)
0347         st->reg |= MAX1027_TEMP;
0348     ret = spi_write(st->spi, &st->reg, 1);
0349     if (ret < 0) {
0350         dev_err(&indio_dev->dev,
0351             "Failed to configure conversion register\n");
0352         goto release;
0353     }
0354 
0355     /*
0356      * For an unknown reason, when we use the mode "10" (write
0357      * conversion register), the interrupt doesn't occur every time.
0358      * So we just wait the maximum conversion time and deliver the value.
0359      */
0360     ret = max1027_wait_eoc(indio_dev);
0361     if (ret)
0362         goto release;
0363 
0364     /* Read result */
0365     ret = spi_read(st->spi, st->buffer, (chan->type == IIO_TEMP) ? 4 : 2);
0366 
0367 release:
0368     iio_device_release_direct_mode(indio_dev);
0369 
0370     if (ret < 0)
0371         return ret;
0372 
0373     *val = be16_to_cpu(st->buffer[0]);
0374 
0375     return IIO_VAL_INT;
0376 }
0377 
0378 static int max1027_read_raw(struct iio_dev *indio_dev,
0379                 struct iio_chan_spec const *chan,
0380                 int *val, int *val2, long mask)
0381 {
0382     int ret = 0;
0383     struct max1027_state *st = iio_priv(indio_dev);
0384 
0385     mutex_lock(&st->lock);
0386 
0387     switch (mask) {
0388     case IIO_CHAN_INFO_RAW:
0389         ret = max1027_read_single_value(indio_dev, chan, val);
0390         break;
0391     case IIO_CHAN_INFO_SCALE:
0392         switch (chan->type) {
0393         case IIO_TEMP:
0394             *val = 1;
0395             *val2 = 8;
0396             ret = IIO_VAL_FRACTIONAL;
0397             break;
0398         case IIO_VOLTAGE:
0399             *val = 2500;
0400             *val2 = chan->scan_type.realbits;
0401             ret = IIO_VAL_FRACTIONAL_LOG2;
0402             break;
0403         default:
0404             ret = -EINVAL;
0405             break;
0406         }
0407         break;
0408     default:
0409         ret = -EINVAL;
0410         break;
0411     }
0412 
0413     mutex_unlock(&st->lock);
0414 
0415     return ret;
0416 }
0417 
0418 static int max1027_debugfs_reg_access(struct iio_dev *indio_dev,
0419                       unsigned int reg, unsigned int writeval,
0420                       unsigned int *readval)
0421 {
0422     struct max1027_state *st = iio_priv(indio_dev);
0423     u8 *val = (u8 *)st->buffer;
0424 
0425     if (readval) {
0426         int ret = spi_read(st->spi, val, 2);
0427         *readval = be16_to_cpu(st->buffer[0]);
0428         return ret;
0429     }
0430 
0431     *val = (u8)writeval;
0432     return spi_write(st->spi, val, 1);
0433 }
0434 
0435 static int max1027_set_cnvst_trigger_state(struct iio_trigger *trig, bool state)
0436 {
0437     struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
0438     int ret;
0439 
0440     /*
0441      * In order to disable the convst trigger, start acquisition on
0442      * conversion register write, which basically disables triggering
0443      * conversions upon cnvst changes and thus has the effect of disabling
0444      * the external hardware trigger.
0445      */
0446     ret = max1027_enable_trigger(indio_dev, state);
0447     if (ret)
0448         return ret;
0449 
0450     if (state) {
0451         ret = max1027_configure_chans_and_start(indio_dev);
0452         if (ret)
0453             return ret;
0454     }
0455 
0456     return 0;
0457 }
0458 
0459 static int max1027_read_scan(struct iio_dev *indio_dev)
0460 {
0461     struct max1027_state *st = iio_priv(indio_dev);
0462     unsigned int scanned_chans;
0463     int ret;
0464 
0465     scanned_chans = fls(*indio_dev->active_scan_mask) - 1;
0466     if (*indio_dev->active_scan_mask & MAX1X27_SCAN_MASK_TEMP)
0467         scanned_chans++;
0468 
0469     /* fill buffer with all channel */
0470     ret = spi_read(st->spi, st->buffer, scanned_chans * 2);
0471     if (ret < 0)
0472         return ret;
0473 
0474     iio_push_to_buffers(indio_dev, st->buffer);
0475 
0476     return 0;
0477 }
0478 
0479 static irqreturn_t max1027_handler(int irq, void *private)
0480 {
0481     struct iio_dev *indio_dev = private;
0482     struct max1027_state *st = iio_priv(indio_dev);
0483 
0484     /*
0485      * If buffers are disabled (raw read) or when using external triggers,
0486      * we just need to unlock the waiters which will then handle the data.
0487      *
0488      * When using the internal trigger, we must hand-off the choice of the
0489      * handler to the core which will then lookup through the interrupt tree
0490      * for the right handler registered with iio_triggered_buffer_setup()
0491      * to execute, as this trigger might very well be used in conjunction
0492      * with another device. The core will then call the relevant handler to
0493      * perform the data processing step.
0494      */
0495     if (!iio_buffer_enabled(indio_dev))
0496         complete(&st->complete);
0497     else
0498         iio_trigger_poll(indio_dev->trig);
0499 
0500     return IRQ_HANDLED;
0501 }
0502 
0503 static irqreturn_t max1027_trigger_handler(int irq, void *private)
0504 {
0505     struct iio_poll_func *pf = private;
0506     struct iio_dev *indio_dev = pf->indio_dev;
0507     int ret;
0508 
0509     if (!iio_trigger_using_own(indio_dev)) {
0510         ret = max1027_configure_chans_and_start(indio_dev);
0511         if (ret)
0512             goto out;
0513 
0514         /* This is a threaded handler, it is fine to wait for an IRQ */
0515         ret = max1027_wait_eoc(indio_dev);
0516         if (ret)
0517             goto out;
0518     }
0519 
0520     ret = max1027_read_scan(indio_dev);
0521 out:
0522     if (ret)
0523         dev_err(&indio_dev->dev,
0524             "Cannot read scanned values (%d)\n", ret);
0525 
0526     iio_trigger_notify_done(indio_dev->trig);
0527 
0528     return IRQ_HANDLED;
0529 }
0530 
0531 static const struct iio_trigger_ops max1027_trigger_ops = {
0532     .validate_device = &iio_trigger_validate_own_device,
0533     .set_trigger_state = &max1027_set_cnvst_trigger_state,
0534 };
0535 
0536 static const struct iio_info max1027_info = {
0537     .read_raw = &max1027_read_raw,
0538     .debugfs_reg_access = &max1027_debugfs_reg_access,
0539 };
0540 
0541 static int max1027_probe(struct spi_device *spi)
0542 {
0543     int ret;
0544     struct iio_dev *indio_dev;
0545     struct max1027_state *st;
0546 
0547     indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
0548     if (!indio_dev) {
0549         pr_err("Can't allocate iio device\n");
0550         return -ENOMEM;
0551     }
0552 
0553     st = iio_priv(indio_dev);
0554     st->spi = spi;
0555     st->info = &max1027_chip_info_tbl[spi_get_device_id(spi)->driver_data];
0556 
0557     mutex_init(&st->lock);
0558     init_completion(&st->complete);
0559 
0560     indio_dev->name = spi_get_device_id(spi)->name;
0561     indio_dev->info = &max1027_info;
0562     indio_dev->modes = INDIO_DIRECT_MODE;
0563     indio_dev->channels = st->info->channels;
0564     indio_dev->num_channels = st->info->num_channels;
0565     indio_dev->available_scan_masks = st->info->available_scan_masks;
0566 
0567     st->buffer = devm_kmalloc_array(&indio_dev->dev,
0568                     indio_dev->num_channels, 2,
0569                     GFP_KERNEL);
0570     if (!st->buffer)
0571         return -ENOMEM;
0572 
0573     /* Enable triggered buffers */
0574     ret = devm_iio_triggered_buffer_setup(&spi->dev, indio_dev,
0575                           &iio_pollfunc_store_time,
0576                           &max1027_trigger_handler,
0577                           NULL);
0578     if (ret < 0) {
0579         dev_err(&indio_dev->dev, "Failed to setup buffer\n");
0580         return ret;
0581     }
0582 
0583     /* If there is an EOC interrupt, register the cnvst hardware trigger */
0584     if (spi->irq) {
0585         st->trig = devm_iio_trigger_alloc(&spi->dev, "%s-trigger",
0586                           indio_dev->name);
0587         if (!st->trig) {
0588             ret = -ENOMEM;
0589             dev_err(&indio_dev->dev,
0590                 "Failed to allocate iio trigger\n");
0591             return ret;
0592         }
0593 
0594         st->trig->ops = &max1027_trigger_ops;
0595         iio_trigger_set_drvdata(st->trig, indio_dev);
0596         ret = devm_iio_trigger_register(&indio_dev->dev,
0597                         st->trig);
0598         if (ret < 0) {
0599             dev_err(&indio_dev->dev,
0600                 "Failed to register iio trigger\n");
0601             return ret;
0602         }
0603 
0604         ret = devm_request_irq(&spi->dev, spi->irq, max1027_handler,
0605                        IRQF_TRIGGER_FALLING,
0606                        spi->dev.driver->name, indio_dev);
0607         if (ret < 0) {
0608             dev_err(&indio_dev->dev, "Failed to allocate IRQ.\n");
0609             return ret;
0610         }
0611     }
0612 
0613     /* Internal reset */
0614     st->reg = MAX1027_RST_REG;
0615     ret = spi_write(st->spi, &st->reg, 1);
0616     if (ret < 0) {
0617         dev_err(&indio_dev->dev, "Failed to reset the ADC\n");
0618         return ret;
0619     }
0620 
0621     /* Disable averaging */
0622     st->reg = MAX1027_AVG_REG;
0623     ret = spi_write(st->spi, &st->reg, 1);
0624     if (ret < 0) {
0625         dev_err(&indio_dev->dev, "Failed to configure averaging register\n");
0626         return ret;
0627     }
0628 
0629     /* Assume conversion on register write for now */
0630     ret = max1027_enable_trigger(indio_dev, false);
0631     if (ret)
0632         return ret;
0633 
0634     return devm_iio_device_register(&spi->dev, indio_dev);
0635 }
0636 
0637 static struct spi_driver max1027_driver = {
0638     .driver = {
0639         .name   = "max1027",
0640         .of_match_table = max1027_adc_dt_ids,
0641     },
0642     .probe      = max1027_probe,
0643     .id_table   = max1027_id,
0644 };
0645 module_spi_driver(max1027_driver);
0646 
0647 MODULE_AUTHOR("Philippe Reynes <tremyfr@yahoo.fr>");
0648 MODULE_DESCRIPTION("MAX1X27/MAX1X29/MAX1X31 ADC");
0649 MODULE_LICENSE("GPL v2");
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