iio/adc/lpc32xx_adc.c

0001 // SPDX-License-Identifier: GPL-2.0+
0002 /*
0003  *  lpc32xx_adc.c - Support for ADC in LPC32XX
0004  *
0005  *  3-channel, 10-bit ADC
0006  *
0007  *  Copyright (C) 2011, 2012 Roland Stigge <stigge@antcom.de>
0008  */
0009
0010 #include <linux/clk.h>
0011 #include <linux/completion.h>
0012 #include <linux/err.h>
0013 #include <linux/iio/iio.h>
0014 #include <linux/interrupt.h>
0015 #include <linux/io.h>
0016 #include <linux/module.h>
0017 #include <linux/mod_devicetable.h>
0018 #include <linux/platform_device.h>
0019 #include <linux/regulator/consumer.h>
0020
0021 /*
0022  * LPC32XX registers definitions
0023  */
0024 #define LPC32XXAD_SELECT(x) ((x) + 0x04)
0025 #define LPC32XXAD_CTRL(x)   ((x) + 0x08)
0026 #define LPC32XXAD_VALUE(x)  ((x) + 0x48)
0027
0028 /* Bit definitions for LPC32XXAD_SELECT: */
0029 /* constant, always write this value! */
0030 #define LPC32XXAD_REFm         0x00000200
0031 /* constant, always write this value! */
0032 #define LPC32XXAD_REFp      0x00000080
0033  /* multiple of this is the channel number: 0, 1, 2 */
0034 #define LPC32XXAD_IN        0x00000010
0035 /* constant, always write this value! */
0036 #define LPC32XXAD_INTERNAL  0x00000004
0037
0038 /* Bit definitions for LPC32XXAD_CTRL: */
0039 #define LPC32XXAD_STROBE    0x00000002
0040 #define LPC32XXAD_PDN_CTRL  0x00000004
0041
0042 /* Bit definitions for LPC32XXAD_VALUE: */
0043 #define LPC32XXAD_VALUE_MASK    0x000003FF
0044
0045 #define LPC32XXAD_NAME "lpc32xx-adc"
0046
0047 struct lpc32xx_adc_state {
0048     void __iomem *adc_base;
0049     struct clk *clk;
0050     struct completion completion;
0051     struct regulator *vref;
0052
0053     u32 value;
0054 };
0055
0056 static int lpc32xx_read_raw(struct iio_dev *indio_dev,
0057                 struct iio_chan_spec const *chan,
0058                 int *val,
0059                 int *val2,
0060                 long mask)
0061 {
0062     struct lpc32xx_adc_state *st = iio_priv(indio_dev);
0063     int ret;
0064
0065     switch (mask) {
0066     case IIO_CHAN_INFO_RAW:
0067         mutex_lock(&indio_dev->mlock);
0068         ret = clk_prepare_enable(st->clk);
0069         if (ret) {
0070             mutex_unlock(&indio_dev->mlock);
0071             return ret;
0072         }
0073         /* Measurement setup */
0074         __raw_writel(LPC32XXAD_INTERNAL | (chan->address) |
0075                  LPC32XXAD_REFp | LPC32XXAD_REFm,
0076                  LPC32XXAD_SELECT(st->adc_base));
0077         /* Trigger conversion */
0078         __raw_writel(LPC32XXAD_PDN_CTRL | LPC32XXAD_STROBE,
0079                  LPC32XXAD_CTRL(st->adc_base));
0080         wait_for_completion(&st->completion); /* set by ISR */
0081         clk_disable_unprepare(st->clk);
0082         *val = st->value;
0083         mutex_unlock(&indio_dev->mlock);
0084
0085         return IIO_VAL_INT;
0086
0087     case IIO_CHAN_INFO_SCALE:
0088         *val = regulator_get_voltage(st->vref) / 1000;
0089         *val2 =  10;
0090
0091         return IIO_VAL_FRACTIONAL_LOG2;
0092     default:
0093         return -EINVAL;
0094     }
0095 }
0096
0097 static const struct iio_info lpc32xx_adc_iio_info = {
0098     .read_raw = &lpc32xx_read_raw,
0099 };
0100
0101 #define LPC32XX_ADC_CHANNEL_BASE(_index)        \
0102     .type = IIO_VOLTAGE,                \
0103     .indexed = 1,                   \
0104     .channel = _index,              \
0105     .info_mask_separate = BIT(IIO_CHAN_INFO_RAW),   \
0106     .address = LPC32XXAD_IN * _index,       \
0107     .scan_index = _index,
0108
0109 #define LPC32XX_ADC_CHANNEL(_index) {       \
0110     LPC32XX_ADC_CHANNEL_BASE(_index)    \
0111 }
0112
0113 #define LPC32XX_ADC_SCALE_CHANNEL(_index) {         \
0114     LPC32XX_ADC_CHANNEL_BASE(_index)            \
0115     .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE)    \
0116 }
0117
0118 static const struct iio_chan_spec lpc32xx_adc_iio_channels[] = {
0119     LPC32XX_ADC_CHANNEL(0),
0120     LPC32XX_ADC_CHANNEL(1),
0121     LPC32XX_ADC_CHANNEL(2),
0122 };
0123
0124 static const struct iio_chan_spec lpc32xx_adc_iio_scale_channels[] = {
0125     LPC32XX_ADC_SCALE_CHANNEL(0),
0126     LPC32XX_ADC_SCALE_CHANNEL(1),
0127     LPC32XX_ADC_SCALE_CHANNEL(2),
0128 };
0129
0130 static irqreturn_t lpc32xx_adc_isr(int irq, void *dev_id)
0131 {
0132     struct lpc32xx_adc_state *st = dev_id;
0133
0134     /* Read value and clear irq */
0135     st->value = __raw_readl(LPC32XXAD_VALUE(st->adc_base)) &
0136         LPC32XXAD_VALUE_MASK;
0137     complete(&st->completion);
0138
0139     return IRQ_HANDLED;
0140 }
0141
0142 static int lpc32xx_adc_probe(struct platform_device *pdev)
0143 {
0144     struct lpc32xx_adc_state *st = NULL;
0145     struct resource *res;
0146     int retval = -ENODEV;
0147     struct iio_dev *iodev = NULL;
0148     int irq;
0149
0150     res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
0151     if (!res) {
0152         dev_err(&pdev->dev, "failed to get platform I/O memory\n");
0153         return -ENXIO;
0154     }
0155
0156     iodev = devm_iio_device_alloc(&pdev->dev, sizeof(*st));
0157     if (!iodev)
0158         return -ENOMEM;
0159
0160     st = iio_priv(iodev);
0161
0162     st->adc_base = devm_ioremap(&pdev->dev, res->start,
0163                     resource_size(res));
0164     if (!st->adc_base) {
0165         dev_err(&pdev->dev, "failed mapping memory\n");
0166         return -EBUSY;
0167     }
0168
0169     st->clk = devm_clk_get(&pdev->dev, NULL);
0170     if (IS_ERR(st->clk)) {
0171         dev_err(&pdev->dev, "failed getting clock\n");
0172         return PTR_ERR(st->clk);
0173     }
0174
0175     irq = platform_get_irq(pdev, 0);
0176     if (irq <= 0)
0177         return -ENXIO;
0178
0179     retval = devm_request_irq(&pdev->dev, irq, lpc32xx_adc_isr, 0,
0180                   LPC32XXAD_NAME, st);
0181     if (retval < 0) {
0182         dev_err(&pdev->dev, "failed requesting interrupt\n");
0183         return retval;
0184     }
0185
0186     st->vref = devm_regulator_get(&pdev->dev, "vref");
0187     if (IS_ERR(st->vref)) {
0188         iodev->channels = lpc32xx_adc_iio_channels;
0189         dev_info(&pdev->dev,
0190              "Missing vref regulator: No scaling available\n");
0191     } else {
0192         iodev->channels = lpc32xx_adc_iio_scale_channels;
0193     }
0194
0195     platform_set_drvdata(pdev, iodev);
0196
0197     init_completion(&st->completion);
0198
0199     iodev->name = LPC32XXAD_NAME;
0200     iodev->info = &lpc32xx_adc_iio_info;
0201     iodev->modes = INDIO_DIRECT_MODE;
0202     iodev->num_channels = ARRAY_SIZE(lpc32xx_adc_iio_channels);
0203
0204     retval = devm_iio_device_register(&pdev->dev, iodev);
0205     if (retval)
0206         return retval;
0207
0208     dev_info(&pdev->dev, "LPC32XX ADC driver loaded, IRQ %d\n", irq);
0209
0210     return 0;
0211 }
0212
0213 static const struct of_device_id lpc32xx_adc_match[] = {
0214     { .compatible = "nxp,lpc3220-adc" },
0215     {},
0216 };
0217 MODULE_DEVICE_TABLE(of, lpc32xx_adc_match);
0218
0219 static struct platform_driver lpc32xx_adc_driver = {
0220     .probe      = lpc32xx_adc_probe,
0221     .driver     = {
0222         .name   = LPC32XXAD_NAME,
0223         .of_match_table = lpc32xx_adc_match,
0224     },
0225 };
0226
0227 module_platform_driver(lpc32xx_adc_driver);
0228
0229 MODULE_AUTHOR("Roland Stigge <stigge@antcom.de>");
0230 MODULE_DESCRIPTION("LPC32XX ADC driver");
0231 MODULE_LICENSE("GPL");