iio/adc/lpc18xx_adc.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * IIO ADC driver for NXP LPC18xx ADC
0004  *
0005  * Copyright (C) 2016 Joachim Eastwood <manabian@gmail.com>
0006  *
0007  * UNSUPPORTED hardware features:
0008  *  - Hardware triggers
0009  *  - Burst mode
0010  *  - Interrupts
0011  *  - DMA
0012  */
0013
0014 #include <linux/clk.h>
0015 #include <linux/err.h>
0016 #include <linux/iio/iio.h>
0017 #include <linux/iio/driver.h>
0018 #include <linux/io.h>
0019 #include <linux/iopoll.h>
0020 #include <linux/mod_devicetable.h>
0021 #include <linux/module.h>
0022 #include <linux/mutex.h>
0023 #include <linux/platform_device.h>
0024 #include <linux/regulator/consumer.h>
0025
0026 /* LPC18XX ADC registers and bits */
0027 #define LPC18XX_ADC_CR          0x000
0028 #define  LPC18XX_ADC_CR_CLKDIV_SHIFT    8
0029 #define  LPC18XX_ADC_CR_PDN     BIT(21)
0030 #define  LPC18XX_ADC_CR_START_NOW   (0x1 << 24)
0031 #define LPC18XX_ADC_GDR         0x004
0032
0033 /* Data register bits */
0034 #define LPC18XX_ADC_SAMPLE_SHIFT    6
0035 #define LPC18XX_ADC_SAMPLE_MASK     0x3ff
0036 #define LPC18XX_ADC_CONV_DONE       BIT(31)
0037
0038 /* Clock should be 4.5 MHz or less */
0039 #define LPC18XX_ADC_CLK_TARGET      4500000
0040
0041 struct lpc18xx_adc {
0042     struct regulator *vref;
0043     void __iomem *base;
0044     struct device *dev;
0045     struct mutex lock;
0046     struct clk *clk;
0047     u32 cr_reg;
0048 };
0049
0050 #define LPC18XX_ADC_CHAN(_idx) {                \
0051     .type = IIO_VOLTAGE,                    \
0052     .indexed = 1,                       \
0053     .channel = _idx,                    \
0054     .info_mask_separate = BIT(IIO_CHAN_INFO_RAW),       \
0055     .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),   \
0056 }
0057
0058 static const struct iio_chan_spec lpc18xx_adc_iio_channels[] = {
0059     LPC18XX_ADC_CHAN(0),
0060     LPC18XX_ADC_CHAN(1),
0061     LPC18XX_ADC_CHAN(2),
0062     LPC18XX_ADC_CHAN(3),
0063     LPC18XX_ADC_CHAN(4),
0064     LPC18XX_ADC_CHAN(5),
0065     LPC18XX_ADC_CHAN(6),
0066     LPC18XX_ADC_CHAN(7),
0067 };
0068
0069 static int lpc18xx_adc_read_chan(struct lpc18xx_adc *adc, unsigned int ch)
0070 {
0071     int ret;
0072     u32 reg;
0073
0074     reg = adc->cr_reg | BIT(ch) | LPC18XX_ADC_CR_START_NOW;
0075     writel(reg, adc->base + LPC18XX_ADC_CR);
0076
0077     ret = readl_poll_timeout(adc->base + LPC18XX_ADC_GDR, reg,
0078                  reg & LPC18XX_ADC_CONV_DONE, 3, 9);
0079     if (ret) {
0080         dev_warn(adc->dev, "adc read timed out\n");
0081         return ret;
0082     }
0083
0084     return (reg >> LPC18XX_ADC_SAMPLE_SHIFT) & LPC18XX_ADC_SAMPLE_MASK;
0085 }
0086
0087 static int lpc18xx_adc_read_raw(struct iio_dev *indio_dev,
0088                 struct iio_chan_spec const *chan,
0089                 int *val, int *val2, long mask)
0090 {
0091     struct lpc18xx_adc *adc = iio_priv(indio_dev);
0092
0093     switch (mask) {
0094     case IIO_CHAN_INFO_RAW:
0095         mutex_lock(&adc->lock);
0096         *val = lpc18xx_adc_read_chan(adc, chan->channel);
0097         mutex_unlock(&adc->lock);
0098         if (*val < 0)
0099             return *val;
0100
0101         return IIO_VAL_INT;
0102
0103     case IIO_CHAN_INFO_SCALE:
0104         *val = regulator_get_voltage(adc->vref) / 1000;
0105         *val2 = 10;
0106
0107         return IIO_VAL_FRACTIONAL_LOG2;
0108     }
0109
0110     return -EINVAL;
0111 }
0112
0113 static const struct iio_info lpc18xx_adc_info = {
0114     .read_raw = lpc18xx_adc_read_raw,
0115 };
0116
0117 static void lpc18xx_clear_cr_reg(void *data)
0118 {
0119     struct lpc18xx_adc *adc = data;
0120
0121     writel(0, adc->base + LPC18XX_ADC_CR);
0122 }
0123
0124 static void lpc18xx_clk_disable(void *clk)
0125 {
0126     clk_disable_unprepare(clk);
0127 }
0128
0129 static void lpc18xx_regulator_disable(void *vref)
0130 {
0131     regulator_disable(vref);
0132 }
0133
0134 static int lpc18xx_adc_probe(struct platform_device *pdev)
0135 {
0136     struct iio_dev *indio_dev;
0137     struct lpc18xx_adc *adc;
0138     unsigned int clkdiv;
0139     unsigned long rate;
0140     int ret;
0141
0142     indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*adc));
0143     if (!indio_dev)
0144         return -ENOMEM;
0145
0146     adc = iio_priv(indio_dev);
0147     adc->dev = &pdev->dev;
0148     mutex_init(&adc->lock);
0149
0150     adc->base = devm_platform_ioremap_resource(pdev, 0);
0151     if (IS_ERR(adc->base))
0152         return PTR_ERR(adc->base);
0153
0154     adc->clk = devm_clk_get(&pdev->dev, NULL);
0155     if (IS_ERR(adc->clk))
0156         return dev_err_probe(&pdev->dev, PTR_ERR(adc->clk),
0157                      "error getting clock\n");
0158
0159     adc->vref = devm_regulator_get(&pdev->dev, "vref");
0160     if (IS_ERR(adc->vref))
0161         return dev_err_probe(&pdev->dev, PTR_ERR(adc->vref),
0162                      "error getting regulator\n");
0163
0164     indio_dev->name = dev_name(&pdev->dev);
0165     indio_dev->info = &lpc18xx_adc_info;
0166     indio_dev->modes = INDIO_DIRECT_MODE;
0167     indio_dev->channels = lpc18xx_adc_iio_channels;
0168     indio_dev->num_channels = ARRAY_SIZE(lpc18xx_adc_iio_channels);
0169
0170     ret = regulator_enable(adc->vref);
0171     if (ret) {
0172         dev_err(&pdev->dev, "unable to enable regulator\n");
0173         return ret;
0174     }
0175
0176     ret = devm_add_action_or_reset(&pdev->dev, lpc18xx_regulator_disable, adc->vref);
0177     if (ret)
0178         return ret;
0179
0180     ret = clk_prepare_enable(adc->clk);
0181     if (ret) {
0182         dev_err(&pdev->dev, "unable to enable clock\n");
0183         return ret;
0184     }
0185
0186     ret = devm_add_action_or_reset(&pdev->dev, lpc18xx_clk_disable,
0187                        adc->clk);
0188     if (ret)
0189         return ret;
0190
0191     rate = clk_get_rate(adc->clk);
0192     clkdiv = DIV_ROUND_UP(rate, LPC18XX_ADC_CLK_TARGET);
0193
0194     adc->cr_reg = (clkdiv << LPC18XX_ADC_CR_CLKDIV_SHIFT) |
0195             LPC18XX_ADC_CR_PDN;
0196     writel(adc->cr_reg, adc->base + LPC18XX_ADC_CR);
0197
0198     ret = devm_add_action_or_reset(&pdev->dev, lpc18xx_clear_cr_reg, adc);
0199     if (ret)
0200         return ret;
0201
0202     return devm_iio_device_register(&pdev->dev, indio_dev);
0203 }
0204
0205 static const struct of_device_id lpc18xx_adc_match[] = {
0206     { .compatible = "nxp,lpc1850-adc" },
0207     { /* sentinel */ }
0208 };
0209 MODULE_DEVICE_TABLE(of, lpc18xx_adc_match);
0210
0211 static struct platform_driver lpc18xx_adc_driver = {
0212     .probe  = lpc18xx_adc_probe,
0213     .driver = {
0214         .name = "lpc18xx-adc",
0215         .of_match_table = lpc18xx_adc_match,
0216     },
0217 };
0218 module_platform_driver(lpc18xx_adc_driver);
0219
0220 MODULE_DESCRIPTION("LPC18xx ADC driver");
0221 MODULE_AUTHOR("Joachim Eastwood <manabian@gmail.com>");
0222 MODULE_LICENSE("GPL v2");