iio/adc/imx8qxp-adc.c

0001 // SPDX-License-Identifier: GPL-2.0+
0002 /*
0003  * NXP i.MX8QXP ADC driver
0004  *
0005  * Based on the work of Haibo Chen <haibo.chen@nxp.com>
0006  * The initial developer of the original code is Haibo Chen.
0007  * Portions created by Haibo Chen are Copyright (C) 2018 NXP.
0008  * All Rights Reserved.
0009  *
0010  * Copyright (C) 2018 NXP
0011  * Copyright (C) 2021 Cai Huoqing
0012  */
0013 #include <linux/bitfield.h>
0014 #include <linux/bits.h>
0015 #include <linux/clk.h>
0016 #include <linux/completion.h>
0017 #include <linux/delay.h>
0018 #include <linux/err.h>
0019 #include <linux/interrupt.h>
0020 #include <linux/io.h>
0021 #include <linux/kernel.h>
0022 #include <linux/mod_devicetable.h>
0023 #include <linux/module.h>
0024 #include <linux/platform_device.h>
0025 #include <linux/pm_runtime.h>
0026 #include <linux/regulator/consumer.h>
0027
0028 #include <linux/iio/iio.h>
0029
0030 #define ADC_DRIVER_NAME     "imx8qxp-adc"
0031
0032 /* Register map definition */
0033 #define IMX8QXP_ADR_ADC_CTRL        0x10
0034 #define IMX8QXP_ADR_ADC_STAT        0x14
0035 #define IMX8QXP_ADR_ADC_IE      0x18
0036 #define IMX8QXP_ADR_ADC_DE      0x1c
0037 #define IMX8QXP_ADR_ADC_CFG     0x20
0038 #define IMX8QXP_ADR_ADC_FCTRL       0x30
0039 #define IMX8QXP_ADR_ADC_SWTRIG      0x34
0040 #define IMX8QXP_ADR_ADC_TCTRL(tid)  (0xc0 + (tid) * 4)
0041 #define IMX8QXP_ADR_ADC_CMDH(cid)   (0x100 + (cid) * 8)
0042 #define IMX8QXP_ADR_ADC_CMDL(cid)   (0x104 + (cid) * 8)
0043 #define IMX8QXP_ADR_ADC_RESFIFO     0x300
0044 #define IMX8QXP_ADR_ADC_TST     0xffc
0045
0046 /* ADC bit shift */
0047 #define IMX8QXP_ADC_IE_FWMIE_MASK       GENMASK(1, 0)
0048 #define IMX8QXP_ADC_CTRL_FIFO_RESET_MASK    BIT(8)
0049 #define IMX8QXP_ADC_CTRL_SOFTWARE_RESET_MASK    BIT(1)
0050 #define IMX8QXP_ADC_CTRL_ADC_EN_MASK        BIT(0)
0051 #define IMX8QXP_ADC_TCTRL_TCMD_MASK     GENMASK(31, 24)
0052 #define IMX8QXP_ADC_TCTRL_TDLY_MASK     GENMASK(23, 16)
0053 #define IMX8QXP_ADC_TCTRL_TPRI_MASK     GENMASK(15, 8)
0054 #define IMX8QXP_ADC_TCTRL_HTEN_MASK     GENMASK(7, 0)
0055 #define IMX8QXP_ADC_CMDL_CSCALE_MASK        GENMASK(13, 8)
0056 #define IMX8QXP_ADC_CMDL_MODE_MASK      BIT(7)
0057 #define IMX8QXP_ADC_CMDL_DIFF_MASK      BIT(6)
0058 #define IMX8QXP_ADC_CMDL_ABSEL_MASK     BIT(5)
0059 #define IMX8QXP_ADC_CMDL_ADCH_MASK      GENMASK(2, 0)
0060 #define IMX8QXP_ADC_CMDH_NEXT_MASK      GENMASK(31, 24)
0061 #define IMX8QXP_ADC_CMDH_LOOP_MASK      GENMASK(23, 16)
0062 #define IMX8QXP_ADC_CMDH_AVGS_MASK      GENMASK(15, 12)
0063 #define IMX8QXP_ADC_CMDH_STS_MASK       BIT(8)
0064 #define IMX8QXP_ADC_CMDH_LWI_MASK       GENMASK(7, 7)
0065 #define IMX8QXP_ADC_CMDH_CMPEN_MASK     GENMASK(0, 0)
0066 #define IMX8QXP_ADC_CFG_PWREN_MASK      BIT(28)
0067 #define IMX8QXP_ADC_CFG_PUDLY_MASK      GENMASK(23, 16)
0068 #define IMX8QXP_ADC_CFG_REFSEL_MASK     GENMASK(7, 6)
0069 #define IMX8QXP_ADC_CFG_PWRSEL_MASK     GENMASK(5, 4)
0070 #define IMX8QXP_ADC_CFG_TPRICTRL_MASK       GENMASK(3, 0)
0071 #define IMX8QXP_ADC_FCTRL_FWMARK_MASK       GENMASK(20, 16)
0072 #define IMX8QXP_ADC_FCTRL_FCOUNT_MASK       GENMASK(4, 0)
0073 #define IMX8QXP_ADC_RESFIFO_VAL_MASK        GENMASK(18, 3)
0074
0075 /* ADC PARAMETER*/
0076 #define IMX8QXP_ADC_CMDL_CHANNEL_SCALE_FULL     GENMASK(5, 0)
0077 #define IMX8QXP_ADC_CMDL_SEL_A_A_B_CHANNEL      0
0078 #define IMX8QXP_ADC_CMDL_STANDARD_RESOLUTION        0
0079 #define IMX8QXP_ADC_CMDL_MODE_SINGLE            0
0080 #define IMX8QXP_ADC_CMDH_LWI_INCREMENT_DIS      0
0081 #define IMX8QXP_ADC_CMDH_CMPEN_DIS          0
0082 #define IMX8QXP_ADC_PAUSE_EN                BIT(31)
0083 #define IMX8QXP_ADC_TCTRL_TPRI_PRIORITY_HIGH        0
0084
0085 #define IMX8QXP_ADC_TCTRL_HTEN_HW_TIRG_DIS      0
0086
0087 #define IMX8QXP_ADC_TIMEOUT     msecs_to_jiffies(100)
0088
0089 struct imx8qxp_adc {
0090     struct device *dev;
0091     void __iomem *regs;
0092     struct clk *clk;
0093     struct clk *ipg_clk;
0094     struct regulator *vref;
0095     /* Serialise ADC channel reads */
0096     struct mutex lock;
0097     struct completion completion;
0098 };
0099
0100 #define IMX8QXP_ADC_CHAN(_idx) {                \
0101     .type = IIO_VOLTAGE,                    \
0102     .indexed = 1,                       \
0103     .channel = (_idx),                  \
0104     .info_mask_separate = BIT(IIO_CHAN_INFO_RAW),       \
0105     .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) |  \
0106                 BIT(IIO_CHAN_INFO_SAMP_FREQ),   \
0107 }
0108
0109 static const struct iio_chan_spec imx8qxp_adc_iio_channels[] = {
0110     IMX8QXP_ADC_CHAN(0),
0111     IMX8QXP_ADC_CHAN(1),
0112     IMX8QXP_ADC_CHAN(2),
0113     IMX8QXP_ADC_CHAN(3),
0114     IMX8QXP_ADC_CHAN(4),
0115     IMX8QXP_ADC_CHAN(5),
0116     IMX8QXP_ADC_CHAN(6),
0117     IMX8QXP_ADC_CHAN(7),
0118 };
0119
0120 static void imx8qxp_adc_reset(struct imx8qxp_adc *adc)
0121 {
0122     u32 ctrl;
0123
0124     /*software reset, need to clear the set bit*/
0125     ctrl = readl(adc->regs + IMX8QXP_ADR_ADC_CTRL);
0126     ctrl |= FIELD_PREP(IMX8QXP_ADC_CTRL_SOFTWARE_RESET_MASK, 1);
0127     writel(ctrl, adc->regs + IMX8QXP_ADR_ADC_CTRL);
0128     udelay(10);
0129     ctrl &= ~FIELD_PREP(IMX8QXP_ADC_CTRL_SOFTWARE_RESET_MASK, 1);
0130     writel(ctrl, adc->regs + IMX8QXP_ADR_ADC_CTRL);
0131
0132     /* reset the fifo */
0133     ctrl |= FIELD_PREP(IMX8QXP_ADC_CTRL_FIFO_RESET_MASK, 1);
0134     writel(ctrl, adc->regs + IMX8QXP_ADR_ADC_CTRL);
0135 }
0136
0137 static void imx8qxp_adc_reg_config(struct imx8qxp_adc *adc, int channel)
0138 {
0139     u32 adc_cfg, adc_tctrl, adc_cmdl, adc_cmdh;
0140
0141     /* ADC configuration */
0142     adc_cfg = FIELD_PREP(IMX8QXP_ADC_CFG_PWREN_MASK, 1) |
0143           FIELD_PREP(IMX8QXP_ADC_CFG_PUDLY_MASK, 0x80)|
0144           FIELD_PREP(IMX8QXP_ADC_CFG_REFSEL_MASK, 0) |
0145           FIELD_PREP(IMX8QXP_ADC_CFG_PWRSEL_MASK, 3) |
0146           FIELD_PREP(IMX8QXP_ADC_CFG_TPRICTRL_MASK, 0);
0147     writel(adc_cfg, adc->regs + IMX8QXP_ADR_ADC_CFG);
0148
0149     /* config the trigger control */
0150     adc_tctrl = FIELD_PREP(IMX8QXP_ADC_TCTRL_TCMD_MASK, 1) |
0151             FIELD_PREP(IMX8QXP_ADC_TCTRL_TDLY_MASK, 0) |
0152             FIELD_PREP(IMX8QXP_ADC_TCTRL_TPRI_MASK, IMX8QXP_ADC_TCTRL_TPRI_PRIORITY_HIGH) |
0153             FIELD_PREP(IMX8QXP_ADC_TCTRL_HTEN_MASK, IMX8QXP_ADC_TCTRL_HTEN_HW_TIRG_DIS);
0154     writel(adc_tctrl, adc->regs + IMX8QXP_ADR_ADC_TCTRL(0));
0155
0156     /* config the cmd */
0157     adc_cmdl = FIELD_PREP(IMX8QXP_ADC_CMDL_CSCALE_MASK, IMX8QXP_ADC_CMDL_CHANNEL_SCALE_FULL) |
0158            FIELD_PREP(IMX8QXP_ADC_CMDL_MODE_MASK, IMX8QXP_ADC_CMDL_STANDARD_RESOLUTION) |
0159            FIELD_PREP(IMX8QXP_ADC_CMDL_DIFF_MASK, IMX8QXP_ADC_CMDL_MODE_SINGLE) |
0160            FIELD_PREP(IMX8QXP_ADC_CMDL_ABSEL_MASK, IMX8QXP_ADC_CMDL_SEL_A_A_B_CHANNEL) |
0161            FIELD_PREP(IMX8QXP_ADC_CMDL_ADCH_MASK, channel);
0162     writel(adc_cmdl, adc->regs + IMX8QXP_ADR_ADC_CMDL(0));
0163
0164     adc_cmdh = FIELD_PREP(IMX8QXP_ADC_CMDH_NEXT_MASK, 0) |
0165            FIELD_PREP(IMX8QXP_ADC_CMDH_LOOP_MASK, 0) |
0166            FIELD_PREP(IMX8QXP_ADC_CMDH_AVGS_MASK, 7) |
0167            FIELD_PREP(IMX8QXP_ADC_CMDH_STS_MASK, 0) |
0168            FIELD_PREP(IMX8QXP_ADC_CMDH_LWI_MASK, IMX8QXP_ADC_CMDH_LWI_INCREMENT_DIS) |
0169            FIELD_PREP(IMX8QXP_ADC_CMDH_CMPEN_MASK, IMX8QXP_ADC_CMDH_CMPEN_DIS);
0170     writel(adc_cmdh, adc->regs + IMX8QXP_ADR_ADC_CMDH(0));
0171 }
0172
0173 static void imx8qxp_adc_fifo_config(struct imx8qxp_adc *adc)
0174 {
0175     u32 fifo_ctrl, interrupt_en;
0176
0177     fifo_ctrl = readl(adc->regs + IMX8QXP_ADR_ADC_FCTRL);
0178     fifo_ctrl &= ~IMX8QXP_ADC_FCTRL_FWMARK_MASK;
0179     /* set the watermark level to 1 */
0180     fifo_ctrl |= FIELD_PREP(IMX8QXP_ADC_FCTRL_FWMARK_MASK, 0);
0181     writel(fifo_ctrl, adc->regs + IMX8QXP_ADR_ADC_FCTRL);
0182
0183     /* FIFO Watermark Interrupt Enable */
0184     interrupt_en = readl(adc->regs + IMX8QXP_ADR_ADC_IE);
0185     interrupt_en |= FIELD_PREP(IMX8QXP_ADC_IE_FWMIE_MASK, 1);
0186     writel(interrupt_en, adc->regs + IMX8QXP_ADR_ADC_IE);
0187 }
0188
0189 static void imx8qxp_adc_disable(struct imx8qxp_adc *adc)
0190 {
0191     u32 ctrl;
0192
0193     ctrl = readl(adc->regs + IMX8QXP_ADR_ADC_CTRL);
0194     ctrl &= ~FIELD_PREP(IMX8QXP_ADC_CTRL_ADC_EN_MASK, 1);
0195     writel(ctrl, adc->regs + IMX8QXP_ADR_ADC_CTRL);
0196 }
0197
0198 static int imx8qxp_adc_read_raw(struct iio_dev *indio_dev,
0199                 struct iio_chan_spec const *chan,
0200                 int *val, int *val2, long mask)
0201 {
0202     struct imx8qxp_adc *adc = iio_priv(indio_dev);
0203     struct device *dev = adc->dev;
0204
0205     u32 ctrl, vref_uv;
0206     long ret;
0207
0208     switch (mask) {
0209     case IIO_CHAN_INFO_RAW:
0210         pm_runtime_get_sync(dev);
0211
0212         mutex_lock(&adc->lock);
0213         reinit_completion(&adc->completion);
0214
0215         imx8qxp_adc_reg_config(adc, chan->channel);
0216
0217         imx8qxp_adc_fifo_config(adc);
0218
0219         /* adc enable */
0220         ctrl = readl(adc->regs + IMX8QXP_ADR_ADC_CTRL);
0221         ctrl |= FIELD_PREP(IMX8QXP_ADC_CTRL_ADC_EN_MASK, 1);
0222         writel(ctrl, adc->regs + IMX8QXP_ADR_ADC_CTRL);
0223         /* adc start */
0224         writel(1, adc->regs + IMX8QXP_ADR_ADC_SWTRIG);
0225
0226         ret = wait_for_completion_interruptible_timeout(&adc->completion,
0227                                 IMX8QXP_ADC_TIMEOUT);
0228
0229         pm_runtime_mark_last_busy(dev);
0230         pm_runtime_put_sync_autosuspend(dev);
0231
0232         if (ret == 0) {
0233             mutex_unlock(&adc->lock);
0234             return -ETIMEDOUT;
0235         }
0236         if (ret < 0) {
0237             mutex_unlock(&adc->lock);
0238             return ret;
0239         }
0240
0241         *val = FIELD_GET(IMX8QXP_ADC_RESFIFO_VAL_MASK,
0242                  readl(adc->regs + IMX8QXP_ADR_ADC_RESFIFO));
0243
0244         mutex_unlock(&adc->lock);
0245         return IIO_VAL_INT;
0246
0247     case IIO_CHAN_INFO_SCALE:
0248         vref_uv = regulator_get_voltage(adc->vref);
0249         *val = vref_uv / 1000;
0250         *val2 = 12;
0251         return IIO_VAL_FRACTIONAL_LOG2;
0252
0253     case IIO_CHAN_INFO_SAMP_FREQ:
0254         *val = clk_get_rate(adc->clk) / 3;
0255         return IIO_VAL_INT;
0256
0257     default:
0258         return -EINVAL;
0259     }
0260 }
0261
0262 static irqreturn_t imx8qxp_adc_isr(int irq, void *dev_id)
0263 {
0264     struct imx8qxp_adc *adc = dev_id;
0265     u32 fifo_count;
0266
0267     fifo_count = FIELD_GET(IMX8QXP_ADC_FCTRL_FCOUNT_MASK,
0268                    readl(adc->regs + IMX8QXP_ADR_ADC_FCTRL));
0269
0270     if (fifo_count)
0271         complete(&adc->completion);
0272
0273     return IRQ_HANDLED;
0274 }
0275
0276 static int imx8qxp_adc_reg_access(struct iio_dev *indio_dev, unsigned int reg,
0277                   unsigned int writeval, unsigned int *readval)
0278 {
0279     struct imx8qxp_adc *adc = iio_priv(indio_dev);
0280     struct device *dev = adc->dev;
0281
0282     if (!readval || reg % 4 || reg > IMX8QXP_ADR_ADC_TST)
0283         return -EINVAL;
0284
0285     pm_runtime_get_sync(dev);
0286
0287     *readval = readl(adc->regs + reg);
0288
0289     pm_runtime_mark_last_busy(dev);
0290     pm_runtime_put_sync_autosuspend(dev);
0291
0292     return 0;
0293 }
0294
0295 static const struct iio_info imx8qxp_adc_iio_info = {
0296     .read_raw = &imx8qxp_adc_read_raw,
0297     .debugfs_reg_access = &imx8qxp_adc_reg_access,
0298 };
0299
0300 static int imx8qxp_adc_probe(struct platform_device *pdev)
0301 {
0302     struct imx8qxp_adc *adc;
0303     struct iio_dev *indio_dev;
0304     struct device *dev = &pdev->dev;
0305     int irq;
0306     int ret;
0307
0308     indio_dev = devm_iio_device_alloc(dev, sizeof(*adc));
0309     if (!indio_dev) {
0310         dev_err(dev, "Failed allocating iio device\n");
0311         return -ENOMEM;
0312     }
0313
0314     adc = iio_priv(indio_dev);
0315     adc->dev = dev;
0316
0317     mutex_init(&adc->lock);
0318     adc->regs = devm_platform_ioremap_resource(pdev, 0);
0319     if (IS_ERR(adc->regs))
0320         return PTR_ERR(adc->regs);
0321
0322     irq = platform_get_irq(pdev, 0);
0323     if (irq < 0)
0324         return irq;
0325
0326     adc->clk = devm_clk_get(dev, "per");
0327     if (IS_ERR(adc->clk))
0328         return dev_err_probe(dev, PTR_ERR(adc->clk), "Failed getting clock\n");
0329
0330     adc->ipg_clk = devm_clk_get(dev, "ipg");
0331     if (IS_ERR(adc->ipg_clk))
0332         return dev_err_probe(dev, PTR_ERR(adc->ipg_clk), "Failed getting clock\n");
0333
0334     adc->vref = devm_regulator_get(dev, "vref");
0335     if (IS_ERR(adc->vref))
0336         return dev_err_probe(dev, PTR_ERR(adc->vref), "Failed getting reference voltage\n");
0337
0338     ret = regulator_enable(adc->vref);
0339     if (ret) {
0340         dev_err(dev, "Can't enable adc reference top voltage\n");
0341         return ret;
0342     }
0343
0344     platform_set_drvdata(pdev, indio_dev);
0345
0346     init_completion(&adc->completion);
0347
0348     indio_dev->name = ADC_DRIVER_NAME;
0349     indio_dev->info = &imx8qxp_adc_iio_info;
0350     indio_dev->modes = INDIO_DIRECT_MODE;
0351     indio_dev->channels = imx8qxp_adc_iio_channels;
0352     indio_dev->num_channels = ARRAY_SIZE(imx8qxp_adc_iio_channels);
0353
0354     ret = clk_prepare_enable(adc->clk);
0355     if (ret) {
0356         dev_err(&pdev->dev, "Could not prepare or enable the clock.\n");
0357         goto error_regulator_disable;
0358     }
0359
0360     ret = clk_prepare_enable(adc->ipg_clk);
0361     if (ret) {
0362         dev_err(&pdev->dev, "Could not prepare or enable the clock.\n");
0363         goto error_adc_clk_disable;
0364     }
0365
0366     ret = devm_request_irq(dev, irq, imx8qxp_adc_isr, 0, ADC_DRIVER_NAME, adc);
0367     if (ret < 0) {
0368         dev_err(dev, "Failed requesting irq, irq = %d\n", irq);
0369         goto error_ipg_clk_disable;
0370     }
0371
0372     imx8qxp_adc_reset(adc);
0373
0374     ret = iio_device_register(indio_dev);
0375     if (ret) {
0376         imx8qxp_adc_disable(adc);
0377         dev_err(dev, "Couldn't register the device.\n");
0378         goto error_ipg_clk_disable;
0379     }
0380
0381     pm_runtime_set_active(dev);
0382     pm_runtime_set_autosuspend_delay(dev, 50);
0383     pm_runtime_use_autosuspend(dev);
0384     pm_runtime_enable(dev);
0385
0386     return 0;
0387
0388 error_ipg_clk_disable:
0389     clk_disable_unprepare(adc->ipg_clk);
0390 error_adc_clk_disable:
0391     clk_disable_unprepare(adc->clk);
0392 error_regulator_disable:
0393     regulator_disable(adc->vref);
0394
0395     return ret;
0396 }
0397
0398 static int imx8qxp_adc_remove(struct platform_device *pdev)
0399 {
0400     struct iio_dev *indio_dev = platform_get_drvdata(pdev);
0401     struct imx8qxp_adc *adc = iio_priv(indio_dev);
0402     struct device *dev = adc->dev;
0403
0404     pm_runtime_get_sync(dev);
0405
0406     iio_device_unregister(indio_dev);
0407
0408     imx8qxp_adc_disable(adc);
0409
0410     clk_disable_unprepare(adc->clk);
0411     clk_disable_unprepare(adc->ipg_clk);
0412     regulator_disable(adc->vref);
0413
0414     pm_runtime_disable(dev);
0415     pm_runtime_put_noidle(dev);
0416
0417     return 0;
0418 }
0419
0420 static int imx8qxp_adc_runtime_suspend(struct device *dev)
0421 {
0422     struct iio_dev *indio_dev = dev_get_drvdata(dev);
0423     struct imx8qxp_adc *adc = iio_priv(indio_dev);
0424
0425     imx8qxp_adc_disable(adc);
0426
0427     clk_disable_unprepare(adc->clk);
0428     clk_disable_unprepare(adc->ipg_clk);
0429     regulator_disable(adc->vref);
0430
0431     return 0;
0432 }
0433
0434 static int imx8qxp_adc_runtime_resume(struct device *dev)
0435 {
0436     struct iio_dev *indio_dev = dev_get_drvdata(dev);
0437     struct imx8qxp_adc *adc = iio_priv(indio_dev);
0438     int ret;
0439
0440     ret = regulator_enable(adc->vref);
0441     if (ret) {
0442         dev_err(dev, "Can't enable adc reference top voltage, err = %d\n", ret);
0443         return ret;
0444     }
0445
0446     ret = clk_prepare_enable(adc->clk);
0447     if (ret) {
0448         dev_err(dev, "Could not prepare or enable clock.\n");
0449         goto err_disable_reg;
0450     }
0451
0452     ret = clk_prepare_enable(adc->ipg_clk);
0453     if (ret) {
0454         dev_err(dev, "Could not prepare or enable clock.\n");
0455         goto err_unprepare_clk;
0456     }
0457
0458     imx8qxp_adc_reset(adc);
0459
0460     return 0;
0461
0462 err_unprepare_clk:
0463     clk_disable_unprepare(adc->clk);
0464
0465 err_disable_reg:
0466     regulator_disable(adc->vref);
0467
0468     return ret;
0469 }
0470
0471 static DEFINE_RUNTIME_DEV_PM_OPS(imx8qxp_adc_pm_ops,
0472                  imx8qxp_adc_runtime_suspend,
0473                  imx8qxp_adc_runtime_resume, NULL);
0474
0475 static const struct of_device_id imx8qxp_adc_match[] = {
0476     { .compatible = "nxp,imx8qxp-adc", },
0477     { /* sentinel */ }
0478 };
0479 MODULE_DEVICE_TABLE(of, imx8qxp_adc_match);
0480
0481 static struct platform_driver imx8qxp_adc_driver = {
0482     .probe      = imx8qxp_adc_probe,
0483     .remove     = imx8qxp_adc_remove,
0484     .driver     = {
0485         .name   = ADC_DRIVER_NAME,
0486         .of_match_table = imx8qxp_adc_match,
0487         .pm = pm_ptr(&imx8qxp_adc_pm_ops),
0488     },
0489 };
0490
0491 module_platform_driver(imx8qxp_adc_driver);
0492
0493 MODULE_DESCRIPTION("i.MX8QuadXPlus ADC driver");
0494 MODULE_LICENSE("GPL v2");