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0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Holt Integrated Circuits HI-8435 threshold detector driver
0004  *
0005  * Copyright (C) 2015 Zodiac Inflight Innovations
0006  * Copyright (C) 2015 Cogent Embedded, Inc.
0007  */
0008 
0009 #include <linux/delay.h>
0010 #include <linux/iio/events.h>
0011 #include <linux/iio/iio.h>
0012 #include <linux/iio/sysfs.h>
0013 #include <linux/iio/trigger.h>
0014 #include <linux/iio/trigger_consumer.h>
0015 #include <linux/iio/triggered_event.h>
0016 #include <linux/interrupt.h>
0017 #include <linux/module.h>
0018 #include <linux/mod_devicetable.h>
0019 #include <linux/spi/spi.h>
0020 #include <linux/gpio/consumer.h>
0021 
0022 #define DRV_NAME "hi8435"
0023 
0024 /* Register offsets for HI-8435 */
0025 #define HI8435_CTRL_REG     0x02
0026 #define HI8435_PSEN_REG     0x04
0027 #define HI8435_TMDATA_REG   0x1E
0028 #define HI8435_GOCENHYS_REG 0x3A
0029 #define HI8435_SOCENHYS_REG 0x3C
0030 #define HI8435_SO7_0_REG    0x10
0031 #define HI8435_SO15_8_REG   0x12
0032 #define HI8435_SO23_16_REG  0x14
0033 #define HI8435_SO31_24_REG  0x16
0034 #define HI8435_SO31_0_REG   0x78
0035 
0036 #define HI8435_WRITE_OPCODE 0x00
0037 #define HI8435_READ_OPCODE  0x80
0038 
0039 /* CTRL register bits */
0040 #define HI8435_CTRL_TEST    0x01
0041 #define HI8435_CTRL_SRST    0x02
0042 
0043 struct hi8435_priv {
0044     struct spi_device *spi;
0045     struct mutex lock;
0046 
0047     unsigned long event_scan_mask; /* soft mask/unmask channels events */
0048     unsigned int event_prev_val;
0049 
0050     unsigned threshold_lo[2]; /* GND-Open and Supply-Open thresholds */
0051     unsigned threshold_hi[2]; /* GND-Open and Supply-Open thresholds */
0052     u8 reg_buffer[3] __aligned(IIO_DMA_MINALIGN);
0053 };
0054 
0055 static int hi8435_readb(struct hi8435_priv *priv, u8 reg, u8 *val)
0056 {
0057     reg |= HI8435_READ_OPCODE;
0058     return spi_write_then_read(priv->spi, &reg, 1, val, 1);
0059 }
0060 
0061 static int hi8435_readw(struct hi8435_priv *priv, u8 reg, u16 *val)
0062 {
0063     int ret;
0064     __be16 be_val;
0065 
0066     reg |= HI8435_READ_OPCODE;
0067     ret = spi_write_then_read(priv->spi, &reg, 1, &be_val, 2);
0068     *val = be16_to_cpu(be_val);
0069 
0070     return ret;
0071 }
0072 
0073 static int hi8435_readl(struct hi8435_priv *priv, u8 reg, u32 *val)
0074 {
0075     int ret;
0076     __be32 be_val;
0077 
0078     reg |= HI8435_READ_OPCODE;
0079     ret = spi_write_then_read(priv->spi, &reg, 1, &be_val, 4);
0080     *val = be32_to_cpu(be_val);
0081 
0082     return ret;
0083 }
0084 
0085 static int hi8435_writeb(struct hi8435_priv *priv, u8 reg, u8 val)
0086 {
0087     priv->reg_buffer[0] = reg | HI8435_WRITE_OPCODE;
0088     priv->reg_buffer[1] = val;
0089 
0090     return spi_write(priv->spi, priv->reg_buffer, 2);
0091 }
0092 
0093 static int hi8435_writew(struct hi8435_priv *priv, u8 reg, u16 val)
0094 {
0095     priv->reg_buffer[0] = reg | HI8435_WRITE_OPCODE;
0096     priv->reg_buffer[1] = (val >> 8) & 0xff;
0097     priv->reg_buffer[2] = val & 0xff;
0098 
0099     return spi_write(priv->spi, priv->reg_buffer, 3);
0100 }
0101 
0102 static int hi8435_read_raw(struct iio_dev *idev,
0103                const struct iio_chan_spec *chan,
0104                int *val, int *val2, long mask)
0105 {
0106     struct hi8435_priv *priv = iio_priv(idev);
0107     u32 tmp;
0108     int ret;
0109 
0110     switch (mask) {
0111     case IIO_CHAN_INFO_RAW:
0112         ret = hi8435_readl(priv, HI8435_SO31_0_REG, &tmp);
0113         if (ret < 0)
0114             return ret;
0115         *val = !!(tmp & BIT(chan->channel));
0116         return IIO_VAL_INT;
0117     default:
0118         return -EINVAL;
0119     }
0120 }
0121 
0122 static int hi8435_read_event_config(struct iio_dev *idev,
0123                     const struct iio_chan_spec *chan,
0124                     enum iio_event_type type,
0125                     enum iio_event_direction dir)
0126 {
0127     struct hi8435_priv *priv = iio_priv(idev);
0128 
0129     return !!(priv->event_scan_mask & BIT(chan->channel));
0130 }
0131 
0132 static int hi8435_write_event_config(struct iio_dev *idev,
0133                      const struct iio_chan_spec *chan,
0134                      enum iio_event_type type,
0135                      enum iio_event_direction dir, int state)
0136 {
0137     struct hi8435_priv *priv = iio_priv(idev);
0138     int ret;
0139     u32 tmp;
0140 
0141     if (state) {
0142         ret = hi8435_readl(priv, HI8435_SO31_0_REG, &tmp);
0143         if (ret < 0)
0144             return ret;
0145         if (tmp & BIT(chan->channel))
0146             priv->event_prev_val |= BIT(chan->channel);
0147         else
0148             priv->event_prev_val &= ~BIT(chan->channel);
0149 
0150         priv->event_scan_mask |= BIT(chan->channel);
0151     } else
0152         priv->event_scan_mask &= ~BIT(chan->channel);
0153 
0154     return 0;
0155 }
0156 
0157 static int hi8435_read_event_value(struct iio_dev *idev,
0158                    const struct iio_chan_spec *chan,
0159                    enum iio_event_type type,
0160                    enum iio_event_direction dir,
0161                    enum iio_event_info info,
0162                    int *val, int *val2)
0163 {
0164     struct hi8435_priv *priv = iio_priv(idev);
0165     int ret;
0166     u8 mode, psen;
0167     u16 reg;
0168 
0169     ret = hi8435_readb(priv, HI8435_PSEN_REG, &psen);
0170     if (ret < 0)
0171         return ret;
0172 
0173     /* Supply-Open or GND-Open sensing mode */
0174     mode = !!(psen & BIT(chan->channel / 8));
0175 
0176     ret = hi8435_readw(priv, mode ? HI8435_SOCENHYS_REG :
0177                  HI8435_GOCENHYS_REG, &reg);
0178     if (ret < 0)
0179         return ret;
0180 
0181     if (dir == IIO_EV_DIR_FALLING)
0182         *val = ((reg & 0xff) - (reg >> 8)) / 2;
0183     else if (dir == IIO_EV_DIR_RISING)
0184         *val = ((reg & 0xff) + (reg >> 8)) / 2;
0185 
0186     return IIO_VAL_INT;
0187 }
0188 
0189 static int hi8435_write_event_value(struct iio_dev *idev,
0190                     const struct iio_chan_spec *chan,
0191                     enum iio_event_type type,
0192                     enum iio_event_direction dir,
0193                     enum iio_event_info info,
0194                     int val, int val2)
0195 {
0196     struct hi8435_priv *priv = iio_priv(idev);
0197     int ret;
0198     u8 mode, psen;
0199     u16 reg;
0200 
0201     ret = hi8435_readb(priv, HI8435_PSEN_REG, &psen);
0202     if (ret < 0)
0203         return ret;
0204 
0205     /* Supply-Open or GND-Open sensing mode */
0206     mode = !!(psen & BIT(chan->channel / 8));
0207 
0208     ret = hi8435_readw(priv, mode ? HI8435_SOCENHYS_REG :
0209                  HI8435_GOCENHYS_REG, &reg);
0210     if (ret < 0)
0211         return ret;
0212 
0213     if (dir == IIO_EV_DIR_FALLING) {
0214         /* falling threshold range 2..21V, hysteresis minimum 2V */
0215         if (val < 2 || val > 21 || (val + 2) > priv->threshold_hi[mode])
0216             return -EINVAL;
0217 
0218         if (val == priv->threshold_lo[mode])
0219             return 0;
0220 
0221         priv->threshold_lo[mode] = val;
0222 
0223         /* hysteresis must not be odd */
0224         if ((priv->threshold_hi[mode] - priv->threshold_lo[mode]) % 2)
0225             priv->threshold_hi[mode]--;
0226     } else if (dir == IIO_EV_DIR_RISING) {
0227         /* rising threshold range 3..22V, hysteresis minimum 2V */
0228         if (val < 3 || val > 22 || val < (priv->threshold_lo[mode] + 2))
0229             return -EINVAL;
0230 
0231         if (val == priv->threshold_hi[mode])
0232             return 0;
0233 
0234         priv->threshold_hi[mode] = val;
0235 
0236         /* hysteresis must not be odd */
0237         if ((priv->threshold_hi[mode] - priv->threshold_lo[mode]) % 2)
0238             priv->threshold_lo[mode]++;
0239     }
0240 
0241     /* program thresholds */
0242     mutex_lock(&priv->lock);
0243 
0244     ret = hi8435_readw(priv, mode ? HI8435_SOCENHYS_REG :
0245                  HI8435_GOCENHYS_REG, &reg);
0246     if (ret < 0) {
0247         mutex_unlock(&priv->lock);
0248         return ret;
0249     }
0250 
0251     /* hysteresis */
0252     reg = priv->threshold_hi[mode] - priv->threshold_lo[mode];
0253     reg <<= 8;
0254     /* threshold center */
0255     reg |= (priv->threshold_hi[mode] + priv->threshold_lo[mode]);
0256 
0257     ret = hi8435_writew(priv, mode ? HI8435_SOCENHYS_REG :
0258                   HI8435_GOCENHYS_REG, reg);
0259 
0260     mutex_unlock(&priv->lock);
0261 
0262     return ret;
0263 }
0264 
0265 static int hi8435_debugfs_reg_access(struct iio_dev *idev,
0266                      unsigned reg, unsigned writeval,
0267                      unsigned *readval)
0268 {
0269     struct hi8435_priv *priv = iio_priv(idev);
0270     int ret;
0271     u8 val;
0272 
0273     if (readval != NULL) {
0274         ret = hi8435_readb(priv, reg, &val);
0275         *readval = val;
0276     } else {
0277         val = (u8)writeval;
0278         ret = hi8435_writeb(priv, reg, val);
0279     }
0280 
0281     return ret;
0282 }
0283 
0284 static const struct iio_event_spec hi8435_events[] = {
0285     {
0286         .type = IIO_EV_TYPE_THRESH,
0287         .dir = IIO_EV_DIR_RISING,
0288         .mask_separate = BIT(IIO_EV_INFO_VALUE),
0289     }, {
0290         .type = IIO_EV_TYPE_THRESH,
0291         .dir = IIO_EV_DIR_FALLING,
0292         .mask_separate = BIT(IIO_EV_INFO_VALUE),
0293     }, {
0294         .type = IIO_EV_TYPE_THRESH,
0295         .dir = IIO_EV_DIR_EITHER,
0296         .mask_separate = BIT(IIO_EV_INFO_ENABLE),
0297     },
0298 };
0299 
0300 static int hi8435_get_sensing_mode(struct iio_dev *idev,
0301                    const struct iio_chan_spec *chan)
0302 {
0303     struct hi8435_priv *priv = iio_priv(idev);
0304     int ret;
0305     u8 reg;
0306 
0307     ret = hi8435_readb(priv, HI8435_PSEN_REG, &reg);
0308     if (ret < 0)
0309         return ret;
0310 
0311     return !!(reg & BIT(chan->channel / 8));
0312 }
0313 
0314 static int hi8435_set_sensing_mode(struct iio_dev *idev,
0315                    const struct iio_chan_spec *chan,
0316                    unsigned int mode)
0317 {
0318     struct hi8435_priv *priv = iio_priv(idev);
0319     int ret;
0320     u8 reg;
0321 
0322     mutex_lock(&priv->lock);
0323 
0324     ret = hi8435_readb(priv, HI8435_PSEN_REG, &reg);
0325     if (ret < 0) {
0326         mutex_unlock(&priv->lock);
0327         return ret;
0328     }
0329 
0330     reg &= ~BIT(chan->channel / 8);
0331     if (mode)
0332         reg |= BIT(chan->channel / 8);
0333 
0334     ret = hi8435_writeb(priv, HI8435_PSEN_REG, reg);
0335 
0336     mutex_unlock(&priv->lock);
0337 
0338     return ret;
0339 }
0340 
0341 static const char * const hi8435_sensing_modes[] = { "GND-Open",
0342                              "Supply-Open" };
0343 
0344 static const struct iio_enum hi8435_sensing_mode = {
0345     .items = hi8435_sensing_modes,
0346     .num_items = ARRAY_SIZE(hi8435_sensing_modes),
0347     .get = hi8435_get_sensing_mode,
0348     .set = hi8435_set_sensing_mode,
0349 };
0350 
0351 static const struct iio_chan_spec_ext_info hi8435_ext_info[] = {
0352     IIO_ENUM("sensing_mode", IIO_SEPARATE, &hi8435_sensing_mode),
0353     IIO_ENUM_AVAILABLE("sensing_mode", IIO_SHARED_BY_TYPE, &hi8435_sensing_mode),
0354     {},
0355 };
0356 
0357 #define HI8435_VOLTAGE_CHANNEL(num)         \
0358 {                           \
0359     .type = IIO_VOLTAGE,                \
0360     .indexed = 1,                   \
0361     .channel = num,                 \
0362     .info_mask_separate = BIT(IIO_CHAN_INFO_RAW),   \
0363     .event_spec = hi8435_events,            \
0364     .num_event_specs = ARRAY_SIZE(hi8435_events),   \
0365     .ext_info = hi8435_ext_info,            \
0366 }
0367 
0368 static const struct iio_chan_spec hi8435_channels[] = {
0369     HI8435_VOLTAGE_CHANNEL(0),
0370     HI8435_VOLTAGE_CHANNEL(1),
0371     HI8435_VOLTAGE_CHANNEL(2),
0372     HI8435_VOLTAGE_CHANNEL(3),
0373     HI8435_VOLTAGE_CHANNEL(4),
0374     HI8435_VOLTAGE_CHANNEL(5),
0375     HI8435_VOLTAGE_CHANNEL(6),
0376     HI8435_VOLTAGE_CHANNEL(7),
0377     HI8435_VOLTAGE_CHANNEL(8),
0378     HI8435_VOLTAGE_CHANNEL(9),
0379     HI8435_VOLTAGE_CHANNEL(10),
0380     HI8435_VOLTAGE_CHANNEL(11),
0381     HI8435_VOLTAGE_CHANNEL(12),
0382     HI8435_VOLTAGE_CHANNEL(13),
0383     HI8435_VOLTAGE_CHANNEL(14),
0384     HI8435_VOLTAGE_CHANNEL(15),
0385     HI8435_VOLTAGE_CHANNEL(16),
0386     HI8435_VOLTAGE_CHANNEL(17),
0387     HI8435_VOLTAGE_CHANNEL(18),
0388     HI8435_VOLTAGE_CHANNEL(19),
0389     HI8435_VOLTAGE_CHANNEL(20),
0390     HI8435_VOLTAGE_CHANNEL(21),
0391     HI8435_VOLTAGE_CHANNEL(22),
0392     HI8435_VOLTAGE_CHANNEL(23),
0393     HI8435_VOLTAGE_CHANNEL(24),
0394     HI8435_VOLTAGE_CHANNEL(25),
0395     HI8435_VOLTAGE_CHANNEL(26),
0396     HI8435_VOLTAGE_CHANNEL(27),
0397     HI8435_VOLTAGE_CHANNEL(28),
0398     HI8435_VOLTAGE_CHANNEL(29),
0399     HI8435_VOLTAGE_CHANNEL(30),
0400     HI8435_VOLTAGE_CHANNEL(31),
0401     IIO_CHAN_SOFT_TIMESTAMP(32),
0402 };
0403 
0404 static const struct iio_info hi8435_info = {
0405     .read_raw = hi8435_read_raw,
0406     .read_event_config = hi8435_read_event_config,
0407     .write_event_config = hi8435_write_event_config,
0408     .read_event_value = hi8435_read_event_value,
0409     .write_event_value = hi8435_write_event_value,
0410     .debugfs_reg_access = hi8435_debugfs_reg_access,
0411 };
0412 
0413 static void hi8435_iio_push_event(struct iio_dev *idev, unsigned int val)
0414 {
0415     struct hi8435_priv *priv = iio_priv(idev);
0416     enum iio_event_direction dir;
0417     unsigned int i;
0418     unsigned int status = priv->event_prev_val ^ val;
0419 
0420     if (!status)
0421         return;
0422 
0423     for_each_set_bit(i, &priv->event_scan_mask, 32) {
0424         if (status & BIT(i)) {
0425             dir = val & BIT(i) ? IIO_EV_DIR_RISING :
0426                          IIO_EV_DIR_FALLING;
0427             iio_push_event(idev,
0428                        IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, i,
0429                             IIO_EV_TYPE_THRESH, dir),
0430                        iio_get_time_ns(idev));
0431         }
0432     }
0433 
0434     priv->event_prev_val = val;
0435 }
0436 
0437 static irqreturn_t hi8435_trigger_handler(int irq, void *private)
0438 {
0439     struct iio_poll_func *pf = private;
0440     struct iio_dev *idev = pf->indio_dev;
0441     struct hi8435_priv *priv = iio_priv(idev);
0442     u32 val;
0443     int ret;
0444 
0445     ret = hi8435_readl(priv, HI8435_SO31_0_REG, &val);
0446     if (ret < 0)
0447         goto err_read;
0448 
0449     hi8435_iio_push_event(idev, val);
0450 
0451 err_read:
0452     iio_trigger_notify_done(idev->trig);
0453 
0454     return IRQ_HANDLED;
0455 }
0456 
0457 static void hi8435_triggered_event_cleanup(void *data)
0458 {
0459     iio_triggered_event_cleanup(data);
0460 }
0461 
0462 static int hi8435_probe(struct spi_device *spi)
0463 {
0464     struct iio_dev *idev;
0465     struct hi8435_priv *priv;
0466     struct gpio_desc *reset_gpio;
0467     int ret;
0468 
0469     idev = devm_iio_device_alloc(&spi->dev, sizeof(*priv));
0470     if (!idev)
0471         return -ENOMEM;
0472 
0473     priv = iio_priv(idev);
0474     priv->spi = spi;
0475 
0476     reset_gpio = devm_gpiod_get(&spi->dev, NULL, GPIOD_OUT_LOW);
0477     if (IS_ERR(reset_gpio)) {
0478         /* chip s/w reset if h/w reset failed */
0479         hi8435_writeb(priv, HI8435_CTRL_REG, HI8435_CTRL_SRST);
0480         hi8435_writeb(priv, HI8435_CTRL_REG, 0);
0481     } else {
0482         udelay(5);
0483         gpiod_set_value_cansleep(reset_gpio, 1);
0484     }
0485 
0486     mutex_init(&priv->lock);
0487 
0488     idev->name      = spi_get_device_id(spi)->name;
0489     idev->modes     = INDIO_DIRECT_MODE;
0490     idev->info      = &hi8435_info;
0491     idev->channels      = hi8435_channels;
0492     idev->num_channels  = ARRAY_SIZE(hi8435_channels);
0493 
0494     /* unmask all events */
0495     priv->event_scan_mask = ~(0);
0496     /*
0497      * There is a restriction in the chip - the hysteresis can not be odd.
0498      * If the hysteresis is set to odd value then chip gets into lock state
0499      * and not functional anymore.
0500      * After chip reset the thresholds are in undefined state, so we need to
0501      * initialize thresholds to some initial values and then prevent
0502      * userspace setting odd hysteresis.
0503      *
0504      * Set threshold low voltage to 2V, threshold high voltage to 4V
0505      * for both GND-Open and Supply-Open sensing modes.
0506      */
0507     priv->threshold_lo[0] = priv->threshold_lo[1] = 2;
0508     priv->threshold_hi[0] = priv->threshold_hi[1] = 4;
0509     hi8435_writew(priv, HI8435_GOCENHYS_REG, 0x206);
0510     hi8435_writew(priv, HI8435_SOCENHYS_REG, 0x206);
0511 
0512     ret = iio_triggered_event_setup(idev, NULL, hi8435_trigger_handler);
0513     if (ret)
0514         return ret;
0515 
0516     ret = devm_add_action_or_reset(&spi->dev,
0517                        hi8435_triggered_event_cleanup,
0518                        idev);
0519     if (ret)
0520         return ret;
0521 
0522     return devm_iio_device_register(&spi->dev, idev);
0523 }
0524 
0525 static const struct of_device_id hi8435_dt_ids[] = {
0526     { .compatible = "holt,hi8435" },
0527     {},
0528 };
0529 MODULE_DEVICE_TABLE(of, hi8435_dt_ids);
0530 
0531 static const struct spi_device_id hi8435_id[] = {
0532     { "hi8435", 0 },
0533     { }
0534 };
0535 MODULE_DEVICE_TABLE(spi, hi8435_id);
0536 
0537 static struct spi_driver hi8435_driver = {
0538     .driver = {
0539         .name       = DRV_NAME,
0540         .of_match_table = hi8435_dt_ids,
0541     },
0542     .probe      = hi8435_probe,
0543     .id_table   = hi8435_id,
0544 };
0545 module_spi_driver(hi8435_driver);
0546 
0547 MODULE_LICENSE("GPL");
0548 MODULE_AUTHOR("Vladimir Barinov");
0549 MODULE_DESCRIPTION("HI-8435 threshold detector");
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