iio/adc/ep93xx_adc.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Driver for ADC module on the Cirrus Logic EP93xx series of SoCs
0004  *
0005  * Copyright (C) 2015 Alexander Sverdlin
0006  *
0007  * The driver uses polling to get the conversion status. According to EP93xx
0008  * datasheets, reading ADCResult register starts the conversion, but user is also
0009  * responsible for ensuring that delay between adjacent conversion triggers is
0010  * long enough so that maximum allowed conversion rate is not exceeded. This
0011  * basically renders IRQ mode unusable.
0012  */
0013
0014 #include <linux/clk.h>
0015 #include <linux/delay.h>
0016 #include <linux/device.h>
0017 #include <linux/err.h>
0018 #include <linux/iio/iio.h>
0019 #include <linux/io.h>
0020 #include <linux/irqflags.h>
0021 #include <linux/module.h>
0022 #include <linux/mutex.h>
0023 #include <linux/platform_device.h>
0024
0025 /*
0026  * This code could benefit from real HR Timers, but jiffy granularity would
0027  * lower ADC conversion rate down to CONFIG_HZ, so we fallback to busy wait
0028  * in such case.
0029  *
0030  * HR Timers-based version loads CPU only up to 10% during back to back ADC
0031  * conversion, while busy wait-based version consumes whole CPU power.
0032  */
0033 #ifdef CONFIG_HIGH_RES_TIMERS
0034 #define ep93xx_adc_delay(usmin, usmax) usleep_range(usmin, usmax)
0035 #else
0036 #define ep93xx_adc_delay(usmin, usmax) udelay(usmin)
0037 #endif
0038
0039 #define EP93XX_ADC_RESULT   0x08
0040 #define   EP93XX_ADC_SDR    BIT(31)
0041 #define EP93XX_ADC_SWITCH   0x18
0042 #define EP93XX_ADC_SW_LOCK  0x20
0043
0044 struct ep93xx_adc_priv {
0045     struct clk *clk;
0046     void __iomem *base;
0047     int lastch;
0048     struct mutex lock;
0049 };
0050
0051 #define EP93XX_ADC_CH(index, dname, swcfg) {            \
0052     .type = IIO_VOLTAGE,                    \
0053     .indexed = 1,                       \
0054     .channel = index,                   \
0055     .address = swcfg,                   \
0056     .datasheet_name = dname,                \
0057     .info_mask_separate = BIT(IIO_CHAN_INFO_RAW),       \
0058     .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SCALE) |   \
0059                    BIT(IIO_CHAN_INFO_OFFSET),   \
0060 }
0061
0062 /*
0063  * Numbering scheme for channels 0..4 is defined in EP9301 and EP9302 datasheets.
0064  * EP9307, EP9312 and EP9312 have 3 channels more (total 8), but the numbering is
0065  * not defined. So the last three are numbered randomly, let's say.
0066  */
0067 static const struct iio_chan_spec ep93xx_adc_channels[8] = {
0068     EP93XX_ADC_CH(0, "YM",  0x608),
0069     EP93XX_ADC_CH(1, "SXP", 0x680),
0070     EP93XX_ADC_CH(2, "SXM", 0x640),
0071     EP93XX_ADC_CH(3, "SYP", 0x620),
0072     EP93XX_ADC_CH(4, "SYM", 0x610),
0073     EP93XX_ADC_CH(5, "XP",  0x601),
0074     EP93XX_ADC_CH(6, "XM",  0x602),
0075     EP93XX_ADC_CH(7, "YP",  0x604),
0076 };
0077
0078 static int ep93xx_read_raw(struct iio_dev *iiodev,
0079                struct iio_chan_spec const *channel, int *value,
0080                int *shift, long mask)
0081 {
0082     struct ep93xx_adc_priv *priv = iio_priv(iiodev);
0083     unsigned long timeout;
0084     int ret;
0085
0086     switch (mask) {
0087     case IIO_CHAN_INFO_RAW:
0088         mutex_lock(&priv->lock);
0089         if (priv->lastch != channel->channel) {
0090             priv->lastch = channel->channel;
0091             /*
0092              * Switch register is software-locked, unlocking must be
0093              * immediately followed by write
0094              */
0095             local_irq_disable();
0096             writel_relaxed(0xAA, priv->base + EP93XX_ADC_SW_LOCK);
0097             writel_relaxed(channel->address,
0098                        priv->base + EP93XX_ADC_SWITCH);
0099             local_irq_enable();
0100             /*
0101              * Settling delay depends on module clock and could be
0102              * 2ms or 500us
0103              */
0104             ep93xx_adc_delay(2000, 2000);
0105         }
0106         /* Start the conversion, eventually discarding old result */
0107         readl_relaxed(priv->base + EP93XX_ADC_RESULT);
0108         /* Ensure maximum conversion rate is not exceeded */
0109         ep93xx_adc_delay(DIV_ROUND_UP(1000000, 925),
0110                  DIV_ROUND_UP(1000000, 925));
0111         /* At this point conversion must be completed, but anyway... */
0112         ret = IIO_VAL_INT;
0113         timeout = jiffies + msecs_to_jiffies(1) + 1;
0114         while (1) {
0115             u32 t;
0116
0117             t = readl_relaxed(priv->base + EP93XX_ADC_RESULT);
0118             if (t & EP93XX_ADC_SDR) {
0119                 *value = sign_extend32(t, 15);
0120                 break;
0121             }
0122
0123             if (time_after(jiffies, timeout)) {
0124                 dev_err(&iiodev->dev, "Conversion timeout\n");
0125                 ret = -ETIMEDOUT;
0126                 break;
0127             }
0128
0129             cpu_relax();
0130         }
0131         mutex_unlock(&priv->lock);
0132         return ret;
0133
0134     case IIO_CHAN_INFO_OFFSET:
0135         /* According to datasheet, range is -25000..25000 */
0136         *value = 25000;
0137         return IIO_VAL_INT;
0138
0139     case IIO_CHAN_INFO_SCALE:
0140         /* Typical supply voltage is 3.3v */
0141         *value = (1ULL << 32) * 3300 / 50000;
0142         *shift = 32;
0143         return IIO_VAL_FRACTIONAL_LOG2;
0144     }
0145
0146     return -EINVAL;
0147 }
0148
0149 static const struct iio_info ep93xx_adc_info = {
0150     .read_raw = ep93xx_read_raw,
0151 };
0152
0153 static int ep93xx_adc_probe(struct platform_device *pdev)
0154 {
0155     int ret;
0156     struct iio_dev *iiodev;
0157     struct ep93xx_adc_priv *priv;
0158     struct clk *pclk;
0159
0160     iiodev = devm_iio_device_alloc(&pdev->dev, sizeof(*priv));
0161     if (!iiodev)
0162         return -ENOMEM;
0163     priv = iio_priv(iiodev);
0164
0165     priv->base = devm_platform_ioremap_resource(pdev, 0);
0166     if (IS_ERR(priv->base))
0167         return PTR_ERR(priv->base);
0168
0169     iiodev->name = dev_name(&pdev->dev);
0170     iiodev->modes = INDIO_DIRECT_MODE;
0171     iiodev->info = &ep93xx_adc_info;
0172     iiodev->num_channels = ARRAY_SIZE(ep93xx_adc_channels);
0173     iiodev->channels = ep93xx_adc_channels;
0174
0175     priv->lastch = -1;
0176     mutex_init(&priv->lock);
0177
0178     platform_set_drvdata(pdev, iiodev);
0179
0180     priv->clk = devm_clk_get(&pdev->dev, NULL);
0181     if (IS_ERR(priv->clk)) {
0182         dev_err(&pdev->dev, "Cannot obtain clock\n");
0183         return PTR_ERR(priv->clk);
0184     }
0185
0186     pclk = clk_get_parent(priv->clk);
0187     if (!pclk) {
0188         dev_warn(&pdev->dev, "Cannot obtain parent clock\n");
0189     } else {
0190         /*
0191          * This is actually a place for improvement:
0192          * EP93xx ADC supports two clock divisors -- 4 and 16,
0193          * resulting in conversion rates 3750 and 925 samples per second
0194          * with 500us or 2ms settling time respectively.
0195          * One might find this interesting enough to be configurable.
0196          */
0197         ret = clk_set_rate(priv->clk, clk_get_rate(pclk) / 16);
0198         if (ret)
0199             dev_warn(&pdev->dev, "Cannot set clock rate\n");
0200         /*
0201          * We can tolerate rate setting failure because the module should
0202          * work in any case.
0203          */
0204     }
0205
0206     ret = clk_prepare_enable(priv->clk);
0207     if (ret) {
0208         dev_err(&pdev->dev, "Cannot enable clock\n");
0209         return ret;
0210     }
0211
0212     ret = iio_device_register(iiodev);
0213     if (ret)
0214         clk_disable_unprepare(priv->clk);
0215
0216     return ret;
0217 }
0218
0219 static int ep93xx_adc_remove(struct platform_device *pdev)
0220 {
0221     struct iio_dev *iiodev = platform_get_drvdata(pdev);
0222     struct ep93xx_adc_priv *priv = iio_priv(iiodev);
0223
0224     iio_device_unregister(iiodev);
0225     clk_disable_unprepare(priv->clk);
0226
0227     return 0;
0228 }
0229
0230 static struct platform_driver ep93xx_adc_driver = {
0231     .driver = {
0232         .name = "ep93xx-adc",
0233     },
0234     .probe = ep93xx_adc_probe,
0235     .remove = ep93xx_adc_remove,
0236 };
0237 module_platform_driver(ep93xx_adc_driver);
0238
0239 MODULE_AUTHOR("Alexander Sverdlin <alexander.sverdlin@gmail.com>");
0240 MODULE_DESCRIPTION("Cirrus Logic EP93XX ADC driver");
0241 MODULE_LICENSE("GPL");
0242 MODULE_ALIAS("platform:ep93xx-adc");