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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Driver for the Diolan DLN-2 USB-ADC adapter
0004  *
0005  * Copyright (c) 2017 Jack Andersen
0006  */
0007 
0008 #include <linux/kernel.h>
0009 #include <linux/module.h>
0010 #include <linux/types.h>
0011 #include <linux/platform_device.h>
0012 #include <linux/mfd/dln2.h>
0013 
0014 #include <linux/iio/iio.h>
0015 #include <linux/iio/sysfs.h>
0016 #include <linux/iio/trigger.h>
0017 #include <linux/iio/trigger_consumer.h>
0018 #include <linux/iio/triggered_buffer.h>
0019 #include <linux/iio/buffer.h>
0020 #include <linux/iio/kfifo_buf.h>
0021 
0022 #define DLN2_ADC_MOD_NAME "dln2-adc"
0023 
0024 #define DLN2_ADC_ID             0x06
0025 
0026 #define DLN2_ADC_GET_CHANNEL_COUNT  DLN2_CMD(0x01, DLN2_ADC_ID)
0027 #define DLN2_ADC_ENABLE         DLN2_CMD(0x02, DLN2_ADC_ID)
0028 #define DLN2_ADC_DISABLE        DLN2_CMD(0x03, DLN2_ADC_ID)
0029 #define DLN2_ADC_CHANNEL_ENABLE     DLN2_CMD(0x05, DLN2_ADC_ID)
0030 #define DLN2_ADC_CHANNEL_DISABLE    DLN2_CMD(0x06, DLN2_ADC_ID)
0031 #define DLN2_ADC_SET_RESOLUTION     DLN2_CMD(0x08, DLN2_ADC_ID)
0032 #define DLN2_ADC_CHANNEL_GET_VAL    DLN2_CMD(0x0A, DLN2_ADC_ID)
0033 #define DLN2_ADC_CHANNEL_GET_ALL_VAL    DLN2_CMD(0x0B, DLN2_ADC_ID)
0034 #define DLN2_ADC_CHANNEL_SET_CFG    DLN2_CMD(0x0C, DLN2_ADC_ID)
0035 #define DLN2_ADC_CHANNEL_GET_CFG    DLN2_CMD(0x0D, DLN2_ADC_ID)
0036 #define DLN2_ADC_CONDITION_MET_EV   DLN2_CMD(0x10, DLN2_ADC_ID)
0037 
0038 #define DLN2_ADC_EVENT_NONE     0
0039 #define DLN2_ADC_EVENT_BELOW        1
0040 #define DLN2_ADC_EVENT_LEVEL_ABOVE  2
0041 #define DLN2_ADC_EVENT_OUTSIDE      3
0042 #define DLN2_ADC_EVENT_INSIDE       4
0043 #define DLN2_ADC_EVENT_ALWAYS       5
0044 
0045 #define DLN2_ADC_MAX_CHANNELS 8
0046 #define DLN2_ADC_DATA_BITS 10
0047 
0048 /*
0049  * Plays similar role to iio_demux_table in subsystem core; except allocated
0050  * in a fixed 8-element array.
0051  */
0052 struct dln2_adc_demux_table {
0053     unsigned int from;
0054     unsigned int to;
0055     unsigned int length;
0056 };
0057 
0058 struct dln2_adc {
0059     struct platform_device *pdev;
0060     struct iio_chan_spec iio_channels[DLN2_ADC_MAX_CHANNELS + 1];
0061     int port, trigger_chan;
0062     struct iio_trigger *trig;
0063     struct mutex mutex;
0064     /* Cached sample period in milliseconds */
0065     unsigned int sample_period;
0066     /* Demux table */
0067     unsigned int demux_count;
0068     struct dln2_adc_demux_table demux[DLN2_ADC_MAX_CHANNELS];
0069     /* Precomputed timestamp padding offset and length */
0070     unsigned int ts_pad_offset, ts_pad_length;
0071 };
0072 
0073 struct dln2_adc_port_chan {
0074     u8 port;
0075     u8 chan;
0076 };
0077 
0078 struct dln2_adc_get_all_vals {
0079     __le16 channel_mask;
0080     __le16 values[DLN2_ADC_MAX_CHANNELS];
0081 };
0082 
0083 static void dln2_adc_add_demux(struct dln2_adc *dln2,
0084     unsigned int in_loc, unsigned int out_loc,
0085     unsigned int length)
0086 {
0087     struct dln2_adc_demux_table *p = dln2->demux_count ?
0088         &dln2->demux[dln2->demux_count - 1] : NULL;
0089 
0090     if (p && p->from + p->length == in_loc &&
0091         p->to + p->length == out_loc) {
0092         p->length += length;
0093     } else if (dln2->demux_count < DLN2_ADC_MAX_CHANNELS) {
0094         p = &dln2->demux[dln2->demux_count++];
0095         p->from = in_loc;
0096         p->to = out_loc;
0097         p->length = length;
0098     }
0099 }
0100 
0101 static void dln2_adc_update_demux(struct dln2_adc *dln2)
0102 {
0103     int in_ind = -1, out_ind;
0104     unsigned int in_loc = 0, out_loc = 0;
0105     struct iio_dev *indio_dev = platform_get_drvdata(dln2->pdev);
0106 
0107     /* Clear out any old demux */
0108     dln2->demux_count = 0;
0109 
0110     /* Optimize all 8-channels case */
0111     if (indio_dev->masklength &&
0112         (*indio_dev->active_scan_mask & 0xff) == 0xff) {
0113         dln2_adc_add_demux(dln2, 0, 0, 16);
0114         dln2->ts_pad_offset = 0;
0115         dln2->ts_pad_length = 0;
0116         return;
0117     }
0118 
0119     /* Build demux table from fixed 8-channels to active_scan_mask */
0120     for_each_set_bit(out_ind,
0121              indio_dev->active_scan_mask,
0122              indio_dev->masklength) {
0123         /* Handle timestamp separately */
0124         if (out_ind == DLN2_ADC_MAX_CHANNELS)
0125             break;
0126         for (++in_ind; in_ind != out_ind; ++in_ind)
0127             in_loc += 2;
0128         dln2_adc_add_demux(dln2, in_loc, out_loc, 2);
0129         out_loc += 2;
0130         in_loc += 2;
0131     }
0132 
0133     if (indio_dev->scan_timestamp) {
0134         size_t ts_offset = indio_dev->scan_bytes / sizeof(int64_t) - 1;
0135 
0136         dln2->ts_pad_offset = out_loc;
0137         dln2->ts_pad_length = ts_offset * sizeof(int64_t) - out_loc;
0138     } else {
0139         dln2->ts_pad_offset = 0;
0140         dln2->ts_pad_length = 0;
0141     }
0142 }
0143 
0144 static int dln2_adc_get_chan_count(struct dln2_adc *dln2)
0145 {
0146     int ret;
0147     u8 port = dln2->port;
0148     u8 count;
0149     int olen = sizeof(count);
0150 
0151     ret = dln2_transfer(dln2->pdev, DLN2_ADC_GET_CHANNEL_COUNT,
0152                 &port, sizeof(port), &count, &olen);
0153     if (ret < 0) {
0154         dev_dbg(&dln2->pdev->dev, "Problem in %s\n", __func__);
0155         return ret;
0156     }
0157     if (olen < sizeof(count))
0158         return -EPROTO;
0159 
0160     return count;
0161 }
0162 
0163 static int dln2_adc_set_port_resolution(struct dln2_adc *dln2)
0164 {
0165     int ret;
0166     struct dln2_adc_port_chan port_chan = {
0167         .port = dln2->port,
0168         .chan = DLN2_ADC_DATA_BITS,
0169     };
0170 
0171     ret = dln2_transfer_tx(dln2->pdev, DLN2_ADC_SET_RESOLUTION,
0172                    &port_chan, sizeof(port_chan));
0173     if (ret < 0)
0174         dev_dbg(&dln2->pdev->dev, "Problem in %s\n", __func__);
0175 
0176     return ret;
0177 }
0178 
0179 static int dln2_adc_set_chan_enabled(struct dln2_adc *dln2,
0180                      int channel, bool enable)
0181 {
0182     int ret;
0183     struct dln2_adc_port_chan port_chan = {
0184         .port = dln2->port,
0185         .chan = channel,
0186     };
0187     u16 cmd = enable ? DLN2_ADC_CHANNEL_ENABLE : DLN2_ADC_CHANNEL_DISABLE;
0188 
0189     ret = dln2_transfer_tx(dln2->pdev, cmd, &port_chan, sizeof(port_chan));
0190     if (ret < 0)
0191         dev_dbg(&dln2->pdev->dev, "Problem in %s\n", __func__);
0192 
0193     return ret;
0194 }
0195 
0196 static int dln2_adc_set_port_enabled(struct dln2_adc *dln2, bool enable,
0197                      u16 *conflict_out)
0198 {
0199     int ret;
0200     u8 port = dln2->port;
0201     __le16 conflict;
0202     int olen = sizeof(conflict);
0203     u16 cmd = enable ? DLN2_ADC_ENABLE : DLN2_ADC_DISABLE;
0204 
0205     if (conflict_out)
0206         *conflict_out = 0;
0207 
0208     ret = dln2_transfer(dln2->pdev, cmd, &port, sizeof(port),
0209                 &conflict, &olen);
0210     if (ret < 0) {
0211         dev_dbg(&dln2->pdev->dev, "Problem in %s(%d)\n",
0212             __func__, (int)enable);
0213         if (conflict_out && enable && olen >= sizeof(conflict))
0214             *conflict_out = le16_to_cpu(conflict);
0215         return ret;
0216     }
0217     if (enable && olen < sizeof(conflict))
0218         return -EPROTO;
0219 
0220     return ret;
0221 }
0222 
0223 static int dln2_adc_set_chan_period(struct dln2_adc *dln2,
0224     unsigned int channel, unsigned int period)
0225 {
0226     int ret;
0227     struct {
0228         struct dln2_adc_port_chan port_chan;
0229         __u8 type;
0230         __le16 period;
0231         __le16 low;
0232         __le16 high;
0233     } __packed set_cfg = {
0234         .port_chan.port = dln2->port,
0235         .port_chan.chan = channel,
0236         .type = period ? DLN2_ADC_EVENT_ALWAYS : DLN2_ADC_EVENT_NONE,
0237         .period = cpu_to_le16(period)
0238     };
0239 
0240     ret = dln2_transfer_tx(dln2->pdev, DLN2_ADC_CHANNEL_SET_CFG,
0241                    &set_cfg, sizeof(set_cfg));
0242     if (ret < 0)
0243         dev_dbg(&dln2->pdev->dev, "Problem in %s\n", __func__);
0244 
0245     return ret;
0246 }
0247 
0248 static int dln2_adc_read(struct dln2_adc *dln2, unsigned int channel)
0249 {
0250     int ret, i;
0251     u16 conflict;
0252     __le16 value;
0253     int olen = sizeof(value);
0254     struct dln2_adc_port_chan port_chan = {
0255         .port = dln2->port,
0256         .chan = channel,
0257     };
0258 
0259     ret = dln2_adc_set_chan_enabled(dln2, channel, true);
0260     if (ret < 0)
0261         return ret;
0262 
0263     ret = dln2_adc_set_port_enabled(dln2, true, &conflict);
0264     if (ret < 0) {
0265         if (conflict) {
0266             dev_err(&dln2->pdev->dev,
0267                 "ADC pins conflict with mask %04X\n",
0268                 (int)conflict);
0269             ret = -EBUSY;
0270         }
0271         goto disable_chan;
0272     }
0273 
0274     /*
0275      * Call GET_VAL twice due to initial zero-return immediately after
0276      * enabling channel.
0277      */
0278     for (i = 0; i < 2; ++i) {
0279         ret = dln2_transfer(dln2->pdev, DLN2_ADC_CHANNEL_GET_VAL,
0280                     &port_chan, sizeof(port_chan),
0281                     &value, &olen);
0282         if (ret < 0) {
0283             dev_dbg(&dln2->pdev->dev, "Problem in %s\n", __func__);
0284             goto disable_port;
0285         }
0286         if (olen < sizeof(value)) {
0287             ret = -EPROTO;
0288             goto disable_port;
0289         }
0290     }
0291 
0292     ret = le16_to_cpu(value);
0293 
0294 disable_port:
0295     dln2_adc_set_port_enabled(dln2, false, NULL);
0296 disable_chan:
0297     dln2_adc_set_chan_enabled(dln2, channel, false);
0298 
0299     return ret;
0300 }
0301 
0302 static int dln2_adc_read_all(struct dln2_adc *dln2,
0303                  struct dln2_adc_get_all_vals *get_all_vals)
0304 {
0305     int ret;
0306     __u8 port = dln2->port;
0307     int olen = sizeof(*get_all_vals);
0308 
0309     ret = dln2_transfer(dln2->pdev, DLN2_ADC_CHANNEL_GET_ALL_VAL,
0310                 &port, sizeof(port), get_all_vals, &olen);
0311     if (ret < 0) {
0312         dev_dbg(&dln2->pdev->dev, "Problem in %s\n", __func__);
0313         return ret;
0314     }
0315     if (olen < sizeof(*get_all_vals))
0316         return -EPROTO;
0317 
0318     return ret;
0319 }
0320 
0321 static int dln2_adc_read_raw(struct iio_dev *indio_dev,
0322                  struct iio_chan_spec const *chan,
0323                  int *val,
0324                  int *val2,
0325                  long mask)
0326 {
0327     int ret;
0328     unsigned int microhertz;
0329     struct dln2_adc *dln2 = iio_priv(indio_dev);
0330 
0331     switch (mask) {
0332     case IIO_CHAN_INFO_RAW:
0333         ret = iio_device_claim_direct_mode(indio_dev);
0334         if (ret < 0)
0335             return ret;
0336 
0337         mutex_lock(&dln2->mutex);
0338         ret = dln2_adc_read(dln2, chan->channel);
0339         mutex_unlock(&dln2->mutex);
0340 
0341         iio_device_release_direct_mode(indio_dev);
0342 
0343         if (ret < 0)
0344             return ret;
0345 
0346         *val = ret;
0347         return IIO_VAL_INT;
0348 
0349     case IIO_CHAN_INFO_SCALE:
0350         /*
0351          * Voltage reference is fixed at 3.3v
0352          *  3.3 / (1 << 10) * 1000000000
0353          */
0354         *val = 0;
0355         *val2 = 3222656;
0356         return IIO_VAL_INT_PLUS_NANO;
0357 
0358     case IIO_CHAN_INFO_SAMP_FREQ:
0359         if (dln2->sample_period) {
0360             microhertz = 1000000000 / dln2->sample_period;
0361             *val = microhertz / 1000000;
0362             *val2 = microhertz % 1000000;
0363         } else {
0364             *val = 0;
0365             *val2 = 0;
0366         }
0367 
0368         return IIO_VAL_INT_PLUS_MICRO;
0369 
0370     default:
0371         return -EINVAL;
0372     }
0373 }
0374 
0375 static int dln2_adc_write_raw(struct iio_dev *indio_dev,
0376                   struct iio_chan_spec const *chan,
0377                   int val,
0378                   int val2,
0379                   long mask)
0380 {
0381     int ret;
0382     unsigned int microhertz;
0383     struct dln2_adc *dln2 = iio_priv(indio_dev);
0384 
0385     switch (mask) {
0386     case IIO_CHAN_INFO_SAMP_FREQ:
0387         microhertz = 1000000 * val + val2;
0388 
0389         mutex_lock(&dln2->mutex);
0390 
0391         dln2->sample_period =
0392             microhertz ? 1000000000 / microhertz : UINT_MAX;
0393         if (dln2->sample_period > 65535) {
0394             dln2->sample_period = 65535;
0395             dev_warn(&dln2->pdev->dev,
0396                  "clamping period to 65535ms\n");
0397         }
0398 
0399         /*
0400          * The first requested channel is arbitrated as a shared
0401          * trigger source, so only one event is registered with the
0402          * DLN. The event handler will then read all enabled channel
0403          * values using DLN2_ADC_CHANNEL_GET_ALL_VAL to maintain
0404          * synchronization between ADC readings.
0405          */
0406         if (dln2->trigger_chan != -1)
0407             ret = dln2_adc_set_chan_period(dln2,
0408                 dln2->trigger_chan, dln2->sample_period);
0409         else
0410             ret = 0;
0411 
0412         mutex_unlock(&dln2->mutex);
0413 
0414         return ret;
0415 
0416     default:
0417         return -EINVAL;
0418     }
0419 }
0420 
0421 static int dln2_update_scan_mode(struct iio_dev *indio_dev,
0422                  const unsigned long *scan_mask)
0423 {
0424     struct dln2_adc *dln2 = iio_priv(indio_dev);
0425     int chan_count = indio_dev->num_channels - 1;
0426     int ret, i, j;
0427 
0428     mutex_lock(&dln2->mutex);
0429 
0430     for (i = 0; i < chan_count; ++i) {
0431         ret = dln2_adc_set_chan_enabled(dln2, i,
0432                         test_bit(i, scan_mask));
0433         if (ret < 0) {
0434             for (j = 0; j < i; ++j)
0435                 dln2_adc_set_chan_enabled(dln2, j, false);
0436             mutex_unlock(&dln2->mutex);
0437             dev_err(&dln2->pdev->dev,
0438                 "Unable to enable ADC channel %d\n", i);
0439             return -EBUSY;
0440         }
0441     }
0442 
0443     dln2_adc_update_demux(dln2);
0444 
0445     mutex_unlock(&dln2->mutex);
0446 
0447     return 0;
0448 }
0449 
0450 #define DLN2_ADC_CHAN(lval, idx) {                  \
0451     lval.type = IIO_VOLTAGE;                    \
0452     lval.channel = idx;                     \
0453     lval.indexed = 1;                       \
0454     lval.info_mask_separate = BIT(IIO_CHAN_INFO_RAW);       \
0455     lval.info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SCALE) |   \
0456                        BIT(IIO_CHAN_INFO_SAMP_FREQ);    \
0457     lval.scan_index = idx;                      \
0458     lval.scan_type.sign = 'u';                  \
0459     lval.scan_type.realbits = DLN2_ADC_DATA_BITS;           \
0460     lval.scan_type.storagebits = 16;                \
0461     lval.scan_type.endianness = IIO_LE;             \
0462 }
0463 
0464 /* Assignment version of IIO_CHAN_SOFT_TIMESTAMP */
0465 #define IIO_CHAN_SOFT_TIMESTAMP_ASSIGN(lval, _si) { \
0466     lval.type = IIO_TIMESTAMP;          \
0467     lval.channel = -1;              \
0468     lval.scan_index = _si;              \
0469     lval.scan_type.sign = 's';          \
0470     lval.scan_type.realbits = 64;           \
0471     lval.scan_type.storagebits = 64;        \
0472 }
0473 
0474 static const struct iio_info dln2_adc_info = {
0475     .read_raw = dln2_adc_read_raw,
0476     .write_raw = dln2_adc_write_raw,
0477     .update_scan_mode = dln2_update_scan_mode,
0478 };
0479 
0480 static irqreturn_t dln2_adc_trigger_h(int irq, void *p)
0481 {
0482     struct iio_poll_func *pf = p;
0483     struct iio_dev *indio_dev = pf->indio_dev;
0484     struct {
0485         __le16 values[DLN2_ADC_MAX_CHANNELS];
0486         int64_t timestamp_space;
0487     } data;
0488     struct dln2_adc_get_all_vals dev_data;
0489     struct dln2_adc *dln2 = iio_priv(indio_dev);
0490     const struct dln2_adc_demux_table *t;
0491     int ret, i;
0492 
0493     mutex_lock(&dln2->mutex);
0494     ret = dln2_adc_read_all(dln2, &dev_data);
0495     mutex_unlock(&dln2->mutex);
0496     if (ret < 0)
0497         goto done;
0498 
0499     /* Demux operation */
0500     for (i = 0; i < dln2->demux_count; ++i) {
0501         t = &dln2->demux[i];
0502         memcpy((void *)data.values + t->to,
0503                (void *)dev_data.values + t->from, t->length);
0504     }
0505 
0506     /* Zero padding space between values and timestamp */
0507     if (dln2->ts_pad_length)
0508         memset((void *)data.values + dln2->ts_pad_offset,
0509                0, dln2->ts_pad_length);
0510 
0511     iio_push_to_buffers_with_timestamp(indio_dev, &data,
0512                        iio_get_time_ns(indio_dev));
0513 
0514 done:
0515     iio_trigger_notify_done(indio_dev->trig);
0516     return IRQ_HANDLED;
0517 }
0518 
0519 static int dln2_adc_triggered_buffer_postenable(struct iio_dev *indio_dev)
0520 {
0521     int ret;
0522     struct dln2_adc *dln2 = iio_priv(indio_dev);
0523     u16 conflict;
0524     unsigned int trigger_chan;
0525 
0526     mutex_lock(&dln2->mutex);
0527 
0528     /* Enable ADC */
0529     ret = dln2_adc_set_port_enabled(dln2, true, &conflict);
0530     if (ret < 0) {
0531         mutex_unlock(&dln2->mutex);
0532         dev_dbg(&dln2->pdev->dev, "Problem in %s\n", __func__);
0533         if (conflict) {
0534             dev_err(&dln2->pdev->dev,
0535                 "ADC pins conflict with mask %04X\n",
0536                 (int)conflict);
0537             ret = -EBUSY;
0538         }
0539         return ret;
0540     }
0541 
0542     /* Assign trigger channel based on first enabled channel */
0543     trigger_chan = find_first_bit(indio_dev->active_scan_mask,
0544                       indio_dev->masklength);
0545     if (trigger_chan < DLN2_ADC_MAX_CHANNELS) {
0546         dln2->trigger_chan = trigger_chan;
0547         ret = dln2_adc_set_chan_period(dln2, dln2->trigger_chan,
0548                            dln2->sample_period);
0549         mutex_unlock(&dln2->mutex);
0550         if (ret < 0) {
0551             dev_dbg(&dln2->pdev->dev, "Problem in %s\n", __func__);
0552             return ret;
0553         }
0554     } else {
0555         dln2->trigger_chan = -1;
0556         mutex_unlock(&dln2->mutex);
0557     }
0558 
0559     return 0;
0560 }
0561 
0562 static int dln2_adc_triggered_buffer_predisable(struct iio_dev *indio_dev)
0563 {
0564     int ret;
0565     struct dln2_adc *dln2 = iio_priv(indio_dev);
0566 
0567     mutex_lock(&dln2->mutex);
0568 
0569     /* Disable trigger channel */
0570     if (dln2->trigger_chan != -1) {
0571         dln2_adc_set_chan_period(dln2, dln2->trigger_chan, 0);
0572         dln2->trigger_chan = -1;
0573     }
0574 
0575     /* Disable ADC */
0576     ret = dln2_adc_set_port_enabled(dln2, false, NULL);
0577 
0578     mutex_unlock(&dln2->mutex);
0579     if (ret < 0)
0580         dev_dbg(&dln2->pdev->dev, "Problem in %s\n", __func__);
0581 
0582     return ret;
0583 }
0584 
0585 static const struct iio_buffer_setup_ops dln2_adc_buffer_setup_ops = {
0586     .postenable = dln2_adc_triggered_buffer_postenable,
0587     .predisable = dln2_adc_triggered_buffer_predisable,
0588 };
0589 
0590 static void dln2_adc_event(struct platform_device *pdev, u16 echo,
0591                const void *data, int len)
0592 {
0593     struct iio_dev *indio_dev = platform_get_drvdata(pdev);
0594     struct dln2_adc *dln2 = iio_priv(indio_dev);
0595 
0596     /* Called via URB completion handler */
0597     iio_trigger_poll(dln2->trig);
0598 }
0599 
0600 static int dln2_adc_probe(struct platform_device *pdev)
0601 {
0602     struct device *dev = &pdev->dev;
0603     struct dln2_adc *dln2;
0604     struct dln2_platform_data *pdata = dev_get_platdata(&pdev->dev);
0605     struct iio_dev *indio_dev;
0606     int i, ret, chans;
0607 
0608     indio_dev = devm_iio_device_alloc(dev, sizeof(*dln2));
0609     if (!indio_dev) {
0610         dev_err(dev, "failed allocating iio device\n");
0611         return -ENOMEM;
0612     }
0613 
0614     dln2 = iio_priv(indio_dev);
0615     dln2->pdev = pdev;
0616     dln2->port = pdata->port;
0617     dln2->trigger_chan = -1;
0618     mutex_init(&dln2->mutex);
0619 
0620     platform_set_drvdata(pdev, indio_dev);
0621 
0622     ret = dln2_adc_set_port_resolution(dln2);
0623     if (ret < 0) {
0624         dev_err(dev, "failed to set ADC resolution to 10 bits\n");
0625         return ret;
0626     }
0627 
0628     chans = dln2_adc_get_chan_count(dln2);
0629     if (chans < 0) {
0630         dev_err(dev, "failed to get channel count: %d\n", chans);
0631         return chans;
0632     }
0633     if (chans > DLN2_ADC_MAX_CHANNELS) {
0634         chans = DLN2_ADC_MAX_CHANNELS;
0635         dev_warn(dev, "clamping channels to %d\n",
0636              DLN2_ADC_MAX_CHANNELS);
0637     }
0638 
0639     for (i = 0; i < chans; ++i)
0640         DLN2_ADC_CHAN(dln2->iio_channels[i], i)
0641     IIO_CHAN_SOFT_TIMESTAMP_ASSIGN(dln2->iio_channels[i], i);
0642 
0643     indio_dev->name = DLN2_ADC_MOD_NAME;
0644     indio_dev->info = &dln2_adc_info;
0645     indio_dev->modes = INDIO_DIRECT_MODE;
0646     indio_dev->channels = dln2->iio_channels;
0647     indio_dev->num_channels = chans + 1;
0648     indio_dev->setup_ops = &dln2_adc_buffer_setup_ops;
0649 
0650     dln2->trig = devm_iio_trigger_alloc(dev, "%s-dev%d",
0651                         indio_dev->name,
0652                         iio_device_id(indio_dev));
0653     if (!dln2->trig) {
0654         dev_err(dev, "failed to allocate trigger\n");
0655         return -ENOMEM;
0656     }
0657     iio_trigger_set_drvdata(dln2->trig, dln2);
0658     ret = devm_iio_trigger_register(dev, dln2->trig);
0659     if (ret) {
0660         dev_err(dev, "failed to register trigger: %d\n", ret);
0661         return ret;
0662     }
0663     iio_trigger_set_immutable(indio_dev, dln2->trig);
0664 
0665     ret = devm_iio_triggered_buffer_setup(dev, indio_dev, NULL,
0666                           dln2_adc_trigger_h,
0667                           &dln2_adc_buffer_setup_ops);
0668     if (ret) {
0669         dev_err(dev, "failed to allocate triggered buffer: %d\n", ret);
0670         return ret;
0671     }
0672 
0673     ret = dln2_register_event_cb(pdev, DLN2_ADC_CONDITION_MET_EV,
0674                      dln2_adc_event);
0675     if (ret) {
0676         dev_err(dev, "failed to setup DLN2 periodic event: %d\n", ret);
0677         return ret;
0678     }
0679 
0680     ret = iio_device_register(indio_dev);
0681     if (ret) {
0682         dev_err(dev, "failed to register iio device: %d\n", ret);
0683         goto unregister_event;
0684     }
0685 
0686     return ret;
0687 
0688 unregister_event:
0689     dln2_unregister_event_cb(pdev, DLN2_ADC_CONDITION_MET_EV);
0690 
0691     return ret;
0692 }
0693 
0694 static int dln2_adc_remove(struct platform_device *pdev)
0695 {
0696     struct iio_dev *indio_dev = platform_get_drvdata(pdev);
0697 
0698     iio_device_unregister(indio_dev);
0699     dln2_unregister_event_cb(pdev, DLN2_ADC_CONDITION_MET_EV);
0700     return 0;
0701 }
0702 
0703 static struct platform_driver dln2_adc_driver = {
0704     .driver.name    = DLN2_ADC_MOD_NAME,
0705     .probe      = dln2_adc_probe,
0706     .remove     = dln2_adc_remove,
0707 };
0708 
0709 module_platform_driver(dln2_adc_driver);
0710 
0711 MODULE_AUTHOR("Jack Andersen <jackoalan@gmail.com");
0712 MODULE_DESCRIPTION("Driver for the Diolan DLN2 ADC interface");
0713 MODULE_LICENSE("GPL v2");
0714 MODULE_ALIAS("platform:dln2-adc");
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