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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (C) 2017 Tony Lindgren <tony@atomide.com>
0004  *
0005  * Rewritten for Linux IIO framework with some code based on
0006  * earlier driver found in the Motorola Linux kernel:
0007  *
0008  * Copyright (C) 2009-2010 Motorola, Inc.
0009  */
0010 
0011 #include <linux/delay.h>
0012 #include <linux/device.h>
0013 #include <linux/err.h>
0014 #include <linux/init.h>
0015 #include <linux/interrupt.h>
0016 #include <linux/kernel.h>
0017 #include <linux/module.h>
0018 #include <linux/mod_devicetable.h>
0019 #include <linux/platform_device.h>
0020 #include <linux/property.h>
0021 #include <linux/regmap.h>
0022 
0023 #include <linux/iio/buffer.h>
0024 #include <linux/iio/driver.h>
0025 #include <linux/iio/iio.h>
0026 #include <linux/iio/kfifo_buf.h>
0027 #include <linux/mfd/motorola-cpcap.h>
0028 
0029 /* Register CPCAP_REG_ADCC1 bits */
0030 #define CPCAP_BIT_ADEN_AUTO_CLR     BIT(15) /* Currently unused */
0031 #define CPCAP_BIT_CAL_MODE      BIT(14) /* Set with BIT_RAND0 */
0032 #define CPCAP_BIT_ADC_CLK_SEL1      BIT(13) /* Currently unused */
0033 #define CPCAP_BIT_ADC_CLK_SEL0      BIT(12) /* Currently unused */
0034 #define CPCAP_BIT_ATOX          BIT(11)
0035 #define CPCAP_BIT_ATO3          BIT(10)
0036 #define CPCAP_BIT_ATO2          BIT(9)
0037 #define CPCAP_BIT_ATO1          BIT(8)
0038 #define CPCAP_BIT_ATO0          BIT(7)
0039 #define CPCAP_BIT_ADA2          BIT(6)
0040 #define CPCAP_BIT_ADA1          BIT(5)
0041 #define CPCAP_BIT_ADA0          BIT(4)
0042 #define CPCAP_BIT_AD_SEL1       BIT(3)  /* Set for bank1 */
0043 #define CPCAP_BIT_RAND1         BIT(2)  /* Set for channel 16 & 17 */
0044 #define CPCAP_BIT_RAND0         BIT(1)  /* Set with CAL_MODE */
0045 #define CPCAP_BIT_ADEN          BIT(0)  /* Currently unused */
0046 
0047 #define CPCAP_REG_ADCC1_DEFAULTS    (CPCAP_BIT_ADEN_AUTO_CLR | \
0048                      CPCAP_BIT_ADC_CLK_SEL0 |  \
0049                      CPCAP_BIT_RAND1)
0050 
0051 /* Register CPCAP_REG_ADCC2 bits */
0052 #define CPCAP_BIT_CAL_FACTOR_ENABLE BIT(15) /* Currently unused */
0053 #define CPCAP_BIT_BATDETB_EN        BIT(14) /* Currently unused */
0054 #define CPCAP_BIT_ADTRIG_ONESHOT    BIT(13) /* Set for !TIMING_IMM */
0055 #define CPCAP_BIT_ASC           BIT(12) /* Set for TIMING_IMM */
0056 #define CPCAP_BIT_ATOX_PS_FACTOR    BIT(11)
0057 #define CPCAP_BIT_ADC_PS_FACTOR1    BIT(10)
0058 #define CPCAP_BIT_ADC_PS_FACTOR0    BIT(9)
0059 #define CPCAP_BIT_AD4_SELECT        BIT(8)  /* Currently unused */
0060 #define CPCAP_BIT_ADC_BUSY      BIT(7)  /* Currently unused */
0061 #define CPCAP_BIT_THERMBIAS_EN      BIT(6)  /* Bias for AD0_BATTDETB */
0062 #define CPCAP_BIT_ADTRIG_DIS        BIT(5)  /* Disable interrupt */
0063 #define CPCAP_BIT_LIADC         BIT(4)  /* Currently unused */
0064 #define CPCAP_BIT_TS_REFEN      BIT(3)  /* Currently unused */
0065 #define CPCAP_BIT_TS_M2         BIT(2)  /* Currently unused */
0066 #define CPCAP_BIT_TS_M1         BIT(1)  /* Currently unused */
0067 #define CPCAP_BIT_TS_M0         BIT(0)  /* Currently unused */
0068 
0069 #define CPCAP_REG_ADCC2_DEFAULTS    (CPCAP_BIT_AD4_SELECT | \
0070                      CPCAP_BIT_ADTRIG_DIS | \
0071                      CPCAP_BIT_LIADC | \
0072                      CPCAP_BIT_TS_M2 | \
0073                      CPCAP_BIT_TS_M1)
0074 
0075 #define CPCAP_MAX_TEMP_LVL      27
0076 #define CPCAP_FOUR_POINT_TWO_ADC    801
0077 #define ST_ADC_CAL_CHRGI_HIGH_THRESHOLD 530
0078 #define ST_ADC_CAL_CHRGI_LOW_THRESHOLD  494
0079 #define ST_ADC_CAL_BATTI_HIGH_THRESHOLD 530
0080 #define ST_ADC_CAL_BATTI_LOW_THRESHOLD  494
0081 #define ST_ADC_CALIBRATE_DIFF_THRESHOLD 3
0082 
0083 #define CPCAP_ADC_MAX_RETRIES       5   /* Calibration */
0084 
0085 /*
0086  * struct cpcap_adc_ato - timing settings for cpcap adc
0087  *
0088  * Unfortunately no cpcap documentation available, please document when
0089  * using these.
0090  */
0091 struct cpcap_adc_ato {
0092     unsigned short ato_in;
0093     unsigned short atox_in;
0094     unsigned short adc_ps_factor_in;
0095     unsigned short atox_ps_factor_in;
0096     unsigned short ato_out;
0097     unsigned short atox_out;
0098     unsigned short adc_ps_factor_out;
0099     unsigned short atox_ps_factor_out;
0100 };
0101 
0102 /**
0103  * struct cpcap_adc - cpcap adc device driver data
0104  * @reg: cpcap regmap
0105  * @dev: struct device
0106  * @vendor: cpcap vendor
0107  * @irq: interrupt
0108  * @lock: mutex
0109  * @ato: request timings
0110  * @wq_data_avail: work queue
0111  * @done: work done
0112  */
0113 struct cpcap_adc {
0114     struct regmap *reg;
0115     struct device *dev;
0116     u16 vendor;
0117     int irq;
0118     struct mutex lock;  /* ADC register access lock */
0119     const struct cpcap_adc_ato *ato;
0120     wait_queue_head_t wq_data_avail;
0121     bool done;
0122 };
0123 
0124 /*
0125  * enum cpcap_adc_channel - cpcap adc channels
0126  */
0127 enum cpcap_adc_channel {
0128     /* Bank0 channels */
0129     CPCAP_ADC_AD0,      /* Battery temperature */
0130     CPCAP_ADC_BATTP,    /* Battery voltage */
0131     CPCAP_ADC_VBUS,     /* USB VBUS voltage */
0132     CPCAP_ADC_AD3,      /* Die temperature when charging */
0133     CPCAP_ADC_BPLUS_AD4,    /* Another battery or system voltage */
0134     CPCAP_ADC_CHG_ISENSE,   /* Calibrated charge current */
0135     CPCAP_ADC_BATTI,    /* Calibrated system current */
0136     CPCAP_ADC_USB_ID,   /* USB OTG ID, unused on droid 4? */
0137 
0138     /* Bank1 channels */
0139     CPCAP_ADC_AD8,      /* Seems unused */
0140     CPCAP_ADC_AD9,      /* Seems unused */
0141     CPCAP_ADC_LICELL,   /* Maybe system voltage? Always 3V */
0142     CPCAP_ADC_HV_BATTP, /* Another battery detection? */
0143     CPCAP_ADC_TSX1_AD12,    /* Seems unused, for touchscreen? */
0144     CPCAP_ADC_TSX2_AD13,    /* Seems unused, for touchscreen? */
0145     CPCAP_ADC_TSY1_AD14,    /* Seems unused, for touchscreen? */
0146     CPCAP_ADC_TSY2_AD15,    /* Seems unused, for touchscreen? */
0147 
0148     /* Remuxed channels using bank0 entries */
0149     CPCAP_ADC_BATTP_PI16,   /* Alternative mux mode for BATTP */
0150     CPCAP_ADC_BATTI_PI17,   /* Alternative mux mode for BATTI */
0151 
0152     CPCAP_ADC_CHANNEL_NUM,
0153 };
0154 
0155 /*
0156  * enum cpcap_adc_timing - cpcap adc timing options
0157  *
0158  * CPCAP_ADC_TIMING_IMM seems to be immediate with no timings.
0159  * Please document when using.
0160  */
0161 enum cpcap_adc_timing {
0162     CPCAP_ADC_TIMING_IMM,
0163     CPCAP_ADC_TIMING_IN,
0164     CPCAP_ADC_TIMING_OUT,
0165 };
0166 
0167 /**
0168  * struct cpcap_adc_phasing_tbl - cpcap phasing table
0169  * @offset: offset in the phasing table
0170  * @multiplier: multiplier in the phasing table
0171  * @divider: divider in the phasing table
0172  * @min: minimum value
0173  * @max: maximum value
0174  */
0175 struct cpcap_adc_phasing_tbl {
0176     short offset;
0177     unsigned short multiplier;
0178     unsigned short divider;
0179     short min;
0180     short max;
0181 };
0182 
0183 /**
0184  * struct cpcap_adc_conversion_tbl - cpcap conversion table
0185  * @conv_type: conversion type
0186  * @align_offset: align offset
0187  * @conv_offset: conversion offset
0188  * @cal_offset: calibration offset
0189  * @multiplier: conversion multiplier
0190  * @divider: conversion divider
0191  */
0192 struct cpcap_adc_conversion_tbl {
0193     enum iio_chan_info_enum conv_type;
0194     int align_offset;
0195     int conv_offset;
0196     int cal_offset;
0197     int multiplier;
0198     int divider;
0199 };
0200 
0201 /**
0202  * struct cpcap_adc_request - cpcap adc request
0203  * @channel: request channel
0204  * @phase_tbl: channel phasing table
0205  * @conv_tbl: channel conversion table
0206  * @bank_index: channel index within the bank
0207  * @timing: timing settings
0208  * @result: result
0209  */
0210 struct cpcap_adc_request {
0211     int channel;
0212     const struct cpcap_adc_phasing_tbl *phase_tbl;
0213     const struct cpcap_adc_conversion_tbl *conv_tbl;
0214     int bank_index;
0215     enum cpcap_adc_timing timing;
0216     int result;
0217 };
0218 
0219 /* Phasing table for channels. Note that channels 16 & 17 use BATTP and BATTI */
0220 static const struct cpcap_adc_phasing_tbl bank_phasing[] = {
0221     /* Bank0 */
0222     [CPCAP_ADC_AD0] =          {0, 0x80, 0x80,    0, 1023},
0223     [CPCAP_ADC_BATTP] =        {0, 0x80, 0x80,    0, 1023},
0224     [CPCAP_ADC_VBUS] =         {0, 0x80, 0x80,    0, 1023},
0225     [CPCAP_ADC_AD3] =          {0, 0x80, 0x80,    0, 1023},
0226     [CPCAP_ADC_BPLUS_AD4] =    {0, 0x80, 0x80,    0, 1023},
0227     [CPCAP_ADC_CHG_ISENSE] =   {0, 0x80, 0x80, -512,  511},
0228     [CPCAP_ADC_BATTI] =        {0, 0x80, 0x80, -512,  511},
0229     [CPCAP_ADC_USB_ID] =       {0, 0x80, 0x80,    0, 1023},
0230 
0231     /* Bank1 */
0232     [CPCAP_ADC_AD8] =          {0, 0x80, 0x80,    0, 1023},
0233     [CPCAP_ADC_AD9] =          {0, 0x80, 0x80,    0, 1023},
0234     [CPCAP_ADC_LICELL] =       {0, 0x80, 0x80,    0, 1023},
0235     [CPCAP_ADC_HV_BATTP] =     {0, 0x80, 0x80,    0, 1023},
0236     [CPCAP_ADC_TSX1_AD12] =    {0, 0x80, 0x80,    0, 1023},
0237     [CPCAP_ADC_TSX2_AD13] =    {0, 0x80, 0x80,    0, 1023},
0238     [CPCAP_ADC_TSY1_AD14] =    {0, 0x80, 0x80,    0, 1023},
0239     [CPCAP_ADC_TSY2_AD15] =    {0, 0x80, 0x80,    0, 1023},
0240 };
0241 
0242 /*
0243  * Conversion table for channels. Updated during init based on calibration.
0244  * Here too channels 16 & 17 use BATTP and BATTI.
0245  */
0246 static struct cpcap_adc_conversion_tbl bank_conversion[] = {
0247     /* Bank0 */
0248     [CPCAP_ADC_AD0] = {
0249         IIO_CHAN_INFO_PROCESSED,    0,    0, 0,     1,    1,
0250     },
0251     [CPCAP_ADC_BATTP] = {
0252         IIO_CHAN_INFO_PROCESSED,    0, 2400, 0,  2300, 1023,
0253     },
0254     [CPCAP_ADC_VBUS] = {
0255         IIO_CHAN_INFO_PROCESSED,    0,    0, 0, 10000, 1023,
0256     },
0257     [CPCAP_ADC_AD3] = {
0258         IIO_CHAN_INFO_PROCESSED,    0,    0, 0,     1,    1,
0259         },
0260     [CPCAP_ADC_BPLUS_AD4] = {
0261         IIO_CHAN_INFO_PROCESSED,    0, 2400, 0,  2300, 1023,
0262     },
0263     [CPCAP_ADC_CHG_ISENSE] = {
0264         IIO_CHAN_INFO_PROCESSED, -512,    2, 0,  5000, 1023,
0265     },
0266     [CPCAP_ADC_BATTI] = {
0267         IIO_CHAN_INFO_PROCESSED, -512,    2, 0,  5000, 1023,
0268     },
0269     [CPCAP_ADC_USB_ID] = {
0270         IIO_CHAN_INFO_RAW,          0,    0, 0,     1,    1,
0271     },
0272 
0273     /* Bank1 */
0274     [CPCAP_ADC_AD8] = {
0275         IIO_CHAN_INFO_RAW,          0,    0, 0,     1,    1,
0276     },
0277     [CPCAP_ADC_AD9] = {
0278         IIO_CHAN_INFO_RAW,          0,    0, 0,     1,    1,
0279     },
0280     [CPCAP_ADC_LICELL] = {
0281         IIO_CHAN_INFO_PROCESSED,    0,    0, 0,  3400, 1023,
0282     },
0283     [CPCAP_ADC_HV_BATTP] = {
0284         IIO_CHAN_INFO_RAW,          0,    0, 0,     1,    1,
0285     },
0286     [CPCAP_ADC_TSX1_AD12] = {
0287         IIO_CHAN_INFO_RAW,          0,    0, 0,     1,    1,
0288     },
0289     [CPCAP_ADC_TSX2_AD13] = {
0290         IIO_CHAN_INFO_RAW,          0,    0, 0,     1,    1,
0291     },
0292     [CPCAP_ADC_TSY1_AD14] = {
0293         IIO_CHAN_INFO_RAW,          0,    0, 0,     1,    1,
0294     },
0295     [CPCAP_ADC_TSY2_AD15] = {
0296         IIO_CHAN_INFO_RAW,          0,    0, 0,     1,    1,
0297     },
0298 };
0299 
0300 /*
0301  * Temperature lookup table of register values to milliCelcius.
0302  * REVISIT: Check the duplicate 0x3ff entry in a freezer
0303  */
0304 static const int temp_map[CPCAP_MAX_TEMP_LVL][2] = {
0305     { 0x03ff, -40000 },
0306     { 0x03ff, -35000 },
0307     { 0x03ef, -30000 },
0308     { 0x03b2, -25000 },
0309     { 0x036c, -20000 },
0310     { 0x0320, -15000 },
0311     { 0x02d0, -10000 },
0312     { 0x027f, -5000 },
0313     { 0x022f, 0 },
0314     { 0x01e4, 5000 },
0315     { 0x019f, 10000 },
0316     { 0x0161, 15000 },
0317     { 0x012b, 20000 },
0318     { 0x00fc, 25000 },
0319     { 0x00d4, 30000 },
0320     { 0x00b2, 35000 },
0321     { 0x0095, 40000 },
0322     { 0x007d, 45000 },
0323     { 0x0069, 50000 },
0324     { 0x0059, 55000 },
0325     { 0x004b, 60000 },
0326     { 0x003f, 65000 },
0327     { 0x0036, 70000 },
0328     { 0x002e, 75000 },
0329     { 0x0027, 80000 },
0330     { 0x0022, 85000 },
0331     { 0x001d, 90000 },
0332 };
0333 
0334 #define CPCAP_CHAN(_type, _index, _address, _datasheet_name) {  \
0335     .type = (_type), \
0336     .address = (_address), \
0337     .indexed = 1, \
0338     .channel = (_index), \
0339     .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
0340                   BIT(IIO_CHAN_INFO_PROCESSED), \
0341     .scan_index = (_index), \
0342     .scan_type = { \
0343         .sign = 'u', \
0344         .realbits = 10, \
0345         .storagebits = 16, \
0346         .endianness = IIO_CPU, \
0347     }, \
0348     .datasheet_name = (_datasheet_name), \
0349 }
0350 
0351 /*
0352  * The datasheet names are from Motorola mapphone Linux kernel except
0353  * for the last two which might be uncalibrated charge voltage and
0354  * current.
0355  */
0356 static const struct iio_chan_spec cpcap_adc_channels[] = {
0357     /* Bank0 */
0358     CPCAP_CHAN(IIO_TEMP,    0, CPCAP_REG_ADCD0,  "battdetb"),
0359     CPCAP_CHAN(IIO_VOLTAGE, 1, CPCAP_REG_ADCD1,  "battp"),
0360     CPCAP_CHAN(IIO_VOLTAGE, 2, CPCAP_REG_ADCD2,  "vbus"),
0361     CPCAP_CHAN(IIO_TEMP,    3, CPCAP_REG_ADCD3,  "ad3"),
0362     CPCAP_CHAN(IIO_VOLTAGE, 4, CPCAP_REG_ADCD4,  "ad4"),
0363     CPCAP_CHAN(IIO_CURRENT, 5, CPCAP_REG_ADCD5,  "chg_isense"),
0364     CPCAP_CHAN(IIO_CURRENT, 6, CPCAP_REG_ADCD6,  "batti"),
0365     CPCAP_CHAN(IIO_VOLTAGE, 7, CPCAP_REG_ADCD7,  "usb_id"),
0366 
0367     /* Bank1 */
0368     CPCAP_CHAN(IIO_CURRENT, 8, CPCAP_REG_ADCD0,  "ad8"),
0369     CPCAP_CHAN(IIO_VOLTAGE, 9, CPCAP_REG_ADCD1,  "ad9"),
0370     CPCAP_CHAN(IIO_VOLTAGE, 10, CPCAP_REG_ADCD2, "licell"),
0371     CPCAP_CHAN(IIO_VOLTAGE, 11, CPCAP_REG_ADCD3, "hv_battp"),
0372     CPCAP_CHAN(IIO_VOLTAGE, 12, CPCAP_REG_ADCD4, "tsx1_ad12"),
0373     CPCAP_CHAN(IIO_VOLTAGE, 13, CPCAP_REG_ADCD5, "tsx2_ad13"),
0374     CPCAP_CHAN(IIO_VOLTAGE, 14, CPCAP_REG_ADCD6, "tsy1_ad14"),
0375     CPCAP_CHAN(IIO_VOLTAGE, 15, CPCAP_REG_ADCD7, "tsy2_ad15"),
0376 
0377     /* There are two registers with multiplexed functionality */
0378     CPCAP_CHAN(IIO_VOLTAGE, 16, CPCAP_REG_ADCD0, "chg_vsense"),
0379     CPCAP_CHAN(IIO_CURRENT, 17, CPCAP_REG_ADCD1, "batti2"),
0380 };
0381 
0382 static irqreturn_t cpcap_adc_irq_thread(int irq, void *data)
0383 {
0384     struct iio_dev *indio_dev = data;
0385     struct cpcap_adc *ddata = iio_priv(indio_dev);
0386     int error;
0387 
0388     error = regmap_update_bits(ddata->reg, CPCAP_REG_ADCC2,
0389                    CPCAP_BIT_ADTRIG_DIS,
0390                    CPCAP_BIT_ADTRIG_DIS);
0391     if (error)
0392         return IRQ_NONE;
0393 
0394     ddata->done = true;
0395     wake_up_interruptible(&ddata->wq_data_avail);
0396 
0397     return IRQ_HANDLED;
0398 }
0399 
0400 /* ADC calibration functions */
0401 static void cpcap_adc_setup_calibrate(struct cpcap_adc *ddata,
0402                       enum cpcap_adc_channel chan)
0403 {
0404     unsigned int value = 0;
0405     unsigned long timeout = jiffies + msecs_to_jiffies(3000);
0406     int error;
0407 
0408     if ((chan != CPCAP_ADC_CHG_ISENSE) &&
0409         (chan != CPCAP_ADC_BATTI))
0410         return;
0411 
0412     value |= CPCAP_BIT_CAL_MODE | CPCAP_BIT_RAND0;
0413     value |= ((chan << 4) &
0414           (CPCAP_BIT_ADA2 | CPCAP_BIT_ADA1 | CPCAP_BIT_ADA0));
0415 
0416     error = regmap_update_bits(ddata->reg, CPCAP_REG_ADCC1,
0417                    CPCAP_BIT_CAL_MODE | CPCAP_BIT_ATOX |
0418                    CPCAP_BIT_ATO3 | CPCAP_BIT_ATO2 |
0419                    CPCAP_BIT_ATO1 | CPCAP_BIT_ATO0 |
0420                    CPCAP_BIT_ADA2 | CPCAP_BIT_ADA1 |
0421                    CPCAP_BIT_ADA0 | CPCAP_BIT_AD_SEL1 |
0422                    CPCAP_BIT_RAND1 | CPCAP_BIT_RAND0,
0423                    value);
0424     if (error)
0425         return;
0426 
0427     error = regmap_update_bits(ddata->reg, CPCAP_REG_ADCC2,
0428                    CPCAP_BIT_ATOX_PS_FACTOR |
0429                    CPCAP_BIT_ADC_PS_FACTOR1 |
0430                    CPCAP_BIT_ADC_PS_FACTOR0,
0431                    0);
0432     if (error)
0433         return;
0434 
0435     error = regmap_update_bits(ddata->reg, CPCAP_REG_ADCC2,
0436                    CPCAP_BIT_ADTRIG_DIS,
0437                    CPCAP_BIT_ADTRIG_DIS);
0438     if (error)
0439         return;
0440 
0441     error = regmap_update_bits(ddata->reg, CPCAP_REG_ADCC2,
0442                    CPCAP_BIT_ASC,
0443                    CPCAP_BIT_ASC);
0444     if (error)
0445         return;
0446 
0447     do {
0448         schedule_timeout_uninterruptible(1);
0449         error = regmap_read(ddata->reg, CPCAP_REG_ADCC2, &value);
0450         if (error)
0451             return;
0452     } while ((value & CPCAP_BIT_ASC) && time_before(jiffies, timeout));
0453 
0454     if (value & CPCAP_BIT_ASC)
0455         dev_err(ddata->dev,
0456             "Timeout waiting for calibration to complete\n");
0457 
0458     error = regmap_update_bits(ddata->reg, CPCAP_REG_ADCC1,
0459                    CPCAP_BIT_CAL_MODE, 0);
0460     if (error)
0461         return;
0462 }
0463 
0464 static int cpcap_adc_calibrate_one(struct cpcap_adc *ddata,
0465                    int channel,
0466                    u16 calibration_register,
0467                    int lower_threshold,
0468                    int upper_threshold)
0469 {
0470     unsigned int calibration_data[2];
0471     unsigned short cal_data_diff;
0472     int i, error;
0473 
0474     for (i = 0; i < CPCAP_ADC_MAX_RETRIES; i++) {
0475         calibration_data[0]  = 0;
0476         calibration_data[1]  = 0;
0477 
0478         cpcap_adc_setup_calibrate(ddata, channel);
0479         error = regmap_read(ddata->reg, calibration_register,
0480                     &calibration_data[0]);
0481         if (error)
0482             return error;
0483         cpcap_adc_setup_calibrate(ddata, channel);
0484         error = regmap_read(ddata->reg, calibration_register,
0485                     &calibration_data[1]);
0486         if (error)
0487             return error;
0488 
0489         if (calibration_data[0] > calibration_data[1])
0490             cal_data_diff =
0491                 calibration_data[0] - calibration_data[1];
0492         else
0493             cal_data_diff =
0494                 calibration_data[1] - calibration_data[0];
0495 
0496         if (((calibration_data[1] >= lower_threshold) &&
0497              (calibration_data[1] <= upper_threshold) &&
0498              (cal_data_diff <= ST_ADC_CALIBRATE_DIFF_THRESHOLD)) ||
0499             (ddata->vendor == CPCAP_VENDOR_TI)) {
0500             bank_conversion[channel].cal_offset =
0501                 ((short)calibration_data[1] * -1) + 512;
0502             dev_dbg(ddata->dev, "ch%i calibration complete: %i\n",
0503                 channel, bank_conversion[channel].cal_offset);
0504             break;
0505         }
0506         usleep_range(5000, 10000);
0507     }
0508 
0509     return 0;
0510 }
0511 
0512 static int cpcap_adc_calibrate(struct cpcap_adc *ddata)
0513 {
0514     int error;
0515 
0516     error = cpcap_adc_calibrate_one(ddata, CPCAP_ADC_CHG_ISENSE,
0517                     CPCAP_REG_ADCAL1,
0518                     ST_ADC_CAL_CHRGI_LOW_THRESHOLD,
0519                     ST_ADC_CAL_CHRGI_HIGH_THRESHOLD);
0520     if (error)
0521         return error;
0522 
0523     error = cpcap_adc_calibrate_one(ddata, CPCAP_ADC_BATTI,
0524                     CPCAP_REG_ADCAL2,
0525                     ST_ADC_CAL_BATTI_LOW_THRESHOLD,
0526                     ST_ADC_CAL_BATTI_HIGH_THRESHOLD);
0527     if (error)
0528         return error;
0529 
0530     return 0;
0531 }
0532 
0533 /* ADC setup, read and scale functions */
0534 static void cpcap_adc_setup_bank(struct cpcap_adc *ddata,
0535                  struct cpcap_adc_request *req)
0536 {
0537     const struct cpcap_adc_ato *ato = ddata->ato;
0538     unsigned short value1 = 0;
0539     unsigned short value2 = 0;
0540     int error;
0541 
0542     if (!ato)
0543         return;
0544 
0545     switch (req->channel) {
0546     case CPCAP_ADC_AD0:
0547         value2 |= CPCAP_BIT_THERMBIAS_EN;
0548         error = regmap_update_bits(ddata->reg, CPCAP_REG_ADCC2,
0549                        CPCAP_BIT_THERMBIAS_EN,
0550                        value2);
0551         if (error)
0552             return;
0553         usleep_range(800, 1000);
0554         break;
0555     case CPCAP_ADC_AD8 ... CPCAP_ADC_TSY2_AD15:
0556         value1 |= CPCAP_BIT_AD_SEL1;
0557         break;
0558     case CPCAP_ADC_BATTP_PI16 ... CPCAP_ADC_BATTI_PI17:
0559         value1 |= CPCAP_BIT_RAND1;
0560         break;
0561     default:
0562         break;
0563     }
0564 
0565     switch (req->timing) {
0566     case CPCAP_ADC_TIMING_IN:
0567         value1 |= ato->ato_in;
0568         value1 |= ato->atox_in;
0569         value2 |= ato->adc_ps_factor_in;
0570         value2 |= ato->atox_ps_factor_in;
0571         break;
0572     case CPCAP_ADC_TIMING_OUT:
0573         value1 |= ato->ato_out;
0574         value1 |= ato->atox_out;
0575         value2 |= ato->adc_ps_factor_out;
0576         value2 |= ato->atox_ps_factor_out;
0577         break;
0578 
0579     case CPCAP_ADC_TIMING_IMM:
0580     default:
0581         break;
0582     }
0583 
0584     error = regmap_update_bits(ddata->reg, CPCAP_REG_ADCC1,
0585                    CPCAP_BIT_CAL_MODE | CPCAP_BIT_ATOX |
0586                    CPCAP_BIT_ATO3 | CPCAP_BIT_ATO2 |
0587                    CPCAP_BIT_ATO1 | CPCAP_BIT_ATO0 |
0588                    CPCAP_BIT_ADA2 | CPCAP_BIT_ADA1 |
0589                    CPCAP_BIT_ADA0 | CPCAP_BIT_AD_SEL1 |
0590                    CPCAP_BIT_RAND1 | CPCAP_BIT_RAND0,
0591                    value1);
0592     if (error)
0593         return;
0594 
0595     error = regmap_update_bits(ddata->reg, CPCAP_REG_ADCC2,
0596                    CPCAP_BIT_ATOX_PS_FACTOR |
0597                    CPCAP_BIT_ADC_PS_FACTOR1 |
0598                    CPCAP_BIT_ADC_PS_FACTOR0 |
0599                    CPCAP_BIT_THERMBIAS_EN,
0600                    value2);
0601     if (error)
0602         return;
0603 
0604     if (req->timing == CPCAP_ADC_TIMING_IMM) {
0605         error = regmap_update_bits(ddata->reg, CPCAP_REG_ADCC2,
0606                        CPCAP_BIT_ADTRIG_DIS,
0607                        CPCAP_BIT_ADTRIG_DIS);
0608         if (error)
0609             return;
0610 
0611         error = regmap_update_bits(ddata->reg, CPCAP_REG_ADCC2,
0612                        CPCAP_BIT_ASC,
0613                        CPCAP_BIT_ASC);
0614         if (error)
0615             return;
0616     } else {
0617         error = regmap_update_bits(ddata->reg, CPCAP_REG_ADCC2,
0618                        CPCAP_BIT_ADTRIG_ONESHOT,
0619                        CPCAP_BIT_ADTRIG_ONESHOT);
0620         if (error)
0621             return;
0622 
0623         error = regmap_update_bits(ddata->reg, CPCAP_REG_ADCC2,
0624                        CPCAP_BIT_ADTRIG_DIS, 0);
0625         if (error)
0626             return;
0627     }
0628 }
0629 
0630 static int cpcap_adc_start_bank(struct cpcap_adc *ddata,
0631                 struct cpcap_adc_request *req)
0632 {
0633     int i, error;
0634 
0635     req->timing = CPCAP_ADC_TIMING_IMM;
0636     ddata->done = false;
0637 
0638     for (i = 0; i < CPCAP_ADC_MAX_RETRIES; i++) {
0639         cpcap_adc_setup_bank(ddata, req);
0640         error = wait_event_interruptible_timeout(ddata->wq_data_avail,
0641                              ddata->done,
0642                              msecs_to_jiffies(50));
0643         if (error > 0)
0644             return 0;
0645 
0646         if (error == 0) {
0647             error = -ETIMEDOUT;
0648             continue;
0649         }
0650 
0651         if (error < 0)
0652             return error;
0653     }
0654 
0655     return error;
0656 }
0657 
0658 static int cpcap_adc_stop_bank(struct cpcap_adc *ddata)
0659 {
0660     int error;
0661 
0662     error = regmap_update_bits(ddata->reg, CPCAP_REG_ADCC1,
0663                    0xffff,
0664                    CPCAP_REG_ADCC1_DEFAULTS);
0665     if (error)
0666         return error;
0667 
0668     return regmap_update_bits(ddata->reg, CPCAP_REG_ADCC2,
0669                   0xffff,
0670                   CPCAP_REG_ADCC2_DEFAULTS);
0671 }
0672 
0673 static void cpcap_adc_phase(struct cpcap_adc_request *req)
0674 {
0675     const struct cpcap_adc_conversion_tbl *conv_tbl = req->conv_tbl;
0676     const struct cpcap_adc_phasing_tbl *phase_tbl = req->phase_tbl;
0677     int index = req->channel;
0678 
0679     /* Remuxed channels 16 and 17 use BATTP and BATTI entries */
0680     switch (req->channel) {
0681     case CPCAP_ADC_BATTP:
0682     case CPCAP_ADC_BATTP_PI16:
0683         index = req->bank_index;
0684         req->result -= phase_tbl[index].offset;
0685         req->result -= CPCAP_FOUR_POINT_TWO_ADC;
0686         req->result *= phase_tbl[index].multiplier;
0687         if (phase_tbl[index].divider == 0)
0688             return;
0689         req->result /= phase_tbl[index].divider;
0690         req->result += CPCAP_FOUR_POINT_TWO_ADC;
0691         break;
0692     case CPCAP_ADC_BATTI_PI17:
0693         index = req->bank_index;
0694         fallthrough;
0695     default:
0696         req->result += conv_tbl[index].cal_offset;
0697         req->result += conv_tbl[index].align_offset;
0698         req->result *= phase_tbl[index].multiplier;
0699         if (phase_tbl[index].divider == 0)
0700             return;
0701         req->result /= phase_tbl[index].divider;
0702         req->result += phase_tbl[index].offset;
0703         break;
0704     }
0705 
0706     if (req->result < phase_tbl[index].min)
0707         req->result = phase_tbl[index].min;
0708     else if (req->result > phase_tbl[index].max)
0709         req->result = phase_tbl[index].max;
0710 }
0711 
0712 /* Looks up temperatures in a table and calculates averages if needed */
0713 static int cpcap_adc_table_to_millicelcius(unsigned short value)
0714 {
0715     int i, result = 0, alpha;
0716 
0717     if (value <= temp_map[CPCAP_MAX_TEMP_LVL - 1][0])
0718         return temp_map[CPCAP_MAX_TEMP_LVL - 1][1];
0719 
0720     if (value >= temp_map[0][0])
0721         return temp_map[0][1];
0722 
0723     for (i = 0; i < CPCAP_MAX_TEMP_LVL - 1; i++) {
0724         if ((value <= temp_map[i][0]) &&
0725             (value >= temp_map[i + 1][0])) {
0726             if (value == temp_map[i][0]) {
0727                 result = temp_map[i][1];
0728             } else if (value == temp_map[i + 1][0]) {
0729                 result = temp_map[i + 1][1];
0730             } else {
0731                 alpha = ((value - temp_map[i][0]) * 1000) /
0732                     (temp_map[i + 1][0] - temp_map[i][0]);
0733 
0734                 result = temp_map[i][1] +
0735                     ((alpha * (temp_map[i + 1][1] -
0736                          temp_map[i][1])) / 1000);
0737             }
0738             break;
0739         }
0740     }
0741 
0742     return result;
0743 }
0744 
0745 static void cpcap_adc_convert(struct cpcap_adc_request *req)
0746 {
0747     const struct cpcap_adc_conversion_tbl *conv_tbl = req->conv_tbl;
0748     int index = req->channel;
0749 
0750     /* Remuxed channels 16 and 17 use BATTP and BATTI entries */
0751     switch (req->channel) {
0752     case CPCAP_ADC_BATTP_PI16:
0753         index = CPCAP_ADC_BATTP;
0754         break;
0755     case CPCAP_ADC_BATTI_PI17:
0756         index = CPCAP_ADC_BATTI;
0757         break;
0758     default:
0759         break;
0760     }
0761 
0762     /* No conversion for raw channels */
0763     if (conv_tbl[index].conv_type == IIO_CHAN_INFO_RAW)
0764         return;
0765 
0766     /* Temperatures use a lookup table instead of conversion table */
0767     if ((req->channel == CPCAP_ADC_AD0) ||
0768         (req->channel == CPCAP_ADC_AD3)) {
0769         req->result =
0770             cpcap_adc_table_to_millicelcius(req->result);
0771 
0772         return;
0773     }
0774 
0775     /* All processed channels use a conversion table */
0776     req->result *= conv_tbl[index].multiplier;
0777     if (conv_tbl[index].divider == 0)
0778         return;
0779     req->result /= conv_tbl[index].divider;
0780     req->result += conv_tbl[index].conv_offset;
0781 }
0782 
0783 /*
0784  * REVISIT: Check if timed sampling can use multiple channels at the
0785  * same time. If not, replace channel_mask with just channel.
0786  */
0787 static int cpcap_adc_read_bank_scaled(struct cpcap_adc *ddata,
0788                       struct cpcap_adc_request *req)
0789 {
0790     int calibration_data, error, addr;
0791 
0792     if (ddata->vendor == CPCAP_VENDOR_TI) {
0793         error = regmap_read(ddata->reg, CPCAP_REG_ADCAL1,
0794                     &calibration_data);
0795         if (error)
0796             return error;
0797         bank_conversion[CPCAP_ADC_CHG_ISENSE].cal_offset =
0798             ((short)calibration_data * -1) + 512;
0799 
0800         error = regmap_read(ddata->reg, CPCAP_REG_ADCAL2,
0801                     &calibration_data);
0802         if (error)
0803             return error;
0804         bank_conversion[CPCAP_ADC_BATTI].cal_offset =
0805             ((short)calibration_data * -1) + 512;
0806     }
0807 
0808     addr = CPCAP_REG_ADCD0 + req->bank_index * 4;
0809 
0810     error = regmap_read(ddata->reg, addr, &req->result);
0811     if (error)
0812         return error;
0813 
0814     req->result &= 0x3ff;
0815     cpcap_adc_phase(req);
0816     cpcap_adc_convert(req);
0817 
0818     return 0;
0819 }
0820 
0821 static int cpcap_adc_init_request(struct cpcap_adc_request *req,
0822                   int channel)
0823 {
0824     req->channel = channel;
0825     req->phase_tbl = bank_phasing;
0826     req->conv_tbl = bank_conversion;
0827 
0828     switch (channel) {
0829     case CPCAP_ADC_AD0 ... CPCAP_ADC_USB_ID:
0830         req->bank_index = channel;
0831         break;
0832     case CPCAP_ADC_AD8 ... CPCAP_ADC_TSY2_AD15:
0833         req->bank_index = channel - 8;
0834         break;
0835     case CPCAP_ADC_BATTP_PI16:
0836         req->bank_index = CPCAP_ADC_BATTP;
0837         break;
0838     case CPCAP_ADC_BATTI_PI17:
0839         req->bank_index = CPCAP_ADC_BATTI;
0840         break;
0841     default:
0842         return -EINVAL;
0843     }
0844 
0845     return 0;
0846 }
0847 
0848 static int cpcap_adc_read_st_die_temp(struct cpcap_adc *ddata,
0849                       int addr, int *val)
0850 {
0851     int error;
0852 
0853     error = regmap_read(ddata->reg, addr, val);
0854     if (error)
0855         return error;
0856 
0857     *val -= 282;
0858     *val *= 114;
0859     *val += 25000;
0860 
0861     return 0;
0862 }
0863 
0864 static int cpcap_adc_read(struct iio_dev *indio_dev,
0865               struct iio_chan_spec const *chan,
0866               int *val, int *val2, long mask)
0867 {
0868     struct cpcap_adc *ddata = iio_priv(indio_dev);
0869     struct cpcap_adc_request req;
0870     int error;
0871 
0872     error = cpcap_adc_init_request(&req, chan->channel);
0873     if (error)
0874         return error;
0875 
0876     switch (mask) {
0877     case IIO_CHAN_INFO_RAW:
0878         mutex_lock(&ddata->lock);
0879         error = cpcap_adc_start_bank(ddata, &req);
0880         if (error)
0881             goto err_unlock;
0882         error = regmap_read(ddata->reg, chan->address, val);
0883         if (error)
0884             goto err_unlock;
0885         error = cpcap_adc_stop_bank(ddata);
0886         if (error)
0887             goto err_unlock;
0888         mutex_unlock(&ddata->lock);
0889         break;
0890     case IIO_CHAN_INFO_PROCESSED:
0891         mutex_lock(&ddata->lock);
0892         error = cpcap_adc_start_bank(ddata, &req);
0893         if (error)
0894             goto err_unlock;
0895         if ((ddata->vendor == CPCAP_VENDOR_ST) &&
0896             (chan->channel == CPCAP_ADC_AD3)) {
0897             error = cpcap_adc_read_st_die_temp(ddata,
0898                                chan->address,
0899                                &req.result);
0900             if (error)
0901                 goto err_unlock;
0902         } else {
0903             error = cpcap_adc_read_bank_scaled(ddata, &req);
0904             if (error)
0905                 goto err_unlock;
0906         }
0907         error = cpcap_adc_stop_bank(ddata);
0908         if (error)
0909             goto err_unlock;
0910         mutex_unlock(&ddata->lock);
0911         *val = req.result;
0912         break;
0913     default:
0914         return -EINVAL;
0915     }
0916 
0917     return IIO_VAL_INT;
0918 
0919 err_unlock:
0920     mutex_unlock(&ddata->lock);
0921     dev_err(ddata->dev, "error reading ADC: %i\n", error);
0922 
0923     return error;
0924 }
0925 
0926 static const struct iio_info cpcap_adc_info = {
0927     .read_raw = &cpcap_adc_read,
0928 };
0929 
0930 /*
0931  * Configuration for Motorola mapphone series such as droid 4.
0932  * Copied from the Motorola mapphone kernel tree.
0933  */
0934 static const struct cpcap_adc_ato mapphone_adc = {
0935     .ato_in = 0x0480,
0936     .atox_in = 0,
0937     .adc_ps_factor_in = 0x0200,
0938     .atox_ps_factor_in = 0,
0939     .ato_out = 0,
0940     .atox_out = 0,
0941     .adc_ps_factor_out = 0,
0942     .atox_ps_factor_out = 0,
0943 };
0944 
0945 static const struct of_device_id cpcap_adc_id_table[] = {
0946     {
0947         .compatible = "motorola,cpcap-adc",
0948     },
0949     {
0950         .compatible = "motorola,mapphone-cpcap-adc",
0951         .data = &mapphone_adc,
0952     },
0953     { /* sentinel */ },
0954 };
0955 MODULE_DEVICE_TABLE(of, cpcap_adc_id_table);
0956 
0957 static int cpcap_adc_probe(struct platform_device *pdev)
0958 {
0959     struct cpcap_adc *ddata;
0960     struct iio_dev *indio_dev;
0961     int error;
0962 
0963     indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*ddata));
0964     if (!indio_dev) {
0965         dev_err(&pdev->dev, "failed to allocate iio device\n");
0966 
0967         return -ENOMEM;
0968     }
0969     ddata = iio_priv(indio_dev);
0970     ddata->ato = device_get_match_data(&pdev->dev);
0971     if (!ddata->ato)
0972         return -ENODEV;
0973     ddata->dev = &pdev->dev;
0974 
0975     mutex_init(&ddata->lock);
0976     init_waitqueue_head(&ddata->wq_data_avail);
0977 
0978     indio_dev->modes = INDIO_DIRECT_MODE | INDIO_BUFFER_SOFTWARE;
0979     indio_dev->channels = cpcap_adc_channels;
0980     indio_dev->num_channels = ARRAY_SIZE(cpcap_adc_channels);
0981     indio_dev->name = dev_name(&pdev->dev);
0982     indio_dev->info = &cpcap_adc_info;
0983 
0984     ddata->reg = dev_get_regmap(pdev->dev.parent, NULL);
0985     if (!ddata->reg)
0986         return -ENODEV;
0987 
0988     error = cpcap_get_vendor(ddata->dev, ddata->reg, &ddata->vendor);
0989     if (error)
0990         return error;
0991 
0992     platform_set_drvdata(pdev, indio_dev);
0993 
0994     ddata->irq = platform_get_irq_byname(pdev, "adcdone");
0995     if (ddata->irq < 0)
0996         return -ENODEV;
0997 
0998     error = devm_request_threaded_irq(&pdev->dev, ddata->irq, NULL,
0999                       cpcap_adc_irq_thread,
1000                       IRQF_TRIGGER_NONE | IRQF_ONESHOT,
1001                       "cpcap-adc", indio_dev);
1002     if (error) {
1003         dev_err(&pdev->dev, "could not get irq: %i\n",
1004             error);
1005 
1006         return error;
1007     }
1008 
1009     error = cpcap_adc_calibrate(ddata);
1010     if (error)
1011         return error;
1012 
1013     dev_info(&pdev->dev, "CPCAP ADC device probed\n");
1014 
1015     return devm_iio_device_register(&pdev->dev, indio_dev);
1016 }
1017 
1018 static struct platform_driver cpcap_adc_driver = {
1019     .driver = {
1020         .name = "cpcap_adc",
1021         .of_match_table = cpcap_adc_id_table,
1022     },
1023     .probe = cpcap_adc_probe,
1024 };
1025 
1026 module_platform_driver(cpcap_adc_driver);
1027 
1028 MODULE_ALIAS("platform:cpcap_adc");
1029 MODULE_DESCRIPTION("CPCAP ADC driver");
1030 MODULE_AUTHOR("Tony Lindgren <tony@atomide.com");
1031 MODULE_LICENSE("GPL v2");
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