iio/adc/cc10001_adc.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (c) 2014-2015 Imagination Technologies Ltd.
0004  */
0005
0006 #include <linux/clk.h>
0007 #include <linux/delay.h>
0008 #include <linux/err.h>
0009 #include <linux/kernel.h>
0010 #include <linux/module.h>
0011 #include <linux/of.h>
0012 #include <linux/of_device.h>
0013 #include <linux/platform_device.h>
0014 #include <linux/regulator/consumer.h>
0015 #include <linux/slab.h>
0016
0017 #include <linux/iio/buffer.h>
0018 #include <linux/iio/iio.h>
0019 #include <linux/iio/sysfs.h>
0020 #include <linux/iio/trigger.h>
0021 #include <linux/iio/trigger_consumer.h>
0022 #include <linux/iio/triggered_buffer.h>
0023
0024 /* Registers */
0025 #define CC10001_ADC_CONFIG      0x00
0026 #define CC10001_ADC_START_CONV      BIT(4)
0027 #define CC10001_ADC_MODE_SINGLE_CONV    BIT(5)
0028
0029 #define CC10001_ADC_DDATA_OUT       0x04
0030 #define CC10001_ADC_EOC         0x08
0031 #define CC10001_ADC_EOC_SET     BIT(0)
0032
0033 #define CC10001_ADC_CHSEL_SAMPLED   0x0c
0034 #define CC10001_ADC_POWER_DOWN      0x10
0035 #define CC10001_ADC_POWER_DOWN_SET  BIT(0)
0036
0037 #define CC10001_ADC_DEBUG       0x14
0038 #define CC10001_ADC_DATA_COUNT      0x20
0039
0040 #define CC10001_ADC_DATA_MASK       GENMASK(9, 0)
0041 #define CC10001_ADC_NUM_CHANNELS    8
0042 #define CC10001_ADC_CH_MASK     GENMASK(2, 0)
0043
0044 #define CC10001_INVALID_SAMPLED     0xffff
0045 #define CC10001_MAX_POLL_COUNT      20
0046
0047 /*
0048  * As per device specification, wait six clock cycles after power-up to
0049  * activate START. Since adding two more clock cycles delay does not
0050  * impact the performance too much, we are adding two additional cycles delay
0051  * intentionally here.
0052  */
0053 #define CC10001_WAIT_CYCLES     8
0054
0055 struct cc10001_adc_device {
0056     void __iomem *reg_base;
0057     struct clk *adc_clk;
0058     struct regulator *reg;
0059     u16 *buf;
0060
0061     bool shared;
0062     struct mutex lock;
0063     unsigned int start_delay_ns;
0064     unsigned int eoc_delay_ns;
0065 };
0066
0067 static inline void cc10001_adc_write_reg(struct cc10001_adc_device *adc_dev,
0068                      u32 reg, u32 val)
0069 {
0070     writel(val, adc_dev->reg_base + reg);
0071 }
0072
0073 static inline u32 cc10001_adc_read_reg(struct cc10001_adc_device *adc_dev,
0074                        u32 reg)
0075 {
0076     return readl(adc_dev->reg_base + reg);
0077 }
0078
0079 static void cc10001_adc_power_up(struct cc10001_adc_device *adc_dev)
0080 {
0081     cc10001_adc_write_reg(adc_dev, CC10001_ADC_POWER_DOWN, 0);
0082     ndelay(adc_dev->start_delay_ns);
0083 }
0084
0085 static void cc10001_adc_power_down(struct cc10001_adc_device *adc_dev)
0086 {
0087     cc10001_adc_write_reg(adc_dev, CC10001_ADC_POWER_DOWN,
0088                   CC10001_ADC_POWER_DOWN_SET);
0089 }
0090
0091 static void cc10001_adc_start(struct cc10001_adc_device *adc_dev,
0092                   unsigned int channel)
0093 {
0094     u32 val;
0095
0096     /* Channel selection and mode of operation */
0097     val = (channel & CC10001_ADC_CH_MASK) | CC10001_ADC_MODE_SINGLE_CONV;
0098     cc10001_adc_write_reg(adc_dev, CC10001_ADC_CONFIG, val);
0099
0100     udelay(1);
0101     val = cc10001_adc_read_reg(adc_dev, CC10001_ADC_CONFIG);
0102     val = val | CC10001_ADC_START_CONV;
0103     cc10001_adc_write_reg(adc_dev, CC10001_ADC_CONFIG, val);
0104 }
0105
0106 static u16 cc10001_adc_poll_done(struct iio_dev *indio_dev,
0107                  unsigned int channel,
0108                  unsigned int delay)
0109 {
0110     struct cc10001_adc_device *adc_dev = iio_priv(indio_dev);
0111     unsigned int poll_count = 0;
0112
0113     while (!(cc10001_adc_read_reg(adc_dev, CC10001_ADC_EOC) &
0114             CC10001_ADC_EOC_SET)) {
0115
0116         ndelay(delay);
0117         if (poll_count++ == CC10001_MAX_POLL_COUNT)
0118             return CC10001_INVALID_SAMPLED;
0119     }
0120
0121     poll_count = 0;
0122     while ((cc10001_adc_read_reg(adc_dev, CC10001_ADC_CHSEL_SAMPLED) &
0123             CC10001_ADC_CH_MASK) != channel) {
0124
0125         ndelay(delay);
0126         if (poll_count++ == CC10001_MAX_POLL_COUNT)
0127             return CC10001_INVALID_SAMPLED;
0128     }
0129
0130     /* Read the 10 bit output register */
0131     return cc10001_adc_read_reg(adc_dev, CC10001_ADC_DDATA_OUT) &
0132                    CC10001_ADC_DATA_MASK;
0133 }
0134
0135 static irqreturn_t cc10001_adc_trigger_h(int irq, void *p)
0136 {
0137     struct cc10001_adc_device *adc_dev;
0138     struct iio_poll_func *pf = p;
0139     struct iio_dev *indio_dev;
0140     unsigned int delay_ns;
0141     unsigned int channel;
0142     unsigned int scan_idx;
0143     bool sample_invalid;
0144     u16 *data;
0145     int i;
0146
0147     indio_dev = pf->indio_dev;
0148     adc_dev = iio_priv(indio_dev);
0149     data = adc_dev->buf;
0150
0151     mutex_lock(&adc_dev->lock);
0152
0153     if (!adc_dev->shared)
0154         cc10001_adc_power_up(adc_dev);
0155
0156     /* Calculate delay step for eoc and sampled data */
0157     delay_ns = adc_dev->eoc_delay_ns / CC10001_MAX_POLL_COUNT;
0158
0159     i = 0;
0160     sample_invalid = false;
0161     for_each_set_bit(scan_idx, indio_dev->active_scan_mask,
0162                   indio_dev->masklength) {
0163
0164         channel = indio_dev->channels[scan_idx].channel;
0165         cc10001_adc_start(adc_dev, channel);
0166
0167         data[i] = cc10001_adc_poll_done(indio_dev, channel, delay_ns);
0168         if (data[i] == CC10001_INVALID_SAMPLED) {
0169             dev_warn(&indio_dev->dev,
0170                  "invalid sample on channel %d\n", channel);
0171             sample_invalid = true;
0172             goto done;
0173         }
0174         i++;
0175     }
0176
0177 done:
0178     if (!adc_dev->shared)
0179         cc10001_adc_power_down(adc_dev);
0180
0181     mutex_unlock(&adc_dev->lock);
0182
0183     if (!sample_invalid)
0184         iio_push_to_buffers_with_timestamp(indio_dev, data,
0185                            iio_get_time_ns(indio_dev));
0186     iio_trigger_notify_done(indio_dev->trig);
0187
0188     return IRQ_HANDLED;
0189 }
0190
0191 static u16 cc10001_adc_read_raw_voltage(struct iio_dev *indio_dev,
0192                     struct iio_chan_spec const *chan)
0193 {
0194     struct cc10001_adc_device *adc_dev = iio_priv(indio_dev);
0195     unsigned int delay_ns;
0196     u16 val;
0197
0198     if (!adc_dev->shared)
0199         cc10001_adc_power_up(adc_dev);
0200
0201     /* Calculate delay step for eoc and sampled data */
0202     delay_ns = adc_dev->eoc_delay_ns / CC10001_MAX_POLL_COUNT;
0203
0204     cc10001_adc_start(adc_dev, chan->channel);
0205
0206     val = cc10001_adc_poll_done(indio_dev, chan->channel, delay_ns);
0207
0208     if (!adc_dev->shared)
0209         cc10001_adc_power_down(adc_dev);
0210
0211     return val;
0212 }
0213
0214 static int cc10001_adc_read_raw(struct iio_dev *indio_dev,
0215                  struct iio_chan_spec const *chan,
0216                  int *val, int *val2, long mask)
0217 {
0218     struct cc10001_adc_device *adc_dev = iio_priv(indio_dev);
0219     int ret;
0220
0221     switch (mask) {
0222     case IIO_CHAN_INFO_RAW:
0223         if (iio_buffer_enabled(indio_dev))
0224             return -EBUSY;
0225         mutex_lock(&adc_dev->lock);
0226         *val = cc10001_adc_read_raw_voltage(indio_dev, chan);
0227         mutex_unlock(&adc_dev->lock);
0228
0229         if (*val == CC10001_INVALID_SAMPLED)
0230             return -EIO;
0231         return IIO_VAL_INT;
0232
0233     case IIO_CHAN_INFO_SCALE:
0234         ret = regulator_get_voltage(adc_dev->reg);
0235         if (ret < 0)
0236             return ret;
0237
0238         *val = ret / 1000;
0239         *val2 = chan->scan_type.realbits;
0240         return IIO_VAL_FRACTIONAL_LOG2;
0241
0242     default:
0243         return -EINVAL;
0244     }
0245 }
0246
0247 static int cc10001_update_scan_mode(struct iio_dev *indio_dev,
0248                     const unsigned long *scan_mask)
0249 {
0250     struct cc10001_adc_device *adc_dev = iio_priv(indio_dev);
0251
0252     kfree(adc_dev->buf);
0253     adc_dev->buf = kmalloc(indio_dev->scan_bytes, GFP_KERNEL);
0254     if (!adc_dev->buf)
0255         return -ENOMEM;
0256
0257     return 0;
0258 }
0259
0260 static const struct iio_info cc10001_adc_info = {
0261     .read_raw = &cc10001_adc_read_raw,
0262     .update_scan_mode = &cc10001_update_scan_mode,
0263 };
0264
0265 static int cc10001_adc_channel_init(struct iio_dev *indio_dev,
0266                     unsigned long channel_map)
0267 {
0268     struct iio_chan_spec *chan_array, *timestamp;
0269     unsigned int bit, idx = 0;
0270
0271     indio_dev->num_channels = bitmap_weight(&channel_map,
0272                         CC10001_ADC_NUM_CHANNELS) + 1;
0273
0274     chan_array = devm_kcalloc(&indio_dev->dev, indio_dev->num_channels,
0275                   sizeof(struct iio_chan_spec),
0276                   GFP_KERNEL);
0277     if (!chan_array)
0278         return -ENOMEM;
0279
0280     for_each_set_bit(bit, &channel_map, CC10001_ADC_NUM_CHANNELS) {
0281         struct iio_chan_spec *chan = &chan_array[idx];
0282
0283         chan->type = IIO_VOLTAGE;
0284         chan->indexed = 1;
0285         chan->channel = bit;
0286         chan->scan_index = idx;
0287         chan->scan_type.sign = 'u';
0288         chan->scan_type.realbits = 10;
0289         chan->scan_type.storagebits = 16;
0290         chan->info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE);
0291         chan->info_mask_separate = BIT(IIO_CHAN_INFO_RAW);
0292         idx++;
0293     }
0294
0295     timestamp = &chan_array[idx];
0296     timestamp->type = IIO_TIMESTAMP;
0297     timestamp->channel = -1;
0298     timestamp->scan_index = idx;
0299     timestamp->scan_type.sign = 's';
0300     timestamp->scan_type.realbits = 64;
0301     timestamp->scan_type.storagebits = 64;
0302
0303     indio_dev->channels = chan_array;
0304
0305     return 0;
0306 }
0307
0308 static int cc10001_adc_probe(struct platform_device *pdev)
0309 {
0310     struct device_node *node = pdev->dev.of_node;
0311     struct cc10001_adc_device *adc_dev;
0312     unsigned long adc_clk_rate;
0313     struct iio_dev *indio_dev;
0314     unsigned long channel_map;
0315     int ret;
0316
0317     indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*adc_dev));
0318     if (indio_dev == NULL)
0319         return -ENOMEM;
0320
0321     adc_dev = iio_priv(indio_dev);
0322
0323     channel_map = GENMASK(CC10001_ADC_NUM_CHANNELS - 1, 0);
0324     if (!of_property_read_u32(node, "adc-reserved-channels", &ret)) {
0325         adc_dev->shared = true;
0326         channel_map &= ~ret;
0327     }
0328
0329     adc_dev->reg = devm_regulator_get(&pdev->dev, "vref");
0330     if (IS_ERR(adc_dev->reg))
0331         return PTR_ERR(adc_dev->reg);
0332
0333     ret = regulator_enable(adc_dev->reg);
0334     if (ret)
0335         return ret;
0336
0337     indio_dev->name = dev_name(&pdev->dev);
0338     indio_dev->info = &cc10001_adc_info;
0339     indio_dev->modes = INDIO_DIRECT_MODE;
0340
0341     adc_dev->reg_base = devm_platform_ioremap_resource(pdev, 0);
0342     if (IS_ERR(adc_dev->reg_base)) {
0343         ret = PTR_ERR(adc_dev->reg_base);
0344         goto err_disable_reg;
0345     }
0346
0347     adc_dev->adc_clk = devm_clk_get(&pdev->dev, "adc");
0348     if (IS_ERR(adc_dev->adc_clk)) {
0349         dev_err(&pdev->dev, "failed to get the clock\n");
0350         ret = PTR_ERR(adc_dev->adc_clk);
0351         goto err_disable_reg;
0352     }
0353
0354     ret = clk_prepare_enable(adc_dev->adc_clk);
0355     if (ret) {
0356         dev_err(&pdev->dev, "failed to enable the clock\n");
0357         goto err_disable_reg;
0358     }
0359
0360     adc_clk_rate = clk_get_rate(adc_dev->adc_clk);
0361     if (!adc_clk_rate) {
0362         ret = -EINVAL;
0363         dev_err(&pdev->dev, "null clock rate!\n");
0364         goto err_disable_clk;
0365     }
0366
0367     adc_dev->eoc_delay_ns = NSEC_PER_SEC / adc_clk_rate;
0368     adc_dev->start_delay_ns = adc_dev->eoc_delay_ns * CC10001_WAIT_CYCLES;
0369
0370     /*
0371      * There is only one register to power-up/power-down the AUX ADC.
0372      * If the ADC is shared among multiple CPUs, always power it up here.
0373      * If the ADC is used only by the MIPS, power-up/power-down at runtime.
0374      */
0375     if (adc_dev->shared)
0376         cc10001_adc_power_up(adc_dev);
0377
0378     /* Setup the ADC channels available on the device */
0379     ret = cc10001_adc_channel_init(indio_dev, channel_map);
0380     if (ret < 0)
0381         goto err_disable_clk;
0382
0383     mutex_init(&adc_dev->lock);
0384
0385     ret = iio_triggered_buffer_setup(indio_dev, NULL,
0386                      &cc10001_adc_trigger_h, NULL);
0387     if (ret < 0)
0388         goto err_disable_clk;
0389
0390     ret = iio_device_register(indio_dev);
0391     if (ret < 0)
0392         goto err_cleanup_buffer;
0393
0394     platform_set_drvdata(pdev, indio_dev);
0395
0396     return 0;
0397
0398 err_cleanup_buffer:
0399     iio_triggered_buffer_cleanup(indio_dev);
0400 err_disable_clk:
0401     clk_disable_unprepare(adc_dev->adc_clk);
0402 err_disable_reg:
0403     regulator_disable(adc_dev->reg);
0404     return ret;
0405 }
0406
0407 static int cc10001_adc_remove(struct platform_device *pdev)
0408 {
0409     struct iio_dev *indio_dev = platform_get_drvdata(pdev);
0410     struct cc10001_adc_device *adc_dev = iio_priv(indio_dev);
0411
0412     cc10001_adc_power_down(adc_dev);
0413     iio_device_unregister(indio_dev);
0414     iio_triggered_buffer_cleanup(indio_dev);
0415     clk_disable_unprepare(adc_dev->adc_clk);
0416     regulator_disable(adc_dev->reg);
0417
0418     return 0;
0419 }
0420
0421 static const struct of_device_id cc10001_adc_dt_ids[] = {
0422     { .compatible = "cosmic,10001-adc", },
0423     { }
0424 };
0425 MODULE_DEVICE_TABLE(of, cc10001_adc_dt_ids);
0426
0427 static struct platform_driver cc10001_adc_driver = {
0428     .driver = {
0429         .name   = "cc10001-adc",
0430         .of_match_table = cc10001_adc_dt_ids,
0431     },
0432     .probe  = cc10001_adc_probe,
0433     .remove = cc10001_adc_remove,
0434 };
0435 module_platform_driver(cc10001_adc_driver);
0436
0437 MODULE_AUTHOR("Phani Movva <Phani.Movva@imgtec.com>");
0438 MODULE_DESCRIPTION("Cosmic Circuits ADC driver");
0439 MODULE_LICENSE("GPL v2");