iio/adc/berlin2-adc.c

0001 /*
0002  * Marvell Berlin2 ADC driver
0003  *
0004  * Copyright (C) 2015 Marvell Technology Group Ltd.
0005  *
0006  * Antoine Tenart <antoine.tenart@free-electrons.com>
0007  *
0008  * This file is licensed under the terms of the GNU General Public
0009  * License version 2. This program is licensed "as is" without any
0010  * warranty of any kind, whether express or implied.
0011  */
0012
0013 #include <linux/iio/iio.h>
0014 #include <linux/iio/driver.h>
0015 #include <linux/iio/machine.h>
0016 #include <linux/interrupt.h>
0017 #include <linux/kernel.h>
0018 #include <linux/mod_devicetable.h>
0019 #include <linux/module.h>
0020 #include <linux/of.h>
0021 #include <linux/platform_device.h>
0022 #include <linux/slab.h>
0023 #include <linux/mfd/syscon.h>
0024 #include <linux/regmap.h>
0025 #include <linux/sched.h>
0026 #include <linux/wait.h>
0027
0028 #define BERLIN2_SM_CTRL             0x14
0029 #define  BERLIN2_SM_CTRL_SM_SOC_INT     BIT(1)
0030 #define  BERLIN2_SM_CTRL_SOC_SM_INT     BIT(2)
0031 #define  BERLIN2_SM_CTRL_ADC_SEL(x)     ((x) << 5)  /* 0-15 */
0032 #define  BERLIN2_SM_CTRL_ADC_SEL_MASK       GENMASK(8, 5)
0033 #define  BERLIN2_SM_CTRL_ADC_POWER      BIT(9)
0034 #define  BERLIN2_SM_CTRL_ADC_CLKSEL_DIV2    (0x0 << 10)
0035 #define  BERLIN2_SM_CTRL_ADC_CLKSEL_DIV3    (0x1 << 10)
0036 #define  BERLIN2_SM_CTRL_ADC_CLKSEL_DIV4    (0x2 << 10)
0037 #define  BERLIN2_SM_CTRL_ADC_CLKSEL_DIV8    (0x3 << 10)
0038 #define  BERLIN2_SM_CTRL_ADC_CLKSEL_MASK    GENMASK(11, 10)
0039 #define  BERLIN2_SM_CTRL_ADC_START      BIT(12)
0040 #define  BERLIN2_SM_CTRL_ADC_RESET      BIT(13)
0041 #define  BERLIN2_SM_CTRL_ADC_BANDGAP_RDY    BIT(14)
0042 #define  BERLIN2_SM_CTRL_ADC_CONT_SINGLE    (0x0 << 15)
0043 #define  BERLIN2_SM_CTRL_ADC_CONT_CONTINUOUS    (0x1 << 15)
0044 #define  BERLIN2_SM_CTRL_ADC_BUFFER_EN      BIT(16)
0045 #define  BERLIN2_SM_CTRL_ADC_VREF_EXT       (0x0 << 17)
0046 #define  BERLIN2_SM_CTRL_ADC_VREF_INT       (0x1 << 17)
0047 #define  BERLIN2_SM_CTRL_ADC_ROTATE     BIT(19)
0048 #define  BERLIN2_SM_CTRL_TSEN_EN        BIT(20)
0049 #define  BERLIN2_SM_CTRL_TSEN_CLK_SEL_125   (0x0 << 21) /* 1.25 MHz */
0050 #define  BERLIN2_SM_CTRL_TSEN_CLK_SEL_250   (0x1 << 21) /* 2.5 MHz */
0051 #define  BERLIN2_SM_CTRL_TSEN_MODE_0_125    (0x0 << 22) /* 0-125 C */
0052 #define  BERLIN2_SM_CTRL_TSEN_MODE_10_50    (0x1 << 22) /* 10-50 C */
0053 #define  BERLIN2_SM_CTRL_TSEN_RESET     BIT(29)
0054 #define BERLIN2_SM_ADC_DATA         0x20
0055 #define  BERLIN2_SM_ADC_MASK            GENMASK(9, 0)
0056 #define BERLIN2_SM_ADC_STATUS           0x1c
0057 #define  BERLIN2_SM_ADC_STATUS_DATA_RDY(x)  BIT(x)      /* 0-15 */
0058 #define  BERLIN2_SM_ADC_STATUS_DATA_RDY_MASK    GENMASK(15, 0)
0059 #define  BERLIN2_SM_ADC_STATUS_INT_EN(x)    (BIT(x) << 16)  /* 0-15 */
0060 #define  BERLIN2_SM_ADC_STATUS_INT_EN_MASK  GENMASK(31, 16)
0061 #define BERLIN2_SM_TSEN_STATUS          0x24
0062 #define  BERLIN2_SM_TSEN_STATUS_DATA_RDY    BIT(0)
0063 #define  BERLIN2_SM_TSEN_STATUS_INT_EN      BIT(1)
0064 #define BERLIN2_SM_TSEN_DATA            0x28
0065 #define  BERLIN2_SM_TSEN_MASK           GENMASK(9, 0)
0066 #define BERLIN2_SM_TSEN_CTRL            0x74
0067 #define  BERLIN2_SM_TSEN_CTRL_START     BIT(8)
0068 #define  BERLIN2_SM_TSEN_CTRL_SETTLING_4    (0x0 << 21) /* 4 us */
0069 #define  BERLIN2_SM_TSEN_CTRL_SETTLING_12   (0x1 << 21) /* 12 us */
0070 #define  BERLIN2_SM_TSEN_CTRL_SETTLING_MASK BIT(21)
0071 #define  BERLIN2_SM_TSEN_CTRL_TRIM(x)       ((x) << 22)
0072 #define  BERLIN2_SM_TSEN_CTRL_TRIM_MASK     GENMASK(25, 22)
0073
0074 struct berlin2_adc_priv {
0075     struct regmap       *regmap;
0076     struct mutex        lock;
0077     wait_queue_head_t   wq;
0078     bool            data_available;
0079     int         data;
0080 };
0081
0082 #define BERLIN2_ADC_CHANNEL(n, t)                   \
0083     {                               \
0084         .channel        = n,                \
0085         .datasheet_name     = "channel"#n,          \
0086         .type           = t,                \
0087         .indexed        = 1,                \
0088         .info_mask_separate = BIT(IIO_CHAN_INFO_RAW),   \
0089     }
0090
0091 static const struct iio_chan_spec berlin2_adc_channels[] = {
0092     BERLIN2_ADC_CHANNEL(0, IIO_VOLTAGE),    /* external input */
0093     BERLIN2_ADC_CHANNEL(1, IIO_VOLTAGE),    /* external input */
0094     BERLIN2_ADC_CHANNEL(2, IIO_VOLTAGE),    /* external input */
0095     BERLIN2_ADC_CHANNEL(3, IIO_VOLTAGE),    /* external input */
0096     BERLIN2_ADC_CHANNEL(4, IIO_VOLTAGE),    /* reserved */
0097     BERLIN2_ADC_CHANNEL(5, IIO_VOLTAGE),    /* reserved */
0098     {                   /* temperature sensor */
0099         .channel        = 6,
0100         .datasheet_name     = "channel6",
0101         .type           = IIO_TEMP,
0102         .indexed        = 0,
0103         .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED),
0104     },
0105     BERLIN2_ADC_CHANNEL(7, IIO_VOLTAGE),    /* reserved */
0106     IIO_CHAN_SOFT_TIMESTAMP(8),     /* timestamp */
0107 };
0108
0109 static int berlin2_adc_read(struct iio_dev *indio_dev, int channel)
0110 {
0111     struct berlin2_adc_priv *priv = iio_priv(indio_dev);
0112     int data, ret;
0113
0114     mutex_lock(&priv->lock);
0115
0116     /* Enable the interrupts */
0117     regmap_write(priv->regmap, BERLIN2_SM_ADC_STATUS,
0118              BERLIN2_SM_ADC_STATUS_INT_EN(channel));
0119
0120     /* Configure the ADC */
0121     regmap_update_bits(priv->regmap, BERLIN2_SM_CTRL,
0122                BERLIN2_SM_CTRL_ADC_RESET |
0123                BERLIN2_SM_CTRL_ADC_SEL_MASK |
0124                BERLIN2_SM_CTRL_ADC_START,
0125                BERLIN2_SM_CTRL_ADC_SEL(channel) |
0126                BERLIN2_SM_CTRL_ADC_START);
0127
0128     ret = wait_event_interruptible_timeout(priv->wq, priv->data_available,
0129                            msecs_to_jiffies(1000));
0130
0131     /* Disable the interrupts */
0132     regmap_update_bits(priv->regmap, BERLIN2_SM_ADC_STATUS,
0133                BERLIN2_SM_ADC_STATUS_INT_EN(channel), 0);
0134
0135     if (ret == 0)
0136         ret = -ETIMEDOUT;
0137     if (ret < 0) {
0138         mutex_unlock(&priv->lock);
0139         return ret;
0140     }
0141
0142     regmap_update_bits(priv->regmap, BERLIN2_SM_CTRL,
0143                BERLIN2_SM_CTRL_ADC_START, 0);
0144
0145     data = priv->data;
0146     priv->data_available = false;
0147
0148     mutex_unlock(&priv->lock);
0149
0150     return data;
0151 }
0152
0153 static int berlin2_adc_tsen_read(struct iio_dev *indio_dev)
0154 {
0155     struct berlin2_adc_priv *priv = iio_priv(indio_dev);
0156     int data, ret;
0157
0158     mutex_lock(&priv->lock);
0159
0160     /* Enable interrupts */
0161     regmap_write(priv->regmap, BERLIN2_SM_TSEN_STATUS,
0162              BERLIN2_SM_TSEN_STATUS_INT_EN);
0163
0164     /* Configure the ADC */
0165     regmap_update_bits(priv->regmap, BERLIN2_SM_CTRL,
0166                BERLIN2_SM_CTRL_TSEN_RESET |
0167                BERLIN2_SM_CTRL_ADC_ROTATE,
0168                BERLIN2_SM_CTRL_ADC_ROTATE);
0169
0170     /* Configure the temperature sensor */
0171     regmap_update_bits(priv->regmap, BERLIN2_SM_TSEN_CTRL,
0172                BERLIN2_SM_TSEN_CTRL_TRIM_MASK |
0173                BERLIN2_SM_TSEN_CTRL_SETTLING_MASK |
0174                BERLIN2_SM_TSEN_CTRL_START,
0175                BERLIN2_SM_TSEN_CTRL_TRIM(3) |
0176                BERLIN2_SM_TSEN_CTRL_SETTLING_12 |
0177                BERLIN2_SM_TSEN_CTRL_START);
0178
0179     ret = wait_event_interruptible_timeout(priv->wq, priv->data_available,
0180                            msecs_to_jiffies(1000));
0181
0182     /* Disable interrupts */
0183     regmap_update_bits(priv->regmap, BERLIN2_SM_TSEN_STATUS,
0184                BERLIN2_SM_TSEN_STATUS_INT_EN, 0);
0185
0186     if (ret == 0)
0187         ret = -ETIMEDOUT;
0188     if (ret < 0) {
0189         mutex_unlock(&priv->lock);
0190         return ret;
0191     }
0192
0193     regmap_update_bits(priv->regmap, BERLIN2_SM_TSEN_CTRL,
0194                BERLIN2_SM_TSEN_CTRL_START, 0);
0195
0196     data = priv->data;
0197     priv->data_available = false;
0198
0199     mutex_unlock(&priv->lock);
0200
0201     return data;
0202 }
0203
0204 static int berlin2_adc_read_raw(struct iio_dev *indio_dev,
0205                 struct iio_chan_spec const *chan, int *val,
0206                 int *val2, long mask)
0207 {
0208     int temp;
0209
0210     switch (mask) {
0211     case IIO_CHAN_INFO_RAW:
0212         if (chan->type != IIO_VOLTAGE)
0213             return -EINVAL;
0214
0215         *val = berlin2_adc_read(indio_dev, chan->channel);
0216         if (*val < 0)
0217             return *val;
0218
0219         return IIO_VAL_INT;
0220     case IIO_CHAN_INFO_PROCESSED:
0221         if (chan->type != IIO_TEMP)
0222             return -EINVAL;
0223
0224         temp = berlin2_adc_tsen_read(indio_dev);
0225         if (temp < 0)
0226             return temp;
0227
0228         if (temp > 2047)
0229             temp -= 4096;
0230
0231         /* Convert to milli Celsius */
0232         *val = ((temp * 100000) / 264 - 270000);
0233         return IIO_VAL_INT;
0234     default:
0235         break;
0236     }
0237
0238     return -EINVAL;
0239 }
0240
0241 static irqreturn_t berlin2_adc_irq(int irq, void *private)
0242 {
0243     struct berlin2_adc_priv *priv = iio_priv(private);
0244     unsigned val;
0245
0246     regmap_read(priv->regmap, BERLIN2_SM_ADC_STATUS, &val);
0247     if (val & BERLIN2_SM_ADC_STATUS_DATA_RDY_MASK) {
0248         regmap_read(priv->regmap, BERLIN2_SM_ADC_DATA, &priv->data);
0249         priv->data &= BERLIN2_SM_ADC_MASK;
0250
0251         val &= ~BERLIN2_SM_ADC_STATUS_DATA_RDY_MASK;
0252         regmap_write(priv->regmap, BERLIN2_SM_ADC_STATUS, val);
0253
0254         priv->data_available = true;
0255         wake_up_interruptible(&priv->wq);
0256     }
0257
0258     return IRQ_HANDLED;
0259 }
0260
0261 static irqreturn_t berlin2_adc_tsen_irq(int irq, void *private)
0262 {
0263     struct berlin2_adc_priv *priv = iio_priv(private);
0264     unsigned val;
0265
0266     regmap_read(priv->regmap, BERLIN2_SM_TSEN_STATUS, &val);
0267     if (val & BERLIN2_SM_TSEN_STATUS_DATA_RDY) {
0268         regmap_read(priv->regmap, BERLIN2_SM_TSEN_DATA, &priv->data);
0269         priv->data &= BERLIN2_SM_TSEN_MASK;
0270
0271         val &= ~BERLIN2_SM_TSEN_STATUS_DATA_RDY;
0272         regmap_write(priv->regmap, BERLIN2_SM_TSEN_STATUS, val);
0273
0274         priv->data_available = true;
0275         wake_up_interruptible(&priv->wq);
0276     }
0277
0278     return IRQ_HANDLED;
0279 }
0280
0281 static const struct iio_info berlin2_adc_info = {
0282     .read_raw   = berlin2_adc_read_raw,
0283 };
0284
0285 static void berlin2_adc_powerdown(void *regmap)
0286 {
0287     regmap_update_bits(regmap, BERLIN2_SM_CTRL,
0288                BERLIN2_SM_CTRL_ADC_POWER, 0);
0289
0290 }
0291
0292 static int berlin2_adc_probe(struct platform_device *pdev)
0293 {
0294     struct iio_dev *indio_dev;
0295     struct berlin2_adc_priv *priv;
0296     struct device_node *parent_np = of_get_parent(pdev->dev.of_node);
0297     int irq, tsen_irq;
0298     int ret;
0299
0300     indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*priv));
0301     if (!indio_dev)
0302         return -ENOMEM;
0303
0304     priv = iio_priv(indio_dev);
0305
0306     priv->regmap = syscon_node_to_regmap(parent_np);
0307     of_node_put(parent_np);
0308     if (IS_ERR(priv->regmap))
0309         return PTR_ERR(priv->regmap);
0310
0311     irq = platform_get_irq_byname(pdev, "adc");
0312     if (irq < 0)
0313         return irq;
0314
0315     tsen_irq = platform_get_irq_byname(pdev, "tsen");
0316     if (tsen_irq < 0)
0317         return tsen_irq;
0318
0319     ret = devm_request_irq(&pdev->dev, irq, berlin2_adc_irq, 0,
0320                    pdev->dev.driver->name, indio_dev);
0321     if (ret)
0322         return ret;
0323
0324     ret = devm_request_irq(&pdev->dev, tsen_irq, berlin2_adc_tsen_irq,
0325                    0, pdev->dev.driver->name, indio_dev);
0326     if (ret)
0327         return ret;
0328
0329     init_waitqueue_head(&priv->wq);
0330     mutex_init(&priv->lock);
0331
0332     indio_dev->name = dev_name(&pdev->dev);
0333     indio_dev->modes = INDIO_DIRECT_MODE;
0334     indio_dev->info = &berlin2_adc_info;
0335
0336     indio_dev->channels = berlin2_adc_channels;
0337     indio_dev->num_channels = ARRAY_SIZE(berlin2_adc_channels);
0338
0339     /* Power up the ADC */
0340     regmap_update_bits(priv->regmap, BERLIN2_SM_CTRL,
0341                BERLIN2_SM_CTRL_ADC_POWER,
0342                BERLIN2_SM_CTRL_ADC_POWER);
0343
0344     ret = devm_add_action_or_reset(&pdev->dev, berlin2_adc_powerdown,
0345                        priv->regmap);
0346     if (ret)
0347         return ret;
0348
0349     return devm_iio_device_register(&pdev->dev, indio_dev);
0350 }
0351
0352 static const struct of_device_id berlin2_adc_match[] = {
0353     { .compatible = "marvell,berlin2-adc", },
0354     { },
0355 };
0356 MODULE_DEVICE_TABLE(of, berlin2_adc_match);
0357
0358 static struct platform_driver berlin2_adc_driver = {
0359     .driver = {
0360         .name       = "berlin2-adc",
0361         .of_match_table = berlin2_adc_match,
0362     },
0363     .probe  = berlin2_adc_probe,
0364 };
0365 module_platform_driver(berlin2_adc_driver);
0366
0367 MODULE_AUTHOR("Antoine Tenart <antoine.tenart@free-electrons.com>");
0368 MODULE_DESCRIPTION("Marvell Berlin2 ADC driver");
0369 MODULE_LICENSE("GPL v2");