iio/adc/bcm_iproc_adc.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright 2016 Broadcom
0004  */
0005
0006 #include <linux/module.h>
0007 #include <linux/mod_devicetable.h>
0008 #include <linux/io.h>
0009 #include <linux/clk.h>
0010 #include <linux/mfd/syscon.h>
0011 #include <linux/regmap.h>
0012 #include <linux/delay.h>
0013 #include <linux/interrupt.h>
0014 #include <linux/platform_device.h>
0015
0016 #include <linux/iio/iio.h>
0017
0018 /* Below Register's are common to IPROC ADC and Touchscreen IP */
0019 #define IPROC_REGCTL1           0x00
0020 #define IPROC_REGCTL2           0x04
0021 #define IPROC_INTERRUPT_THRES       0x08
0022 #define IPROC_INTERRUPT_MASK        0x0c
0023 #define IPROC_INTERRUPT_STATUS      0x10
0024 #define IPROC_ANALOG_CONTROL        0x1c
0025 #define IPROC_CONTROLLER_STATUS     0x14
0026 #define IPROC_AUX_DATA          0x20
0027 #define IPROC_SOFT_BYPASS_CONTROL   0x38
0028 #define IPROC_SOFT_BYPASS_DATA      0x3C
0029
0030 /* IPROC ADC Channel register offsets */
0031 #define IPROC_ADC_CHANNEL_REGCTL1       0x800
0032 #define IPROC_ADC_CHANNEL_REGCTL2       0x804
0033 #define IPROC_ADC_CHANNEL_STATUS        0x808
0034 #define IPROC_ADC_CHANNEL_INTERRUPT_STATUS  0x80c
0035 #define IPROC_ADC_CHANNEL_INTERRUPT_MASK    0x810
0036 #define IPROC_ADC_CHANNEL_DATA          0x814
0037 #define IPROC_ADC_CHANNEL_OFFSET        0x20
0038
0039 /* Bit definitions for IPROC_REGCTL2 */
0040 #define IPROC_ADC_AUXIN_SCAN_ENA    BIT(0)
0041 #define IPROC_ADC_PWR_LDO       BIT(5)
0042 #define IPROC_ADC_PWR_ADC       BIT(4)
0043 #define IPROC_ADC_PWR_BG        BIT(3)
0044 #define IPROC_ADC_CONTROLLER_EN     BIT(17)
0045
0046 /* Bit definitions for IPROC_INTERRUPT_MASK and IPROC_INTERRUPT_STATUS */
0047 #define IPROC_ADC_AUXDATA_RDY_INTR  BIT(3)
0048 #define IPROC_ADC_INTR          9
0049 #define IPROC_ADC_INTR_MASK     (0xFF << IPROC_ADC_INTR)
0050
0051 /* Bit definitions for IPROC_ANALOG_CONTROL */
0052 #define IPROC_ADC_CHANNEL_SEL       11
0053 #define IPROC_ADC_CHANNEL_SEL_MASK  (0x7 << IPROC_ADC_CHANNEL_SEL)
0054
0055 /* Bit definitions for IPROC_ADC_CHANNEL_REGCTL1 */
0056 #define IPROC_ADC_CHANNEL_ROUNDS    0x2
0057 #define IPROC_ADC_CHANNEL_ROUNDS_MASK   (0x3F << IPROC_ADC_CHANNEL_ROUNDS)
0058 #define IPROC_ADC_CHANNEL_MODE      0x1
0059 #define IPROC_ADC_CHANNEL_MODE_MASK (0x1 << IPROC_ADC_CHANNEL_MODE)
0060 #define IPROC_ADC_CHANNEL_MODE_TDM  0x1
0061 #define IPROC_ADC_CHANNEL_MODE_SNAPSHOT 0x0
0062 #define IPROC_ADC_CHANNEL_ENABLE    0x0
0063 #define IPROC_ADC_CHANNEL_ENABLE_MASK   0x1
0064
0065 /* Bit definitions for IPROC_ADC_CHANNEL_REGCTL2 */
0066 #define IPROC_ADC_CHANNEL_WATERMARK 0x0
0067 #define IPROC_ADC_CHANNEL_WATERMARK_MASK \
0068         (0x3F << IPROC_ADC_CHANNEL_WATERMARK)
0069
0070 #define IPROC_ADC_WATER_MARK_LEVEL  0x1
0071
0072 /* Bit definitions for IPROC_ADC_CHANNEL_STATUS */
0073 #define IPROC_ADC_CHANNEL_DATA_LOST     0x0
0074 #define IPROC_ADC_CHANNEL_DATA_LOST_MASK    \
0075         (0x0 << IPROC_ADC_CHANNEL_DATA_LOST)
0076 #define IPROC_ADC_CHANNEL_VALID_ENTERIES    0x1
0077 #define IPROC_ADC_CHANNEL_VALID_ENTERIES_MASK   \
0078         (0xFF << IPROC_ADC_CHANNEL_VALID_ENTERIES)
0079 #define IPROC_ADC_CHANNEL_TOTAL_ENTERIES    0x9
0080 #define IPROC_ADC_CHANNEL_TOTAL_ENTERIES_MASK   \
0081         (0xFF << IPROC_ADC_CHANNEL_TOTAL_ENTERIES)
0082
0083 /* Bit definitions for IPROC_ADC_CHANNEL_INTERRUPT_MASK */
0084 #define IPROC_ADC_CHANNEL_WTRMRK_INTR           0x0
0085 #define IPROC_ADC_CHANNEL_WTRMRK_INTR_MASK      \
0086         (0x1 << IPROC_ADC_CHANNEL_WTRMRK_INTR)
0087 #define IPROC_ADC_CHANNEL_FULL_INTR         0x1
0088 #define IPROC_ADC_CHANNEL_FULL_INTR_MASK        \
0089         (0x1 << IPROC_ADC_IPROC_ADC_CHANNEL_FULL_INTR)
0090 #define IPROC_ADC_CHANNEL_EMPTY_INTR            0x2
0091 #define IPROC_ADC_CHANNEL_EMPTY_INTR_MASK       \
0092         (0x1 << IPROC_ADC_CHANNEL_EMPTY_INTR)
0093
0094 #define IPROC_ADC_WATER_MARK_INTR_ENABLE        0x1
0095
0096 /* Number of time to retry a set of the interrupt mask reg */
0097 #define IPROC_ADC_INTMASK_RETRY_ATTEMPTS        10
0098
0099 #define IPROC_ADC_READ_TIMEOUT        (HZ*2)
0100
0101 #define iproc_adc_dbg_reg(dev, priv, reg) \
0102 do { \
0103     u32 val; \
0104     regmap_read(priv->regmap, reg, &val); \
0105     dev_dbg(dev, "%20s= 0x%08x\n", #reg, val); \
0106 } while (0)
0107
0108 struct iproc_adc_priv {
0109     struct regmap *regmap;
0110     struct clk *adc_clk;
0111     struct mutex mutex;
0112     int  irqno;
0113     int chan_val;
0114     int chan_id;
0115     struct completion completion;
0116 };
0117
0118 static void iproc_adc_reg_dump(struct iio_dev *indio_dev)
0119 {
0120     struct device *dev = &indio_dev->dev;
0121     struct iproc_adc_priv *adc_priv = iio_priv(indio_dev);
0122
0123     iproc_adc_dbg_reg(dev, adc_priv, IPROC_REGCTL1);
0124     iproc_adc_dbg_reg(dev, adc_priv, IPROC_REGCTL2);
0125     iproc_adc_dbg_reg(dev, adc_priv, IPROC_INTERRUPT_THRES);
0126     iproc_adc_dbg_reg(dev, adc_priv, IPROC_INTERRUPT_MASK);
0127     iproc_adc_dbg_reg(dev, adc_priv, IPROC_INTERRUPT_STATUS);
0128     iproc_adc_dbg_reg(dev, adc_priv, IPROC_CONTROLLER_STATUS);
0129     iproc_adc_dbg_reg(dev, adc_priv, IPROC_ANALOG_CONTROL);
0130     iproc_adc_dbg_reg(dev, adc_priv, IPROC_AUX_DATA);
0131     iproc_adc_dbg_reg(dev, adc_priv, IPROC_SOFT_BYPASS_CONTROL);
0132     iproc_adc_dbg_reg(dev, adc_priv, IPROC_SOFT_BYPASS_DATA);
0133 }
0134
0135 static irqreturn_t iproc_adc_interrupt_thread(int irq, void *data)
0136 {
0137     u32 channel_intr_status;
0138     u32 intr_status;
0139     u32 intr_mask;
0140     struct iio_dev *indio_dev = data;
0141     struct iproc_adc_priv *adc_priv = iio_priv(indio_dev);
0142
0143     /*
0144      * This interrupt is shared with the touchscreen driver.
0145      * Make sure this interrupt is intended for us.
0146      * Handle only ADC channel specific interrupts.
0147      */
0148     regmap_read(adc_priv->regmap, IPROC_INTERRUPT_STATUS, &intr_status);
0149     regmap_read(adc_priv->regmap, IPROC_INTERRUPT_MASK, &intr_mask);
0150     intr_status = intr_status & intr_mask;
0151     channel_intr_status = (intr_status & IPROC_ADC_INTR_MASK) >>
0152                 IPROC_ADC_INTR;
0153     if (channel_intr_status)
0154         return IRQ_WAKE_THREAD;
0155
0156     return IRQ_NONE;
0157 }
0158
0159 static irqreturn_t iproc_adc_interrupt_handler(int irq, void *data)
0160 {
0161     irqreturn_t retval = IRQ_NONE;
0162     struct iproc_adc_priv *adc_priv;
0163     struct iio_dev *indio_dev = data;
0164     unsigned int valid_entries;
0165     u32 intr_status;
0166     u32 intr_channels;
0167     u32 channel_status;
0168     u32 ch_intr_status;
0169
0170     adc_priv = iio_priv(indio_dev);
0171
0172     regmap_read(adc_priv->regmap, IPROC_INTERRUPT_STATUS, &intr_status);
0173     dev_dbg(&indio_dev->dev, "iproc_adc_interrupt_handler(),INTRPT_STS:%x\n",
0174             intr_status);
0175
0176     intr_channels = (intr_status & IPROC_ADC_INTR_MASK) >> IPROC_ADC_INTR;
0177     if (intr_channels) {
0178         regmap_read(adc_priv->regmap,
0179                 IPROC_ADC_CHANNEL_INTERRUPT_STATUS +
0180                 IPROC_ADC_CHANNEL_OFFSET * adc_priv->chan_id,
0181                 &ch_intr_status);
0182
0183         if (ch_intr_status & IPROC_ADC_CHANNEL_WTRMRK_INTR_MASK) {
0184             regmap_read(adc_priv->regmap,
0185                     IPROC_ADC_CHANNEL_STATUS +
0186                     IPROC_ADC_CHANNEL_OFFSET *
0187                     adc_priv->chan_id,
0188                     &channel_status);
0189
0190             valid_entries = ((channel_status &
0191                 IPROC_ADC_CHANNEL_VALID_ENTERIES_MASK) >>
0192                 IPROC_ADC_CHANNEL_VALID_ENTERIES);
0193             if (valid_entries >= 1) {
0194                 regmap_read(adc_priv->regmap,
0195                     IPROC_ADC_CHANNEL_DATA +
0196                     IPROC_ADC_CHANNEL_OFFSET *
0197                     adc_priv->chan_id,
0198                     &adc_priv->chan_val);
0199                 complete(&adc_priv->completion);
0200             } else {
0201                 dev_err(&indio_dev->dev,
0202                     "No data rcvd on channel %d\n",
0203                     adc_priv->chan_id);
0204             }
0205             regmap_write(adc_priv->regmap,
0206                     IPROC_ADC_CHANNEL_INTERRUPT_MASK +
0207                     IPROC_ADC_CHANNEL_OFFSET *
0208                     adc_priv->chan_id,
0209                     (ch_intr_status &
0210                     ~(IPROC_ADC_CHANNEL_WTRMRK_INTR_MASK)));
0211         }
0212         regmap_write(adc_priv->regmap,
0213                 IPROC_ADC_CHANNEL_INTERRUPT_STATUS +
0214                 IPROC_ADC_CHANNEL_OFFSET * adc_priv->chan_id,
0215                 ch_intr_status);
0216         regmap_write(adc_priv->regmap, IPROC_INTERRUPT_STATUS,
0217                 intr_channels);
0218         retval = IRQ_HANDLED;
0219     }
0220
0221     return retval;
0222 }
0223
0224 static int iproc_adc_do_read(struct iio_dev *indio_dev,
0225                int channel,
0226                u16 *p_adc_data)
0227 {
0228     int read_len = 0;
0229     u32 val;
0230     u32 mask;
0231     u32 val_check;
0232     int failed_cnt = 0;
0233     struct iproc_adc_priv *adc_priv = iio_priv(indio_dev);
0234
0235     mutex_lock(&adc_priv->mutex);
0236
0237     /*
0238      * After a read is complete the ADC interrupts will be disabled so
0239      * we can assume this section of code is safe from interrupts.
0240      */
0241     adc_priv->chan_val = -1;
0242     adc_priv->chan_id = channel;
0243
0244     reinit_completion(&adc_priv->completion);
0245     /* Clear any pending interrupt */
0246     regmap_update_bits(adc_priv->regmap, IPROC_INTERRUPT_STATUS,
0247             IPROC_ADC_INTR_MASK | IPROC_ADC_AUXDATA_RDY_INTR,
0248             ((0x0 << channel) << IPROC_ADC_INTR) |
0249             IPROC_ADC_AUXDATA_RDY_INTR);
0250
0251     /* Configure channel for snapshot mode and enable  */
0252     val = (BIT(IPROC_ADC_CHANNEL_ROUNDS) |
0253         (IPROC_ADC_CHANNEL_MODE_SNAPSHOT << IPROC_ADC_CHANNEL_MODE) |
0254         (0x1 << IPROC_ADC_CHANNEL_ENABLE));
0255
0256     mask = IPROC_ADC_CHANNEL_ROUNDS_MASK | IPROC_ADC_CHANNEL_MODE_MASK |
0257         IPROC_ADC_CHANNEL_ENABLE_MASK;
0258     regmap_update_bits(adc_priv->regmap, (IPROC_ADC_CHANNEL_REGCTL1 +
0259                 IPROC_ADC_CHANNEL_OFFSET * channel),
0260                 mask, val);
0261
0262     /* Set the Watermark for a channel */
0263     regmap_update_bits(adc_priv->regmap, (IPROC_ADC_CHANNEL_REGCTL2 +
0264                     IPROC_ADC_CHANNEL_OFFSET * channel),
0265                     IPROC_ADC_CHANNEL_WATERMARK_MASK,
0266                     0x1);
0267
0268     /* Enable water mark interrupt */
0269     regmap_update_bits(adc_priv->regmap, (IPROC_ADC_CHANNEL_INTERRUPT_MASK +
0270                     IPROC_ADC_CHANNEL_OFFSET *
0271                     channel),
0272                     IPROC_ADC_CHANNEL_WTRMRK_INTR_MASK,
0273                     IPROC_ADC_WATER_MARK_INTR_ENABLE);
0274     regmap_read(adc_priv->regmap, IPROC_INTERRUPT_MASK, &val);
0275
0276     /* Enable ADC interrupt for a channel */
0277     val |= (BIT(channel) << IPROC_ADC_INTR);
0278     regmap_write(adc_priv->regmap, IPROC_INTERRUPT_MASK, val);
0279
0280     /*
0281      * There seems to be a very rare issue where writing to this register
0282      * does not take effect.  To work around the issue we will try multiple
0283      * writes.  In total we will spend about 10*10 = 100 us attempting this.
0284      * Testing has shown that this may loop a few time, but we have never
0285      * hit the full count.
0286      */
0287     regmap_read(adc_priv->regmap, IPROC_INTERRUPT_MASK, &val_check);
0288     while (val_check != val) {
0289         failed_cnt++;
0290
0291         if (failed_cnt > IPROC_ADC_INTMASK_RETRY_ATTEMPTS)
0292             break;
0293
0294         udelay(10);
0295         regmap_update_bits(adc_priv->regmap, IPROC_INTERRUPT_MASK,
0296                 IPROC_ADC_INTR_MASK,
0297                 ((0x1 << channel) <<
0298                 IPROC_ADC_INTR));
0299
0300         regmap_read(adc_priv->regmap, IPROC_INTERRUPT_MASK, &val_check);
0301     }
0302
0303     if (failed_cnt) {
0304         dev_dbg(&indio_dev->dev,
0305             "IntMask failed (%d times)", failed_cnt);
0306         if (failed_cnt > IPROC_ADC_INTMASK_RETRY_ATTEMPTS) {
0307             dev_err(&indio_dev->dev,
0308                 "IntMask set failed. Read will likely fail.");
0309             read_len = -EIO;
0310             goto adc_err;
0311         }
0312     }
0313     regmap_read(adc_priv->regmap, IPROC_INTERRUPT_MASK, &val_check);
0314
0315     if (wait_for_completion_timeout(&adc_priv->completion,
0316         IPROC_ADC_READ_TIMEOUT) > 0) {
0317
0318         /* Only the lower 16 bits are relevant */
0319         *p_adc_data = adc_priv->chan_val & 0xFFFF;
0320         read_len = sizeof(*p_adc_data);
0321
0322     } else {
0323         /*
0324          * We never got the interrupt, something went wrong.
0325          * Perhaps the interrupt may still be coming, we do not want
0326          * that now.  Lets disable the ADC interrupt, and clear the
0327          * status to put it back in to normal state.
0328          */
0329         read_len = -ETIMEDOUT;
0330         goto adc_err;
0331     }
0332     mutex_unlock(&adc_priv->mutex);
0333
0334     return read_len;
0335
0336 adc_err:
0337     regmap_update_bits(adc_priv->regmap, IPROC_INTERRUPT_MASK,
0338                IPROC_ADC_INTR_MASK,
0339                ((0x0 << channel) << IPROC_ADC_INTR));
0340
0341     regmap_update_bits(adc_priv->regmap, IPROC_INTERRUPT_STATUS,
0342                IPROC_ADC_INTR_MASK,
0343                ((0x0 << channel) << IPROC_ADC_INTR));
0344
0345     dev_err(&indio_dev->dev, "Timed out waiting for ADC data!\n");
0346     iproc_adc_reg_dump(indio_dev);
0347     mutex_unlock(&adc_priv->mutex);
0348
0349     return read_len;
0350 }
0351
0352 static int iproc_adc_enable(struct iio_dev *indio_dev)
0353 {
0354     u32 val;
0355     u32 channel_id;
0356     struct iproc_adc_priv *adc_priv = iio_priv(indio_dev);
0357     int ret;
0358
0359     /* Set i_amux = 3b'000, select channel 0 */
0360     ret = regmap_update_bits(adc_priv->regmap, IPROC_ANALOG_CONTROL,
0361                 IPROC_ADC_CHANNEL_SEL_MASK, 0);
0362     if (ret) {
0363         dev_err(&indio_dev->dev,
0364             "failed to write IPROC_ANALOG_CONTROL %d\n", ret);
0365         return ret;
0366     }
0367     adc_priv->chan_val = -1;
0368
0369     /*
0370      * PWR up LDO, ADC, and Band Gap (0 to enable)
0371      * Also enable ADC controller (set high)
0372      */
0373     ret = regmap_read(adc_priv->regmap, IPROC_REGCTL2, &val);
0374     if (ret) {
0375         dev_err(&indio_dev->dev,
0376             "failed to read IPROC_REGCTL2 %d\n", ret);
0377         return ret;
0378     }
0379
0380     val &= ~(IPROC_ADC_PWR_LDO | IPROC_ADC_PWR_ADC | IPROC_ADC_PWR_BG);
0381
0382     ret = regmap_write(adc_priv->regmap, IPROC_REGCTL2, val);
0383     if (ret) {
0384         dev_err(&indio_dev->dev,
0385             "failed to write IPROC_REGCTL2 %d\n", ret);
0386         return ret;
0387     }
0388
0389     ret = regmap_read(adc_priv->regmap, IPROC_REGCTL2, &val);
0390     if (ret) {
0391         dev_err(&indio_dev->dev,
0392             "failed to read IPROC_REGCTL2 %d\n", ret);
0393         return ret;
0394     }
0395
0396     val |= IPROC_ADC_CONTROLLER_EN;
0397     ret = regmap_write(adc_priv->regmap, IPROC_REGCTL2, val);
0398     if (ret) {
0399         dev_err(&indio_dev->dev,
0400             "failed to write IPROC_REGCTL2 %d\n", ret);
0401         return ret;
0402     }
0403
0404     for (channel_id = 0; channel_id < indio_dev->num_channels;
0405         channel_id++) {
0406         ret = regmap_write(adc_priv->regmap,
0407                 IPROC_ADC_CHANNEL_INTERRUPT_MASK +
0408                 IPROC_ADC_CHANNEL_OFFSET * channel_id, 0);
0409         if (ret) {
0410             dev_err(&indio_dev->dev,
0411                 "failed to write ADC_CHANNEL_INTERRUPT_MASK %d\n",
0412                 ret);
0413             return ret;
0414         }
0415
0416         ret = regmap_write(adc_priv->regmap,
0417                 IPROC_ADC_CHANNEL_INTERRUPT_STATUS +
0418                 IPROC_ADC_CHANNEL_OFFSET * channel_id, 0);
0419         if (ret) {
0420             dev_err(&indio_dev->dev,
0421                 "failed to write ADC_CHANNEL_INTERRUPT_STATUS %d\n",
0422                 ret);
0423             return ret;
0424         }
0425     }
0426
0427     return 0;
0428 }
0429
0430 static void iproc_adc_disable(struct iio_dev *indio_dev)
0431 {
0432     u32 val;
0433     int ret;
0434     struct iproc_adc_priv *adc_priv = iio_priv(indio_dev);
0435
0436     ret = regmap_read(adc_priv->regmap, IPROC_REGCTL2, &val);
0437     if (ret) {
0438         dev_err(&indio_dev->dev,
0439             "failed to read IPROC_REGCTL2 %d\n", ret);
0440         return;
0441     }
0442
0443     val &= ~IPROC_ADC_CONTROLLER_EN;
0444     ret = regmap_write(adc_priv->regmap, IPROC_REGCTL2, val);
0445     if (ret) {
0446         dev_err(&indio_dev->dev,
0447             "failed to write IPROC_REGCTL2 %d\n", ret);
0448         return;
0449     }
0450 }
0451
0452 static int iproc_adc_read_raw(struct iio_dev *indio_dev,
0453               struct iio_chan_spec const *chan,
0454               int *val,
0455               int *val2,
0456               long mask)
0457 {
0458     u16 adc_data;
0459     int err;
0460
0461     switch (mask) {
0462     case IIO_CHAN_INFO_RAW:
0463         err =  iproc_adc_do_read(indio_dev, chan->channel, &adc_data);
0464         if (err < 0)
0465             return err;
0466         *val = adc_data;
0467         return IIO_VAL_INT;
0468     case IIO_CHAN_INFO_SCALE:
0469         switch (chan->type) {
0470         case IIO_VOLTAGE:
0471             *val = 1800;
0472             *val2 = 10;
0473             return IIO_VAL_FRACTIONAL_LOG2;
0474         default:
0475             return -EINVAL;
0476         }
0477     default:
0478         return -EINVAL;
0479     }
0480 }
0481
0482 static const struct iio_info iproc_adc_iio_info = {
0483     .read_raw = &iproc_adc_read_raw,
0484 };
0485
0486 #define IPROC_ADC_CHANNEL(_index, _id) {                \
0487     .type = IIO_VOLTAGE,                            \
0488     .indexed = 1,                                   \
0489     .channel = _index,                              \
0490     .info_mask_separate = BIT(IIO_CHAN_INFO_RAW),   \
0491     .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
0492     .datasheet_name = _id,                          \
0493 }
0494
0495 static const struct iio_chan_spec iproc_adc_iio_channels[] = {
0496     IPROC_ADC_CHANNEL(0, "adc0"),
0497     IPROC_ADC_CHANNEL(1, "adc1"),
0498     IPROC_ADC_CHANNEL(2, "adc2"),
0499     IPROC_ADC_CHANNEL(3, "adc3"),
0500     IPROC_ADC_CHANNEL(4, "adc4"),
0501     IPROC_ADC_CHANNEL(5, "adc5"),
0502     IPROC_ADC_CHANNEL(6, "adc6"),
0503     IPROC_ADC_CHANNEL(7, "adc7"),
0504 };
0505
0506 static int iproc_adc_probe(struct platform_device *pdev)
0507 {
0508     struct iproc_adc_priv *adc_priv;
0509     struct iio_dev *indio_dev = NULL;
0510     int ret;
0511
0512     indio_dev = devm_iio_device_alloc(&pdev->dev,
0513                     sizeof(*adc_priv));
0514     if (!indio_dev) {
0515         dev_err(&pdev->dev, "failed to allocate iio device\n");
0516         return -ENOMEM;
0517     }
0518
0519     adc_priv = iio_priv(indio_dev);
0520     platform_set_drvdata(pdev, indio_dev);
0521
0522     mutex_init(&adc_priv->mutex);
0523
0524     init_completion(&adc_priv->completion);
0525
0526     adc_priv->regmap = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
0527                "adc-syscon");
0528     if (IS_ERR(adc_priv->regmap)) {
0529         dev_err(&pdev->dev, "failed to get handle for tsc syscon\n");
0530         ret = PTR_ERR(adc_priv->regmap);
0531         return ret;
0532     }
0533
0534     adc_priv->adc_clk = devm_clk_get(&pdev->dev, "tsc_clk");
0535     if (IS_ERR(adc_priv->adc_clk)) {
0536         dev_err(&pdev->dev,
0537             "failed getting clock tsc_clk\n");
0538         ret = PTR_ERR(adc_priv->adc_clk);
0539         return ret;
0540     }
0541
0542     adc_priv->irqno = platform_get_irq(pdev, 0);
0543     if (adc_priv->irqno <= 0)
0544         return -ENODEV;
0545
0546     ret = regmap_update_bits(adc_priv->regmap, IPROC_REGCTL2,
0547                 IPROC_ADC_AUXIN_SCAN_ENA, 0);
0548     if (ret) {
0549         dev_err(&pdev->dev, "failed to write IPROC_REGCTL2 %d\n", ret);
0550         return ret;
0551     }
0552
0553     ret = devm_request_threaded_irq(&pdev->dev, adc_priv->irqno,
0554                 iproc_adc_interrupt_handler,
0555                 iproc_adc_interrupt_thread,
0556                 IRQF_SHARED, "iproc-adc", indio_dev);
0557     if (ret) {
0558         dev_err(&pdev->dev, "request_irq error %d\n", ret);
0559         return ret;
0560     }
0561
0562     ret = clk_prepare_enable(adc_priv->adc_clk);
0563     if (ret) {
0564         dev_err(&pdev->dev,
0565             "clk_prepare_enable failed %d\n", ret);
0566         return ret;
0567     }
0568
0569     ret = iproc_adc_enable(indio_dev);
0570     if (ret) {
0571         dev_err(&pdev->dev, "failed to enable adc %d\n", ret);
0572         goto err_adc_enable;
0573     }
0574
0575     indio_dev->name = "iproc-static-adc";
0576     indio_dev->info = &iproc_adc_iio_info;
0577     indio_dev->modes = INDIO_DIRECT_MODE;
0578     indio_dev->channels = iproc_adc_iio_channels;
0579     indio_dev->num_channels = ARRAY_SIZE(iproc_adc_iio_channels);
0580
0581     ret = iio_device_register(indio_dev);
0582     if (ret) {
0583         dev_err(&pdev->dev, "iio_device_register failed:err %d\n", ret);
0584         goto err_clk;
0585     }
0586
0587     return 0;
0588
0589 err_clk:
0590     iproc_adc_disable(indio_dev);
0591 err_adc_enable:
0592     clk_disable_unprepare(adc_priv->adc_clk);
0593
0594     return ret;
0595 }
0596
0597 static int iproc_adc_remove(struct platform_device *pdev)
0598 {
0599     struct iio_dev *indio_dev = platform_get_drvdata(pdev);
0600     struct iproc_adc_priv *adc_priv = iio_priv(indio_dev);
0601
0602     iio_device_unregister(indio_dev);
0603     iproc_adc_disable(indio_dev);
0604     clk_disable_unprepare(adc_priv->adc_clk);
0605
0606     return 0;
0607 }
0608
0609 static const struct of_device_id iproc_adc_of_match[] = {
0610     {.compatible = "brcm,iproc-static-adc", },
0611     { },
0612 };
0613 MODULE_DEVICE_TABLE(of, iproc_adc_of_match);
0614
0615 static struct platform_driver iproc_adc_driver = {
0616     .probe  = iproc_adc_probe,
0617     .remove = iproc_adc_remove,
0618     .driver = {
0619         .name   = "iproc-static-adc",
0620         .of_match_table = iproc_adc_of_match,
0621     },
0622 };
0623 module_platform_driver(iproc_adc_driver);
0624
0625 MODULE_DESCRIPTION("Broadcom iProc ADC controller driver");
0626 MODULE_AUTHOR("Raveendra Padasalagi <raveendra.padasalagi@broadcom.com>");
0627 MODULE_LICENSE("GPL v2");