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0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Driver for the ADC present in the Atmel AT91 evaluation boards.
0004  *
0005  * Copyright 2011 Free Electrons
0006  */
0007 
0008 #include <linux/bitmap.h>
0009 #include <linux/bitops.h>
0010 #include <linux/clk.h>
0011 #include <linux/err.h>
0012 #include <linux/io.h>
0013 #include <linux/input.h>
0014 #include <linux/interrupt.h>
0015 #include <linux/jiffies.h>
0016 #include <linux/kernel.h>
0017 #include <linux/module.h>
0018 #include <linux/of.h>
0019 #include <linux/of_device.h>
0020 #include <linux/platform_device.h>
0021 #include <linux/sched.h>
0022 #include <linux/slab.h>
0023 #include <linux/wait.h>
0024 
0025 #include <linux/iio/iio.h>
0026 #include <linux/iio/buffer.h>
0027 #include <linux/iio/trigger.h>
0028 #include <linux/iio/trigger_consumer.h>
0029 #include <linux/iio/triggered_buffer.h>
0030 #include <linux/pinctrl/consumer.h>
0031 
0032 /* Registers */
0033 #define AT91_ADC_CR     0x00        /* Control Register */
0034 #define     AT91_ADC_SWRST      (1 << 0)    /* Software Reset */
0035 #define     AT91_ADC_START      (1 << 1)    /* Start Conversion */
0036 
0037 #define AT91_ADC_MR     0x04        /* Mode Register */
0038 #define     AT91_ADC_TSAMOD     (3 << 0)    /* ADC mode */
0039 #define     AT91_ADC_TSAMOD_ADC_ONLY_MODE       (0 << 0)    /* ADC Mode */
0040 #define     AT91_ADC_TSAMOD_TS_ONLY_MODE        (1 << 0)    /* Touch Screen Only Mode */
0041 #define     AT91_ADC_TRGEN      (1 << 0)    /* Trigger Enable */
0042 #define     AT91_ADC_TRGSEL     (7 << 1)    /* Trigger Selection */
0043 #define         AT91_ADC_TRGSEL_TC0     (0 << 1)
0044 #define         AT91_ADC_TRGSEL_TC1     (1 << 1)
0045 #define         AT91_ADC_TRGSEL_TC2     (2 << 1)
0046 #define         AT91_ADC_TRGSEL_EXTERNAL    (6 << 1)
0047 #define     AT91_ADC_LOWRES     (1 << 4)    /* Low Resolution */
0048 #define     AT91_ADC_SLEEP      (1 << 5)    /* Sleep Mode */
0049 #define     AT91_ADC_PENDET     (1 << 6)    /* Pen contact detection enable */
0050 #define     AT91_ADC_PRESCAL_9260   (0x3f << 8) /* Prescalar Rate Selection */
0051 #define     AT91_ADC_PRESCAL_9G45   (0xff << 8)
0052 #define         AT91_ADC_PRESCAL_(x)    ((x) << 8)
0053 #define     AT91_ADC_STARTUP_9260   (0x1f << 16)    /* Startup Up Time */
0054 #define     AT91_ADC_STARTUP_9G45   (0x7f << 16)
0055 #define     AT91_ADC_STARTUP_9X5    (0xf << 16)
0056 #define         AT91_ADC_STARTUP_(x)    ((x) << 16)
0057 #define     AT91_ADC_SHTIM      (0xf  << 24)    /* Sample & Hold Time */
0058 #define         AT91_ADC_SHTIM_(x)  ((x) << 24)
0059 #define     AT91_ADC_PENDBC     (0x0f << 28)    /* Pen Debounce time */
0060 #define         AT91_ADC_PENDBC_(x) ((x) << 28)
0061 
0062 #define AT91_ADC_TSR        0x0C
0063 #define     AT91_ADC_TSR_SHTIM  (0xf  << 24)    /* Sample & Hold Time */
0064 #define         AT91_ADC_TSR_SHTIM_(x)  ((x) << 24)
0065 
0066 #define AT91_ADC_CHER       0x10        /* Channel Enable Register */
0067 #define AT91_ADC_CHDR       0x14        /* Channel Disable Register */
0068 #define AT91_ADC_CHSR       0x18        /* Channel Status Register */
0069 #define     AT91_ADC_CH(n)      (1 << (n))  /* Channel Number */
0070 
0071 #define AT91_ADC_SR     0x1C        /* Status Register */
0072 #define     AT91_ADC_EOC(n)     (1 << (n))  /* End of Conversion on Channel N */
0073 #define     AT91_ADC_OVRE(n)    (1 << ((n) + 8))/* Overrun Error on Channel N */
0074 #define     AT91_ADC_DRDY       (1 << 16)   /* Data Ready */
0075 #define     AT91_ADC_GOVRE      (1 << 17)   /* General Overrun Error */
0076 #define     AT91_ADC_ENDRX      (1 << 18)   /* End of RX Buffer */
0077 #define     AT91_ADC_RXFUFF     (1 << 19)   /* RX Buffer Full */
0078 
0079 #define AT91_ADC_SR_9X5     0x30        /* Status Register for 9x5 */
0080 #define     AT91_ADC_SR_DRDY_9X5    (1 << 24)   /* Data Ready */
0081 
0082 #define AT91_ADC_LCDR       0x20        /* Last Converted Data Register */
0083 #define     AT91_ADC_LDATA      (0x3ff)
0084 
0085 #define AT91_ADC_IER        0x24        /* Interrupt Enable Register */
0086 #define AT91_ADC_IDR        0x28        /* Interrupt Disable Register */
0087 #define AT91_ADC_IMR        0x2C        /* Interrupt Mask Register */
0088 #define     AT91RL_ADC_IER_PEN  (1 << 20)
0089 #define     AT91RL_ADC_IER_NOPEN    (1 << 21)
0090 #define     AT91_ADC_IER_PEN    (1 << 29)
0091 #define     AT91_ADC_IER_NOPEN  (1 << 30)
0092 #define     AT91_ADC_IER_XRDY   (1 << 20)
0093 #define     AT91_ADC_IER_YRDY   (1 << 21)
0094 #define     AT91_ADC_IER_PRDY   (1 << 22)
0095 #define     AT91_ADC_ISR_PENS   (1 << 31)
0096 
0097 #define AT91_ADC_CHR(n)     (0x30 + ((n) * 4))  /* Channel Data Register N */
0098 #define     AT91_ADC_DATA       (0x3ff)
0099 
0100 #define AT91_ADC_CDR0_9X5   (0x50)          /* Channel Data Register 0 for 9X5 */
0101 
0102 #define AT91_ADC_ACR        0x94    /* Analog Control Register */
0103 #define     AT91_ADC_ACR_PENDETSENS (0x3 << 0)  /* pull-up resistor */
0104 
0105 #define AT91_ADC_TSMR       0xB0
0106 #define     AT91_ADC_TSMR_TSMODE    (3 << 0)    /* Touch Screen Mode */
0107 #define         AT91_ADC_TSMR_TSMODE_NONE       (0 << 0)
0108 #define         AT91_ADC_TSMR_TSMODE_4WIRE_NO_PRESS (1 << 0)
0109 #define         AT91_ADC_TSMR_TSMODE_4WIRE_PRESS    (2 << 0)
0110 #define         AT91_ADC_TSMR_TSMODE_5WIRE      (3 << 0)
0111 #define     AT91_ADC_TSMR_TSAV  (3 << 4)    /* Averages samples */
0112 #define         AT91_ADC_TSMR_TSAV_(x)      ((x) << 4)
0113 #define     AT91_ADC_TSMR_SCTIM (0x0f << 16)    /* Switch closure time */
0114 #define         AT91_ADC_TSMR_SCTIM_(x)     ((x) << 16)
0115 #define     AT91_ADC_TSMR_PENDBC    (0x0f << 28)    /* Pen Debounce time */
0116 #define         AT91_ADC_TSMR_PENDBC_(x)    ((x) << 28)
0117 #define     AT91_ADC_TSMR_NOTSDMA   (1 << 22)   /* No Touchscreen DMA */
0118 #define     AT91_ADC_TSMR_PENDET_DIS    (0 << 24)   /* Pen contact detection disable */
0119 #define     AT91_ADC_TSMR_PENDET_ENA    (1 << 24)   /* Pen contact detection enable */
0120 
0121 #define AT91_ADC_TSXPOSR    0xB4
0122 #define AT91_ADC_TSYPOSR    0xB8
0123 #define AT91_ADC_TSPRESSR   0xBC
0124 
0125 #define AT91_ADC_TRGR_9260  AT91_ADC_MR
0126 #define AT91_ADC_TRGR_9G45  0x08
0127 #define AT91_ADC_TRGR_9X5   0xC0
0128 
0129 /* Trigger Register bit field */
0130 #define     AT91_ADC_TRGR_TRGPER    (0xffff << 16)
0131 #define         AT91_ADC_TRGR_TRGPER_(x)    ((x) << 16)
0132 #define     AT91_ADC_TRGR_TRGMOD    (0x7 << 0)
0133 #define         AT91_ADC_TRGR_NONE      (0 << 0)
0134 #define         AT91_ADC_TRGR_MOD_PERIOD_TRIG   (5 << 0)
0135 
0136 #define AT91_ADC_CHAN(st, ch) \
0137     (st->registers->channel_base + (ch * 4))
0138 #define at91_adc_readl(st, reg) \
0139     (readl_relaxed(st->reg_base + reg))
0140 #define at91_adc_writel(st, reg, val) \
0141     (writel_relaxed(val, st->reg_base + reg))
0142 
0143 #define DRIVER_NAME     "at91_adc"
0144 #define MAX_POS_BITS        12
0145 
0146 #define TOUCH_SAMPLE_PERIOD_US      2000    /* 2ms */
0147 #define TOUCH_PEN_DETECT_DEBOUNCE_US    200
0148 
0149 #define MAX_RLPOS_BITS         10
0150 #define TOUCH_SAMPLE_PERIOD_US_RL      10000   /* 10ms, the SoC can't keep up with 2ms */
0151 #define TOUCH_SHTIM                    0xa
0152 #define TOUCH_SCTIM_US      10      /* 10us for the Touchscreen Switches Closure Time */
0153 
0154 enum atmel_adc_ts_type {
0155     ATMEL_ADC_TOUCHSCREEN_NONE = 0,
0156     ATMEL_ADC_TOUCHSCREEN_4WIRE = 4,
0157     ATMEL_ADC_TOUCHSCREEN_5WIRE = 5,
0158 };
0159 
0160 /**
0161  * struct at91_adc_trigger - description of triggers
0162  * @name:       name of the trigger advertised to the user
0163  * @value:      value to set in the ADC's trigger setup register
0164  *          to enable the trigger
0165  * @is_external:    Does the trigger rely on an external pin?
0166  */
0167 struct at91_adc_trigger {
0168     const char  *name;
0169     u8      value;
0170     bool        is_external;
0171 };
0172 
0173 /**
0174  * struct at91_adc_reg_desc - Various informations relative to registers
0175  * @channel_base:   Base offset for the channel data registers
0176  * @drdy_mask:      Mask of the DRDY field in the relevant registers
0177  *          (Interruptions registers mostly)
0178  * @status_register:    Offset of the Interrupt Status Register
0179  * @trigger_register:   Offset of the Trigger setup register
0180  * @mr_prescal_mask:    Mask of the PRESCAL field in the adc MR register
0181  * @mr_startup_mask:    Mask of the STARTUP field in the adc MR register
0182  */
0183 struct at91_adc_reg_desc {
0184     u8  channel_base;
0185     u32 drdy_mask;
0186     u8  status_register;
0187     u8  trigger_register;
0188     u32 mr_prescal_mask;
0189     u32 mr_startup_mask;
0190 };
0191 
0192 struct at91_adc_caps {
0193     bool    has_ts;     /* Support touch screen */
0194     bool    has_tsmr;   /* only at91sam9x5, sama5d3 have TSMR reg */
0195     /*
0196      * Numbers of sampling data will be averaged. Can be 0~3.
0197      * Hardware can average (2 ^ ts_filter_average) sample data.
0198      */
0199     u8  ts_filter_average;
0200     /* Pen Detection input pull-up resistor, can be 0~3 */
0201     u8  ts_pen_detect_sensitivity;
0202 
0203     /* startup time calculate function */
0204     u32 (*calc_startup_ticks)(u32 startup_time, u32 adc_clk_khz);
0205 
0206     u8  num_channels;
0207 
0208     u8  low_res_bits;
0209     u8  high_res_bits;
0210     u32 trigger_number;
0211     const struct at91_adc_trigger *triggers;
0212     struct at91_adc_reg_desc registers;
0213 };
0214 
0215 struct at91_adc_state {
0216     struct clk      *adc_clk;
0217     u16         *buffer;
0218     unsigned long       channels_mask;
0219     struct clk      *clk;
0220     bool            done;
0221     int         irq;
0222     u16         last_value;
0223     int         chnb;
0224     struct mutex        lock;
0225     u8          num_channels;
0226     void __iomem        *reg_base;
0227     const struct at91_adc_reg_desc *registers;
0228     u32         startup_time;
0229     u8          sample_hold_time;
0230     bool            sleep_mode;
0231     struct iio_trigger  **trig;
0232     bool            use_external;
0233     u32         vref_mv;
0234     u32         res;        /* resolution used for convertions */
0235     wait_queue_head_t   wq_data_avail;
0236     const struct at91_adc_caps  *caps;
0237 
0238     /*
0239      * Following ADC channels are shared by touchscreen:
0240      *
0241      * CH0 -- Touch screen XP/UL
0242      * CH1 -- Touch screen XM/UR
0243      * CH2 -- Touch screen YP/LL
0244      * CH3 -- Touch screen YM/Sense
0245      * CH4 -- Touch screen LR(5-wire only)
0246      *
0247      * The bitfields below represents the reserved channel in the
0248      * touchscreen mode.
0249      */
0250 #define CHAN_MASK_TOUCHSCREEN_4WIRE (0xf << 0)
0251 #define CHAN_MASK_TOUCHSCREEN_5WIRE (0x1f << 0)
0252     enum atmel_adc_ts_type  touchscreen_type;
0253     struct input_dev    *ts_input;
0254 
0255     u16         ts_sample_period_val;
0256     u32         ts_pressure_threshold;
0257     u16         ts_pendbc;
0258 
0259     bool            ts_bufferedmeasure;
0260     u32         ts_prev_absx;
0261     u32         ts_prev_absy;
0262 };
0263 
0264 static irqreturn_t at91_adc_trigger_handler(int irq, void *p)
0265 {
0266     struct iio_poll_func *pf = p;
0267     struct iio_dev *idev = pf->indio_dev;
0268     struct at91_adc_state *st = iio_priv(idev);
0269     struct iio_chan_spec const *chan;
0270     int i, j = 0;
0271 
0272     for (i = 0; i < idev->masklength; i++) {
0273         if (!test_bit(i, idev->active_scan_mask))
0274             continue;
0275         chan = idev->channels + i;
0276         st->buffer[j] = at91_adc_readl(st, AT91_ADC_CHAN(st, chan->channel));
0277         j++;
0278     }
0279 
0280     iio_push_to_buffers_with_timestamp(idev, st->buffer, pf->timestamp);
0281 
0282     iio_trigger_notify_done(idev->trig);
0283 
0284     /* Needed to ACK the DRDY interruption */
0285     at91_adc_readl(st, AT91_ADC_LCDR);
0286 
0287     enable_irq(st->irq);
0288 
0289     return IRQ_HANDLED;
0290 }
0291 
0292 /* Handler for classic adc channel eoc trigger */
0293 static void handle_adc_eoc_trigger(int irq, struct iio_dev *idev)
0294 {
0295     struct at91_adc_state *st = iio_priv(idev);
0296 
0297     if (iio_buffer_enabled(idev)) {
0298         disable_irq_nosync(irq);
0299         iio_trigger_poll(idev->trig);
0300     } else {
0301         st->last_value = at91_adc_readl(st, AT91_ADC_CHAN(st, st->chnb));
0302         /* Needed to ACK the DRDY interruption */
0303         at91_adc_readl(st, AT91_ADC_LCDR);
0304         st->done = true;
0305         wake_up_interruptible(&st->wq_data_avail);
0306     }
0307 }
0308 
0309 static int at91_ts_sample(struct iio_dev *idev)
0310 {
0311     struct at91_adc_state *st = iio_priv(idev);
0312     unsigned int xscale, yscale, reg, z1, z2;
0313     unsigned int x, y, pres, xpos, ypos;
0314     unsigned int rxp = 1;
0315     unsigned int factor = 1000;
0316 
0317     unsigned int xyz_mask_bits = st->res;
0318     unsigned int xyz_mask = (1 << xyz_mask_bits) - 1;
0319 
0320     /* calculate position */
0321     /* x position = (x / xscale) * max, max = 2^MAX_POS_BITS - 1 */
0322     reg = at91_adc_readl(st, AT91_ADC_TSXPOSR);
0323     xpos = reg & xyz_mask;
0324     x = (xpos << MAX_POS_BITS) - xpos;
0325     xscale = (reg >> 16) & xyz_mask;
0326     if (xscale == 0) {
0327         dev_err(&idev->dev, "Error: xscale == 0!\n");
0328         return -1;
0329     }
0330     x /= xscale;
0331 
0332     /* y position = (y / yscale) * max, max = 2^MAX_POS_BITS - 1 */
0333     reg = at91_adc_readl(st, AT91_ADC_TSYPOSR);
0334     ypos = reg & xyz_mask;
0335     y = (ypos << MAX_POS_BITS) - ypos;
0336     yscale = (reg >> 16) & xyz_mask;
0337     if (yscale == 0) {
0338         dev_err(&idev->dev, "Error: yscale == 0!\n");
0339         return -1;
0340     }
0341     y /= yscale;
0342 
0343     /* calculate the pressure */
0344     reg = at91_adc_readl(st, AT91_ADC_TSPRESSR);
0345     z1 = reg & xyz_mask;
0346     z2 = (reg >> 16) & xyz_mask;
0347 
0348     if (z1 != 0)
0349         pres = rxp * (x * factor / 1024) * (z2 * factor / z1 - factor)
0350             / factor;
0351     else
0352         pres = st->ts_pressure_threshold;   /* no pen contacted */
0353 
0354     dev_dbg(&idev->dev, "xpos = %d, xscale = %d, ypos = %d, yscale = %d, z1 = %d, z2 = %d, press = %d\n",
0355                 xpos, xscale, ypos, yscale, z1, z2, pres);
0356 
0357     if (pres < st->ts_pressure_threshold) {
0358         dev_dbg(&idev->dev, "x = %d, y = %d, pressure = %d\n",
0359                     x, y, pres / factor);
0360         input_report_abs(st->ts_input, ABS_X, x);
0361         input_report_abs(st->ts_input, ABS_Y, y);
0362         input_report_abs(st->ts_input, ABS_PRESSURE, pres);
0363         input_report_key(st->ts_input, BTN_TOUCH, 1);
0364         input_sync(st->ts_input);
0365     } else {
0366         dev_dbg(&idev->dev, "pressure too low: not reporting\n");
0367     }
0368 
0369     return 0;
0370 }
0371 
0372 static irqreturn_t at91_adc_rl_interrupt(int irq, void *private)
0373 {
0374     struct iio_dev *idev = private;
0375     struct at91_adc_state *st = iio_priv(idev);
0376     u32 status = at91_adc_readl(st, st->registers->status_register);
0377     unsigned int reg;
0378 
0379     status &= at91_adc_readl(st, AT91_ADC_IMR);
0380     if (status & GENMASK(st->num_channels - 1, 0))
0381         handle_adc_eoc_trigger(irq, idev);
0382 
0383     if (status & AT91RL_ADC_IER_PEN) {
0384         /* Disabling pen debounce is required to get a NOPEN irq */
0385         reg = at91_adc_readl(st, AT91_ADC_MR);
0386         reg &= ~AT91_ADC_PENDBC;
0387         at91_adc_writel(st, AT91_ADC_MR, reg);
0388 
0389         at91_adc_writel(st, AT91_ADC_IDR, AT91RL_ADC_IER_PEN);
0390         at91_adc_writel(st, AT91_ADC_IER, AT91RL_ADC_IER_NOPEN
0391                 | AT91_ADC_EOC(3));
0392         /* Set up period trigger for sampling */
0393         at91_adc_writel(st, st->registers->trigger_register,
0394             AT91_ADC_TRGR_MOD_PERIOD_TRIG |
0395             AT91_ADC_TRGR_TRGPER_(st->ts_sample_period_val));
0396     } else if (status & AT91RL_ADC_IER_NOPEN) {
0397         reg = at91_adc_readl(st, AT91_ADC_MR);
0398         reg |= AT91_ADC_PENDBC_(st->ts_pendbc) & AT91_ADC_PENDBC;
0399         at91_adc_writel(st, AT91_ADC_MR, reg);
0400         at91_adc_writel(st, st->registers->trigger_register,
0401             AT91_ADC_TRGR_NONE);
0402 
0403         at91_adc_writel(st, AT91_ADC_IDR, AT91RL_ADC_IER_NOPEN
0404                 | AT91_ADC_EOC(3));
0405         at91_adc_writel(st, AT91_ADC_IER, AT91RL_ADC_IER_PEN);
0406         st->ts_bufferedmeasure = false;
0407         input_report_key(st->ts_input, BTN_TOUCH, 0);
0408         input_sync(st->ts_input);
0409     } else if (status & AT91_ADC_EOC(3) && st->ts_input) {
0410         /* Conversion finished and we've a touchscreen */
0411         if (st->ts_bufferedmeasure) {
0412             /*
0413              * Last measurement is always discarded, since it can
0414              * be erroneous.
0415              * Always report previous measurement
0416              */
0417             input_report_abs(st->ts_input, ABS_X, st->ts_prev_absx);
0418             input_report_abs(st->ts_input, ABS_Y, st->ts_prev_absy);
0419             input_report_key(st->ts_input, BTN_TOUCH, 1);
0420             input_sync(st->ts_input);
0421         } else
0422             st->ts_bufferedmeasure = true;
0423 
0424         /* Now make new measurement */
0425         st->ts_prev_absx = at91_adc_readl(st, AT91_ADC_CHAN(st, 3))
0426                    << MAX_RLPOS_BITS;
0427         st->ts_prev_absx /= at91_adc_readl(st, AT91_ADC_CHAN(st, 2));
0428 
0429         st->ts_prev_absy = at91_adc_readl(st, AT91_ADC_CHAN(st, 1))
0430                    << MAX_RLPOS_BITS;
0431         st->ts_prev_absy /= at91_adc_readl(st, AT91_ADC_CHAN(st, 0));
0432     }
0433 
0434     return IRQ_HANDLED;
0435 }
0436 
0437 static irqreturn_t at91_adc_9x5_interrupt(int irq, void *private)
0438 {
0439     struct iio_dev *idev = private;
0440     struct at91_adc_state *st = iio_priv(idev);
0441     u32 status = at91_adc_readl(st, st->registers->status_register);
0442     const uint32_t ts_data_irq_mask =
0443         AT91_ADC_IER_XRDY |
0444         AT91_ADC_IER_YRDY |
0445         AT91_ADC_IER_PRDY;
0446 
0447     if (status & GENMASK(st->num_channels - 1, 0))
0448         handle_adc_eoc_trigger(irq, idev);
0449 
0450     if (status & AT91_ADC_IER_PEN) {
0451         at91_adc_writel(st, AT91_ADC_IDR, AT91_ADC_IER_PEN);
0452         at91_adc_writel(st, AT91_ADC_IER, AT91_ADC_IER_NOPEN |
0453             ts_data_irq_mask);
0454         /* Set up period trigger for sampling */
0455         at91_adc_writel(st, st->registers->trigger_register,
0456             AT91_ADC_TRGR_MOD_PERIOD_TRIG |
0457             AT91_ADC_TRGR_TRGPER_(st->ts_sample_period_val));
0458     } else if (status & AT91_ADC_IER_NOPEN) {
0459         at91_adc_writel(st, st->registers->trigger_register, 0);
0460         at91_adc_writel(st, AT91_ADC_IDR, AT91_ADC_IER_NOPEN |
0461             ts_data_irq_mask);
0462         at91_adc_writel(st, AT91_ADC_IER, AT91_ADC_IER_PEN);
0463 
0464         input_report_key(st->ts_input, BTN_TOUCH, 0);
0465         input_sync(st->ts_input);
0466     } else if ((status & ts_data_irq_mask) == ts_data_irq_mask) {
0467         /* Now all touchscreen data is ready */
0468 
0469         if (status & AT91_ADC_ISR_PENS) {
0470             /* validate data by pen contact */
0471             at91_ts_sample(idev);
0472         } else {
0473             /* triggered by event that is no pen contact, just read
0474              * them to clean the interrupt and discard all.
0475              */
0476             at91_adc_readl(st, AT91_ADC_TSXPOSR);
0477             at91_adc_readl(st, AT91_ADC_TSYPOSR);
0478             at91_adc_readl(st, AT91_ADC_TSPRESSR);
0479         }
0480     }
0481 
0482     return IRQ_HANDLED;
0483 }
0484 
0485 static int at91_adc_channel_init(struct iio_dev *idev)
0486 {
0487     struct at91_adc_state *st = iio_priv(idev);
0488     struct iio_chan_spec *chan_array, *timestamp;
0489     int bit, idx = 0;
0490     unsigned long rsvd_mask = 0;
0491 
0492     /* If touchscreen is enable, then reserve the adc channels */
0493     if (st->touchscreen_type == ATMEL_ADC_TOUCHSCREEN_4WIRE)
0494         rsvd_mask = CHAN_MASK_TOUCHSCREEN_4WIRE;
0495     else if (st->touchscreen_type == ATMEL_ADC_TOUCHSCREEN_5WIRE)
0496         rsvd_mask = CHAN_MASK_TOUCHSCREEN_5WIRE;
0497 
0498     /* set up the channel mask to reserve touchscreen channels */
0499     st->channels_mask &= ~rsvd_mask;
0500 
0501     idev->num_channels = bitmap_weight(&st->channels_mask,
0502                        st->num_channels) + 1;
0503 
0504     chan_array = devm_kzalloc(&idev->dev,
0505                   ((idev->num_channels + 1) *
0506                     sizeof(struct iio_chan_spec)),
0507                   GFP_KERNEL);
0508 
0509     if (!chan_array)
0510         return -ENOMEM;
0511 
0512     for_each_set_bit(bit, &st->channels_mask, st->num_channels) {
0513         struct iio_chan_spec *chan = chan_array + idx;
0514 
0515         chan->type = IIO_VOLTAGE;
0516         chan->indexed = 1;
0517         chan->channel = bit;
0518         chan->scan_index = idx;
0519         chan->scan_type.sign = 'u';
0520         chan->scan_type.realbits = st->res;
0521         chan->scan_type.storagebits = 16;
0522         chan->info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE);
0523         chan->info_mask_separate = BIT(IIO_CHAN_INFO_RAW);
0524         idx++;
0525     }
0526     timestamp = chan_array + idx;
0527 
0528     timestamp->type = IIO_TIMESTAMP;
0529     timestamp->channel = -1;
0530     timestamp->scan_index = idx;
0531     timestamp->scan_type.sign = 's';
0532     timestamp->scan_type.realbits = 64;
0533     timestamp->scan_type.storagebits = 64;
0534 
0535     idev->channels = chan_array;
0536     return idev->num_channels;
0537 }
0538 
0539 static int at91_adc_get_trigger_value_by_name(struct iio_dev *idev,
0540                          const struct at91_adc_trigger *triggers,
0541                          const char *trigger_name)
0542 {
0543     struct at91_adc_state *st = iio_priv(idev);
0544     int i;
0545 
0546     for (i = 0; i < st->caps->trigger_number; i++) {
0547         char *name = kasprintf(GFP_KERNEL,
0548                 "%s-dev%d-%s",
0549                 idev->name,
0550                 iio_device_id(idev),
0551                 triggers[i].name);
0552         if (!name)
0553             return -ENOMEM;
0554 
0555         if (strcmp(trigger_name, name) == 0) {
0556             kfree(name);
0557             if (triggers[i].value == 0)
0558                 return -EINVAL;
0559             return triggers[i].value;
0560         }
0561 
0562         kfree(name);
0563     }
0564 
0565     return -EINVAL;
0566 }
0567 
0568 static int at91_adc_configure_trigger(struct iio_trigger *trig, bool state)
0569 {
0570     struct iio_dev *idev = iio_trigger_get_drvdata(trig);
0571     struct at91_adc_state *st = iio_priv(idev);
0572     const struct at91_adc_reg_desc *reg = st->registers;
0573     u32 status = at91_adc_readl(st, reg->trigger_register);
0574     int value;
0575     u8 bit;
0576 
0577     value = at91_adc_get_trigger_value_by_name(idev,
0578                            st->caps->triggers,
0579                            idev->trig->name);
0580     if (value < 0)
0581         return value;
0582 
0583     if (state) {
0584         st->buffer = kmalloc(idev->scan_bytes, GFP_KERNEL);
0585         if (st->buffer == NULL)
0586             return -ENOMEM;
0587 
0588         at91_adc_writel(st, reg->trigger_register,
0589                 status | value);
0590 
0591         for_each_set_bit(bit, idev->active_scan_mask,
0592                  st->num_channels) {
0593             struct iio_chan_spec const *chan = idev->channels + bit;
0594             at91_adc_writel(st, AT91_ADC_CHER,
0595                     AT91_ADC_CH(chan->channel));
0596         }
0597 
0598         at91_adc_writel(st, AT91_ADC_IER, reg->drdy_mask);
0599 
0600     } else {
0601         at91_adc_writel(st, AT91_ADC_IDR, reg->drdy_mask);
0602 
0603         at91_adc_writel(st, reg->trigger_register,
0604                 status & ~value);
0605 
0606         for_each_set_bit(bit, idev->active_scan_mask,
0607                  st->num_channels) {
0608             struct iio_chan_spec const *chan = idev->channels + bit;
0609             at91_adc_writel(st, AT91_ADC_CHDR,
0610                     AT91_ADC_CH(chan->channel));
0611         }
0612         kfree(st->buffer);
0613     }
0614 
0615     return 0;
0616 }
0617 
0618 static const struct iio_trigger_ops at91_adc_trigger_ops = {
0619     .set_trigger_state = &at91_adc_configure_trigger,
0620 };
0621 
0622 static struct iio_trigger *at91_adc_allocate_trigger(struct iio_dev *idev,
0623                              const struct at91_adc_trigger *trigger)
0624 {
0625     struct iio_trigger *trig;
0626     int ret;
0627 
0628     trig = iio_trigger_alloc(idev->dev.parent, "%s-dev%d-%s", idev->name,
0629                  iio_device_id(idev), trigger->name);
0630     if (trig == NULL)
0631         return NULL;
0632 
0633     iio_trigger_set_drvdata(trig, idev);
0634     trig->ops = &at91_adc_trigger_ops;
0635 
0636     ret = iio_trigger_register(trig);
0637     if (ret)
0638         return NULL;
0639 
0640     return trig;
0641 }
0642 
0643 static int at91_adc_trigger_init(struct iio_dev *idev)
0644 {
0645     struct at91_adc_state *st = iio_priv(idev);
0646     int i, ret;
0647 
0648     st->trig = devm_kcalloc(&idev->dev,
0649                 st->caps->trigger_number, sizeof(*st->trig),
0650                 GFP_KERNEL);
0651 
0652     if (st->trig == NULL) {
0653         ret = -ENOMEM;
0654         goto error_ret;
0655     }
0656 
0657     for (i = 0; i < st->caps->trigger_number; i++) {
0658         if (st->caps->triggers[i].is_external && !(st->use_external))
0659             continue;
0660 
0661         st->trig[i] = at91_adc_allocate_trigger(idev,
0662                             st->caps->triggers + i);
0663         if (st->trig[i] == NULL) {
0664             dev_err(&idev->dev,
0665                 "Could not allocate trigger %d\n", i);
0666             ret = -ENOMEM;
0667             goto error_trigger;
0668         }
0669     }
0670 
0671     return 0;
0672 
0673 error_trigger:
0674     for (i--; i >= 0; i--) {
0675         iio_trigger_unregister(st->trig[i]);
0676         iio_trigger_free(st->trig[i]);
0677     }
0678 error_ret:
0679     return ret;
0680 }
0681 
0682 static void at91_adc_trigger_remove(struct iio_dev *idev)
0683 {
0684     struct at91_adc_state *st = iio_priv(idev);
0685     int i;
0686 
0687     for (i = 0; i < st->caps->trigger_number; i++) {
0688         iio_trigger_unregister(st->trig[i]);
0689         iio_trigger_free(st->trig[i]);
0690     }
0691 }
0692 
0693 static int at91_adc_buffer_init(struct iio_dev *idev)
0694 {
0695     return iio_triggered_buffer_setup(idev, &iio_pollfunc_store_time,
0696         &at91_adc_trigger_handler, NULL);
0697 }
0698 
0699 static void at91_adc_buffer_remove(struct iio_dev *idev)
0700 {
0701     iio_triggered_buffer_cleanup(idev);
0702 }
0703 
0704 static int at91_adc_read_raw(struct iio_dev *idev,
0705                  struct iio_chan_spec const *chan,
0706                  int *val, int *val2, long mask)
0707 {
0708     struct at91_adc_state *st = iio_priv(idev);
0709     int ret;
0710 
0711     switch (mask) {
0712     case IIO_CHAN_INFO_RAW:
0713         mutex_lock(&st->lock);
0714 
0715         st->chnb = chan->channel;
0716         at91_adc_writel(st, AT91_ADC_CHER,
0717                 AT91_ADC_CH(chan->channel));
0718         at91_adc_writel(st, AT91_ADC_IER, BIT(chan->channel));
0719         at91_adc_writel(st, AT91_ADC_CR, AT91_ADC_START);
0720 
0721         ret = wait_event_interruptible_timeout(st->wq_data_avail,
0722                                st->done,
0723                                msecs_to_jiffies(1000));
0724 
0725         /* Disable interrupts, regardless if adc conversion was
0726          * successful or not
0727          */
0728         at91_adc_writel(st, AT91_ADC_CHDR,
0729                 AT91_ADC_CH(chan->channel));
0730         at91_adc_writel(st, AT91_ADC_IDR, BIT(chan->channel));
0731 
0732         if (ret > 0) {
0733             /* a valid conversion took place */
0734             *val = st->last_value;
0735             st->last_value = 0;
0736             st->done = false;
0737             ret = IIO_VAL_INT;
0738         } else if (ret == 0) {
0739             /* conversion timeout */
0740             dev_err(&idev->dev, "ADC Channel %d timeout.\n",
0741                 chan->channel);
0742             ret = -ETIMEDOUT;
0743         }
0744 
0745         mutex_unlock(&st->lock);
0746         return ret;
0747 
0748     case IIO_CHAN_INFO_SCALE:
0749         *val = st->vref_mv;
0750         *val2 = chan->scan_type.realbits;
0751         return IIO_VAL_FRACTIONAL_LOG2;
0752     default:
0753         break;
0754     }
0755     return -EINVAL;
0756 }
0757 
0758 
0759 static u32 calc_startup_ticks_9260(u32 startup_time, u32 adc_clk_khz)
0760 {
0761     /*
0762      * Number of ticks needed to cover the startup time of the ADC
0763      * as defined in the electrical characteristics of the board,
0764      * divided by 8. The formula thus is :
0765      *   Startup Time = (ticks + 1) * 8 / ADC Clock
0766      */
0767     return round_up((startup_time * adc_clk_khz / 1000) - 1, 8) / 8;
0768 }
0769 
0770 static u32 calc_startup_ticks_9x5(u32 startup_time, u32 adc_clk_khz)
0771 {
0772     /*
0773      * For sama5d3x and at91sam9x5, the formula changes to:
0774      * Startup Time = <lookup_table_value> / ADC Clock
0775      */
0776     static const int startup_lookup[] = {
0777         0,   8,   16,  24,
0778         64,  80,  96,  112,
0779         512, 576, 640, 704,
0780         768, 832, 896, 960
0781         };
0782     int i, size = ARRAY_SIZE(startup_lookup);
0783     unsigned int ticks;
0784 
0785     ticks = startup_time * adc_clk_khz / 1000;
0786     for (i = 0; i < size; i++)
0787         if (ticks < startup_lookup[i])
0788             break;
0789 
0790     ticks = i;
0791     if (ticks == size)
0792         /* Reach the end of lookup table */
0793         ticks = size - 1;
0794 
0795     return ticks;
0796 }
0797 
0798 static int at91_adc_probe_dt_ts(struct device_node *node,
0799     struct at91_adc_state *st, struct device *dev)
0800 {
0801     int ret;
0802     u32 prop;
0803 
0804     ret = of_property_read_u32(node, "atmel,adc-ts-wires", &prop);
0805     if (ret) {
0806         dev_info(dev, "ADC Touch screen is disabled.\n");
0807         return 0;
0808     }
0809 
0810     switch (prop) {
0811     case 4:
0812     case 5:
0813         st->touchscreen_type = prop;
0814         break;
0815     default:
0816         dev_err(dev, "Unsupported number of touchscreen wires (%d). Should be 4 or 5.\n", prop);
0817         return -EINVAL;
0818     }
0819 
0820     if (!st->caps->has_tsmr)
0821         return 0;
0822     prop = 0;
0823     of_property_read_u32(node, "atmel,adc-ts-pressure-threshold", &prop);
0824     st->ts_pressure_threshold = prop;
0825     if (st->ts_pressure_threshold) {
0826         return 0;
0827     } else {
0828         dev_err(dev, "Invalid pressure threshold for the touchscreen\n");
0829         return -EINVAL;
0830     }
0831 }
0832 
0833 static const struct iio_info at91_adc_info = {
0834     .read_raw = &at91_adc_read_raw,
0835 };
0836 
0837 /* Touchscreen related functions */
0838 static int atmel_ts_open(struct input_dev *dev)
0839 {
0840     struct at91_adc_state *st = input_get_drvdata(dev);
0841 
0842     if (st->caps->has_tsmr)
0843         at91_adc_writel(st, AT91_ADC_IER, AT91_ADC_IER_PEN);
0844     else
0845         at91_adc_writel(st, AT91_ADC_IER, AT91RL_ADC_IER_PEN);
0846     return 0;
0847 }
0848 
0849 static void atmel_ts_close(struct input_dev *dev)
0850 {
0851     struct at91_adc_state *st = input_get_drvdata(dev);
0852 
0853     if (st->caps->has_tsmr)
0854         at91_adc_writel(st, AT91_ADC_IDR, AT91_ADC_IER_PEN);
0855     else
0856         at91_adc_writel(st, AT91_ADC_IDR, AT91RL_ADC_IER_PEN);
0857 }
0858 
0859 static int at91_ts_hw_init(struct iio_dev *idev, u32 adc_clk_khz)
0860 {
0861     struct at91_adc_state *st = iio_priv(idev);
0862     u32 reg = 0;
0863     u32 tssctim = 0;
0864     int i = 0;
0865 
0866     /* a Pen Detect Debounce Time is necessary for the ADC Touch to avoid
0867      * pen detect noise.
0868      * The formula is : Pen Detect Debounce Time = (2 ^ pendbc) / ADCClock
0869      */
0870     st->ts_pendbc = round_up(TOUCH_PEN_DETECT_DEBOUNCE_US * adc_clk_khz /
0871                  1000, 1);
0872 
0873     while (st->ts_pendbc >> ++i)
0874         ;   /* Empty! Find the shift offset */
0875     if (abs(st->ts_pendbc - (1 << i)) < abs(st->ts_pendbc - (1 << (i - 1))))
0876         st->ts_pendbc = i;
0877     else
0878         st->ts_pendbc = i - 1;
0879 
0880     if (!st->caps->has_tsmr) {
0881         reg = at91_adc_readl(st, AT91_ADC_MR);
0882         reg |= AT91_ADC_TSAMOD_TS_ONLY_MODE | AT91_ADC_PENDET;
0883 
0884         reg |= AT91_ADC_PENDBC_(st->ts_pendbc) & AT91_ADC_PENDBC;
0885         at91_adc_writel(st, AT91_ADC_MR, reg);
0886 
0887         reg = AT91_ADC_TSR_SHTIM_(TOUCH_SHTIM) & AT91_ADC_TSR_SHTIM;
0888         at91_adc_writel(st, AT91_ADC_TSR, reg);
0889 
0890         st->ts_sample_period_val = round_up((TOUCH_SAMPLE_PERIOD_US_RL *
0891                             adc_clk_khz / 1000) - 1, 1);
0892 
0893         return 0;
0894     }
0895 
0896     /* Touchscreen Switches Closure time needed for allowing the value to
0897      * stabilize.
0898      * Switch Closure Time = (TSSCTIM * 4) ADCClock periods
0899      */
0900     tssctim = DIV_ROUND_UP(TOUCH_SCTIM_US * adc_clk_khz / 1000, 4);
0901     dev_dbg(&idev->dev, "adc_clk at: %d KHz, tssctim at: %d\n",
0902         adc_clk_khz, tssctim);
0903 
0904     if (st->touchscreen_type == ATMEL_ADC_TOUCHSCREEN_4WIRE)
0905         reg = AT91_ADC_TSMR_TSMODE_4WIRE_PRESS;
0906     else
0907         reg = AT91_ADC_TSMR_TSMODE_5WIRE;
0908 
0909     reg |= AT91_ADC_TSMR_SCTIM_(tssctim) & AT91_ADC_TSMR_SCTIM;
0910     reg |= AT91_ADC_TSMR_TSAV_(st->caps->ts_filter_average)
0911            & AT91_ADC_TSMR_TSAV;
0912     reg |= AT91_ADC_TSMR_PENDBC_(st->ts_pendbc) & AT91_ADC_TSMR_PENDBC;
0913     reg |= AT91_ADC_TSMR_NOTSDMA;
0914     reg |= AT91_ADC_TSMR_PENDET_ENA;
0915     reg |= 0x03 << 8;   /* TSFREQ, needs to be bigger than TSAV */
0916 
0917     at91_adc_writel(st, AT91_ADC_TSMR, reg);
0918 
0919     /* Change adc internal resistor value for better pen detection,
0920      * default value is 100 kOhm.
0921      * 0 = 200 kOhm, 1 = 150 kOhm, 2 = 100 kOhm, 3 = 50 kOhm
0922      * option only available on ES2 and higher
0923      */
0924     at91_adc_writel(st, AT91_ADC_ACR, st->caps->ts_pen_detect_sensitivity
0925             & AT91_ADC_ACR_PENDETSENS);
0926 
0927     /* Sample Period Time = (TRGPER + 1) / ADCClock */
0928     st->ts_sample_period_val = round_up((TOUCH_SAMPLE_PERIOD_US *
0929             adc_clk_khz / 1000) - 1, 1);
0930 
0931     return 0;
0932 }
0933 
0934 static int at91_ts_register(struct iio_dev *idev,
0935         struct platform_device *pdev)
0936 {
0937     struct at91_adc_state *st = iio_priv(idev);
0938     struct input_dev *input;
0939     int ret;
0940 
0941     input = input_allocate_device();
0942     if (!input) {
0943         dev_err(&idev->dev, "Failed to allocate TS device!\n");
0944         return -ENOMEM;
0945     }
0946 
0947     input->name = DRIVER_NAME;
0948     input->id.bustype = BUS_HOST;
0949     input->dev.parent = &pdev->dev;
0950     input->open = atmel_ts_open;
0951     input->close = atmel_ts_close;
0952 
0953     __set_bit(EV_ABS, input->evbit);
0954     __set_bit(EV_KEY, input->evbit);
0955     __set_bit(BTN_TOUCH, input->keybit);
0956     if (st->caps->has_tsmr) {
0957         input_set_abs_params(input, ABS_X, 0, (1 << MAX_POS_BITS) - 1,
0958                      0, 0);
0959         input_set_abs_params(input, ABS_Y, 0, (1 << MAX_POS_BITS) - 1,
0960                      0, 0);
0961         input_set_abs_params(input, ABS_PRESSURE, 0, 0xffffff, 0, 0);
0962     } else {
0963         if (st->touchscreen_type != ATMEL_ADC_TOUCHSCREEN_4WIRE) {
0964             dev_err(&pdev->dev,
0965                 "This touchscreen controller only support 4 wires\n");
0966             ret = -EINVAL;
0967             goto err;
0968         }
0969 
0970         input_set_abs_params(input, ABS_X, 0, (1 << MAX_RLPOS_BITS) - 1,
0971                      0, 0);
0972         input_set_abs_params(input, ABS_Y, 0, (1 << MAX_RLPOS_BITS) - 1,
0973                      0, 0);
0974     }
0975 
0976     st->ts_input = input;
0977     input_set_drvdata(input, st);
0978 
0979     ret = input_register_device(input);
0980     if (ret)
0981         goto err;
0982 
0983     return ret;
0984 
0985 err:
0986     input_free_device(st->ts_input);
0987     return ret;
0988 }
0989 
0990 static void at91_ts_unregister(struct at91_adc_state *st)
0991 {
0992     input_unregister_device(st->ts_input);
0993 }
0994 
0995 static int at91_adc_probe(struct platform_device *pdev)
0996 {
0997     unsigned int prsc, mstrclk, ticks, adc_clk, adc_clk_khz, shtim;
0998     struct device_node *node = pdev->dev.of_node;
0999     int ret;
1000     struct iio_dev *idev;
1001     struct at91_adc_state *st;
1002     u32 reg, prop;
1003     char *s;
1004 
1005     idev = devm_iio_device_alloc(&pdev->dev, sizeof(struct at91_adc_state));
1006     if (!idev)
1007         return -ENOMEM;
1008 
1009     st = iio_priv(idev);
1010 
1011     st->caps = of_device_get_match_data(&pdev->dev);
1012 
1013     st->use_external = of_property_read_bool(node, "atmel,adc-use-external-triggers");
1014 
1015     if (of_property_read_u32(node, "atmel,adc-channels-used", &prop)) {
1016         dev_err(&idev->dev, "Missing adc-channels-used property in the DT.\n");
1017         return -EINVAL;
1018     }
1019     st->channels_mask = prop;
1020 
1021     st->sleep_mode = of_property_read_bool(node, "atmel,adc-sleep-mode");
1022 
1023     if (of_property_read_u32(node, "atmel,adc-startup-time", &prop)) {
1024         dev_err(&idev->dev, "Missing adc-startup-time property in the DT.\n");
1025         return -EINVAL;
1026     }
1027     st->startup_time = prop;
1028 
1029     prop = 0;
1030     of_property_read_u32(node, "atmel,adc-sample-hold-time", &prop);
1031     st->sample_hold_time = prop;
1032 
1033     if (of_property_read_u32(node, "atmel,adc-vref", &prop)) {
1034         dev_err(&idev->dev, "Missing adc-vref property in the DT.\n");
1035         return -EINVAL;
1036     }
1037     st->vref_mv = prop;
1038 
1039     st->res = st->caps->high_res_bits;
1040     if (st->caps->low_res_bits &&
1041         !of_property_read_string(node, "atmel,adc-use-res", (const char **)&s)
1042         && !strcmp(s, "lowres"))
1043         st->res = st->caps->low_res_bits;
1044 
1045     dev_info(&idev->dev, "Resolution used: %u bits\n", st->res);
1046 
1047     st->registers = &st->caps->registers;
1048     st->num_channels = st->caps->num_channels;
1049 
1050     /* Check if touchscreen is supported. */
1051     if (st->caps->has_ts) {
1052         ret = at91_adc_probe_dt_ts(node, st, &idev->dev);
1053         if (ret)
1054             return ret;
1055     }
1056 
1057     platform_set_drvdata(pdev, idev);
1058 
1059     idev->name = dev_name(&pdev->dev);
1060     idev->modes = INDIO_DIRECT_MODE;
1061     idev->info = &at91_adc_info;
1062 
1063     st->irq = platform_get_irq(pdev, 0);
1064     if (st->irq < 0)
1065         return -ENODEV;
1066 
1067     st->reg_base = devm_platform_ioremap_resource(pdev, 0);
1068     if (IS_ERR(st->reg_base))
1069         return PTR_ERR(st->reg_base);
1070 
1071 
1072     /*
1073      * Disable all IRQs before setting up the handler
1074      */
1075     at91_adc_writel(st, AT91_ADC_CR, AT91_ADC_SWRST);
1076     at91_adc_writel(st, AT91_ADC_IDR, 0xFFFFFFFF);
1077 
1078     if (st->caps->has_tsmr)
1079         ret = request_irq(st->irq, at91_adc_9x5_interrupt, 0,
1080                   pdev->dev.driver->name, idev);
1081     else
1082         ret = request_irq(st->irq, at91_adc_rl_interrupt, 0,
1083                   pdev->dev.driver->name, idev);
1084     if (ret) {
1085         dev_err(&pdev->dev, "Failed to allocate IRQ.\n");
1086         return ret;
1087     }
1088 
1089     st->clk = devm_clk_get(&pdev->dev, "adc_clk");
1090     if (IS_ERR(st->clk)) {
1091         dev_err(&pdev->dev, "Failed to get the clock.\n");
1092         ret = PTR_ERR(st->clk);
1093         goto error_free_irq;
1094     }
1095 
1096     ret = clk_prepare_enable(st->clk);
1097     if (ret) {
1098         dev_err(&pdev->dev,
1099             "Could not prepare or enable the clock.\n");
1100         goto error_free_irq;
1101     }
1102 
1103     st->adc_clk = devm_clk_get(&pdev->dev, "adc_op_clk");
1104     if (IS_ERR(st->adc_clk)) {
1105         dev_err(&pdev->dev, "Failed to get the ADC clock.\n");
1106         ret = PTR_ERR(st->adc_clk);
1107         goto error_disable_clk;
1108     }
1109 
1110     ret = clk_prepare_enable(st->adc_clk);
1111     if (ret) {
1112         dev_err(&pdev->dev,
1113             "Could not prepare or enable the ADC clock.\n");
1114         goto error_disable_clk;
1115     }
1116 
1117     /*
1118      * Prescaler rate computation using the formula from the Atmel's
1119      * datasheet : ADC Clock = MCK / ((Prescaler + 1) * 2), ADC Clock being
1120      * specified by the electrical characteristics of the board.
1121      */
1122     mstrclk = clk_get_rate(st->clk);
1123     adc_clk = clk_get_rate(st->adc_clk);
1124     adc_clk_khz = adc_clk / 1000;
1125 
1126     dev_dbg(&pdev->dev, "Master clock is set as: %d Hz, adc_clk should set as: %d Hz\n",
1127         mstrclk, adc_clk);
1128 
1129     prsc = (mstrclk / (2 * adc_clk)) - 1;
1130 
1131     if (!st->startup_time) {
1132         dev_err(&pdev->dev, "No startup time available.\n");
1133         ret = -EINVAL;
1134         goto error_disable_adc_clk;
1135     }
1136     ticks = (*st->caps->calc_startup_ticks)(st->startup_time, adc_clk_khz);
1137 
1138     /*
1139      * a minimal Sample and Hold Time is necessary for the ADC to guarantee
1140      * the best converted final value between two channels selection
1141      * The formula thus is : Sample and Hold Time = (shtim + 1) / ADCClock
1142      */
1143     if (st->sample_hold_time > 0)
1144         shtim = round_up((st->sample_hold_time * adc_clk_khz / 1000)
1145                  - 1, 1);
1146     else
1147         shtim = 0;
1148 
1149     reg = AT91_ADC_PRESCAL_(prsc) & st->registers->mr_prescal_mask;
1150     reg |= AT91_ADC_STARTUP_(ticks) & st->registers->mr_startup_mask;
1151     if (st->res == st->caps->low_res_bits)
1152         reg |= AT91_ADC_LOWRES;
1153     if (st->sleep_mode)
1154         reg |= AT91_ADC_SLEEP;
1155     reg |= AT91_ADC_SHTIM_(shtim) & AT91_ADC_SHTIM;
1156     at91_adc_writel(st, AT91_ADC_MR, reg);
1157 
1158     /* Setup the ADC channels available on the board */
1159     ret = at91_adc_channel_init(idev);
1160     if (ret < 0) {
1161         dev_err(&pdev->dev, "Couldn't initialize the channels.\n");
1162         goto error_disable_adc_clk;
1163     }
1164 
1165     init_waitqueue_head(&st->wq_data_avail);
1166     mutex_init(&st->lock);
1167 
1168     /*
1169      * Since touch screen will set trigger register as period trigger. So
1170      * when touch screen is enabled, then we have to disable hardware
1171      * trigger for classic adc.
1172      */
1173     if (!st->touchscreen_type) {
1174         ret = at91_adc_buffer_init(idev);
1175         if (ret < 0) {
1176             dev_err(&pdev->dev, "Couldn't initialize the buffer.\n");
1177             goto error_disable_adc_clk;
1178         }
1179 
1180         ret = at91_adc_trigger_init(idev);
1181         if (ret < 0) {
1182             dev_err(&pdev->dev, "Couldn't setup the triggers.\n");
1183             at91_adc_buffer_remove(idev);
1184             goto error_disable_adc_clk;
1185         }
1186     } else {
1187         ret = at91_ts_register(idev, pdev);
1188         if (ret)
1189             goto error_disable_adc_clk;
1190 
1191         at91_ts_hw_init(idev, adc_clk_khz);
1192     }
1193 
1194     ret = iio_device_register(idev);
1195     if (ret < 0) {
1196         dev_err(&pdev->dev, "Couldn't register the device.\n");
1197         goto error_iio_device_register;
1198     }
1199 
1200     return 0;
1201 
1202 error_iio_device_register:
1203     if (!st->touchscreen_type) {
1204         at91_adc_trigger_remove(idev);
1205         at91_adc_buffer_remove(idev);
1206     } else {
1207         at91_ts_unregister(st);
1208     }
1209 error_disable_adc_clk:
1210     clk_disable_unprepare(st->adc_clk);
1211 error_disable_clk:
1212     clk_disable_unprepare(st->clk);
1213 error_free_irq:
1214     free_irq(st->irq, idev);
1215     return ret;
1216 }
1217 
1218 static int at91_adc_remove(struct platform_device *pdev)
1219 {
1220     struct iio_dev *idev = platform_get_drvdata(pdev);
1221     struct at91_adc_state *st = iio_priv(idev);
1222 
1223     iio_device_unregister(idev);
1224     if (!st->touchscreen_type) {
1225         at91_adc_trigger_remove(idev);
1226         at91_adc_buffer_remove(idev);
1227     } else {
1228         at91_ts_unregister(st);
1229     }
1230     clk_disable_unprepare(st->adc_clk);
1231     clk_disable_unprepare(st->clk);
1232     free_irq(st->irq, idev);
1233 
1234     return 0;
1235 }
1236 
1237 static int at91_adc_suspend(struct device *dev)
1238 {
1239     struct iio_dev *idev = dev_get_drvdata(dev);
1240     struct at91_adc_state *st = iio_priv(idev);
1241 
1242     pinctrl_pm_select_sleep_state(dev);
1243     clk_disable_unprepare(st->clk);
1244 
1245     return 0;
1246 }
1247 
1248 static int at91_adc_resume(struct device *dev)
1249 {
1250     struct iio_dev *idev = dev_get_drvdata(dev);
1251     struct at91_adc_state *st = iio_priv(idev);
1252 
1253     clk_prepare_enable(st->clk);
1254     pinctrl_pm_select_default_state(dev);
1255 
1256     return 0;
1257 }
1258 
1259 static DEFINE_SIMPLE_DEV_PM_OPS(at91_adc_pm_ops, at91_adc_suspend,
1260                 at91_adc_resume);
1261 
1262 static const struct at91_adc_trigger at91sam9260_triggers[] = {
1263     { .name = "timer-counter-0", .value = 0x1 },
1264     { .name = "timer-counter-1", .value = 0x3 },
1265     { .name = "timer-counter-2", .value = 0x5 },
1266     { .name = "external", .value = 0xd, .is_external = true },
1267 };
1268 
1269 static struct at91_adc_caps at91sam9260_caps = {
1270     .calc_startup_ticks = calc_startup_ticks_9260,
1271     .num_channels = 4,
1272     .low_res_bits = 8,
1273     .high_res_bits = 10,
1274     .registers = {
1275         .channel_base = AT91_ADC_CHR(0),
1276         .drdy_mask = AT91_ADC_DRDY,
1277         .status_register = AT91_ADC_SR,
1278         .trigger_register = AT91_ADC_TRGR_9260,
1279         .mr_prescal_mask = AT91_ADC_PRESCAL_9260,
1280         .mr_startup_mask = AT91_ADC_STARTUP_9260,
1281     },
1282     .triggers = at91sam9260_triggers,
1283     .trigger_number = ARRAY_SIZE(at91sam9260_triggers),
1284 };
1285 
1286 static const struct at91_adc_trigger at91sam9x5_triggers[] = {
1287     { .name = "external-rising", .value = 0x1, .is_external = true },
1288     { .name = "external-falling", .value = 0x2, .is_external = true },
1289     { .name = "external-any", .value = 0x3, .is_external = true },
1290     { .name = "continuous", .value = 0x6 },
1291 };
1292 
1293 static struct at91_adc_caps at91sam9rl_caps = {
1294     .has_ts = true,
1295     .calc_startup_ticks = calc_startup_ticks_9260,  /* same as 9260 */
1296     .num_channels = 6,
1297     .low_res_bits = 8,
1298     .high_res_bits = 10,
1299     .registers = {
1300         .channel_base = AT91_ADC_CHR(0),
1301         .drdy_mask = AT91_ADC_DRDY,
1302         .status_register = AT91_ADC_SR,
1303         .trigger_register = AT91_ADC_TRGR_9G45,
1304         .mr_prescal_mask = AT91_ADC_PRESCAL_9260,
1305         .mr_startup_mask = AT91_ADC_STARTUP_9G45,
1306     },
1307     .triggers = at91sam9x5_triggers,
1308     .trigger_number = ARRAY_SIZE(at91sam9x5_triggers),
1309 };
1310 
1311 static struct at91_adc_caps at91sam9g45_caps = {
1312     .has_ts = true,
1313     .calc_startup_ticks = calc_startup_ticks_9260,  /* same as 9260 */
1314     .num_channels = 8,
1315     .low_res_bits = 8,
1316     .high_res_bits = 10,
1317     .registers = {
1318         .channel_base = AT91_ADC_CHR(0),
1319         .drdy_mask = AT91_ADC_DRDY,
1320         .status_register = AT91_ADC_SR,
1321         .trigger_register = AT91_ADC_TRGR_9G45,
1322         .mr_prescal_mask = AT91_ADC_PRESCAL_9G45,
1323         .mr_startup_mask = AT91_ADC_STARTUP_9G45,
1324     },
1325     .triggers = at91sam9x5_triggers,
1326     .trigger_number = ARRAY_SIZE(at91sam9x5_triggers),
1327 };
1328 
1329 static struct at91_adc_caps at91sam9x5_caps = {
1330     .has_ts = true,
1331     .has_tsmr = true,
1332     .ts_filter_average = 3,
1333     .ts_pen_detect_sensitivity = 2,
1334     .calc_startup_ticks = calc_startup_ticks_9x5,
1335     .num_channels = 12,
1336     .low_res_bits = 8,
1337     .high_res_bits = 10,
1338     .registers = {
1339         .channel_base = AT91_ADC_CDR0_9X5,
1340         .drdy_mask = AT91_ADC_SR_DRDY_9X5,
1341         .status_register = AT91_ADC_SR_9X5,
1342         .trigger_register = AT91_ADC_TRGR_9X5,
1343         /* prescal mask is same as 9G45 */
1344         .mr_prescal_mask = AT91_ADC_PRESCAL_9G45,
1345         .mr_startup_mask = AT91_ADC_STARTUP_9X5,
1346     },
1347     .triggers = at91sam9x5_triggers,
1348     .trigger_number = ARRAY_SIZE(at91sam9x5_triggers),
1349 };
1350 
1351 static struct at91_adc_caps sama5d3_caps = {
1352     .has_ts = true,
1353     .has_tsmr = true,
1354     .ts_filter_average = 3,
1355     .ts_pen_detect_sensitivity = 2,
1356     .calc_startup_ticks = calc_startup_ticks_9x5,
1357     .num_channels = 12,
1358     .low_res_bits = 0,
1359     .high_res_bits = 12,
1360     .registers = {
1361         .channel_base = AT91_ADC_CDR0_9X5,
1362         .drdy_mask = AT91_ADC_SR_DRDY_9X5,
1363         .status_register = AT91_ADC_SR_9X5,
1364         .trigger_register = AT91_ADC_TRGR_9X5,
1365         .mr_prescal_mask = AT91_ADC_PRESCAL_9G45,
1366         .mr_startup_mask = AT91_ADC_STARTUP_9X5,
1367     },
1368     .triggers = at91sam9x5_triggers,
1369     .trigger_number = ARRAY_SIZE(at91sam9x5_triggers),
1370 };
1371 
1372 static const struct of_device_id at91_adc_dt_ids[] = {
1373     { .compatible = "atmel,at91sam9260-adc", .data = &at91sam9260_caps },
1374     { .compatible = "atmel,at91sam9rl-adc", .data = &at91sam9rl_caps },
1375     { .compatible = "atmel,at91sam9g45-adc", .data = &at91sam9g45_caps },
1376     { .compatible = "atmel,at91sam9x5-adc", .data = &at91sam9x5_caps },
1377     { .compatible = "atmel,sama5d3-adc", .data = &sama5d3_caps },
1378     {},
1379 };
1380 MODULE_DEVICE_TABLE(of, at91_adc_dt_ids);
1381 
1382 static struct platform_driver at91_adc_driver = {
1383     .probe = at91_adc_probe,
1384     .remove = at91_adc_remove,
1385     .driver = {
1386            .name = DRIVER_NAME,
1387            .of_match_table = at91_adc_dt_ids,
1388            .pm = pm_sleep_ptr(&at91_adc_pm_ops),
1389     },
1390 };
1391 
1392 module_platform_driver(at91_adc_driver);
1393 
1394 MODULE_LICENSE("GPL");
1395 MODULE_DESCRIPTION("Atmel AT91 ADC Driver");
1396 MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
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