iio/adc/aspeed_adc.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Aspeed AST2400/2500/2600 ADC
0004  *
0005  * Copyright (C) 2017 Google, Inc.
0006  * Copyright (C) 2021 Aspeed Technology Inc.
0007  *
0008  * ADC clock formula:
0009  * Ast2400/Ast2500:
0010  * clock period = period of PCLK * 2 * (ADC0C[31:17] + 1) * (ADC0C[9:0] + 1)
0011  * Ast2600:
0012  * clock period = period of PCLK * 2 * (ADC0C[15:0] + 1)
0013  */
0014
0015 #include <linux/clk.h>
0016 #include <linux/clk-provider.h>
0017 #include <linux/err.h>
0018 #include <linux/errno.h>
0019 #include <linux/io.h>
0020 #include <linux/module.h>
0021 #include <linux/of_platform.h>
0022 #include <linux/platform_device.h>
0023 #include <linux/regulator/consumer.h>
0024 #include <linux/reset.h>
0025 #include <linux/spinlock.h>
0026 #include <linux/types.h>
0027 #include <linux/bitfield.h>
0028 #include <linux/regmap.h>
0029 #include <linux/mfd/syscon.h>
0030
0031 #include <linux/iio/iio.h>
0032 #include <linux/iio/driver.h>
0033 #include <linux/iopoll.h>
0034
0035 #define ASPEED_RESOLUTION_BITS      10
0036 #define ASPEED_CLOCKS_PER_SAMPLE    12
0037
0038 #define ASPEED_REG_ENGINE_CONTROL   0x00
0039 #define ASPEED_REG_INTERRUPT_CONTROL    0x04
0040 #define ASPEED_REG_VGA_DETECT_CONTROL   0x08
0041 #define ASPEED_REG_CLOCK_CONTROL    0x0C
0042 #define ASPEED_REG_COMPENSATION_TRIM    0xC4
0043 /*
0044  * The register offset between 0xC8~0xCC can be read and won't affect the
0045  * hardware logic in each version of ADC.
0046  */
0047 #define ASPEED_REG_MAX          0xD0
0048
0049 #define ASPEED_ADC_ENGINE_ENABLE        BIT(0)
0050 #define ASPEED_ADC_OP_MODE          GENMASK(3, 1)
0051 #define ASPEED_ADC_OP_MODE_PWR_DOWN     0
0052 #define ASPEED_ADC_OP_MODE_STANDBY      1
0053 #define ASPEED_ADC_OP_MODE_NORMAL       7
0054 #define ASPEED_ADC_CTRL_COMPENSATION        BIT(4)
0055 #define ASPEED_ADC_AUTO_COMPENSATION        BIT(5)
0056 /*
0057  * Bit 6 determines not only the reference voltage range but also the dividing
0058  * circuit for battery sensing.
0059  */
0060 #define ASPEED_ADC_REF_VOLTAGE          GENMASK(7, 6)
0061 #define ASPEED_ADC_REF_VOLTAGE_2500mV       0
0062 #define ASPEED_ADC_REF_VOLTAGE_1200mV       1
0063 #define ASPEED_ADC_REF_VOLTAGE_EXT_HIGH     2
0064 #define ASPEED_ADC_REF_VOLTAGE_EXT_LOW      3
0065 #define ASPEED_ADC_BAT_SENSING_DIV      BIT(6)
0066 #define ASPEED_ADC_BAT_SENSING_DIV_2_3      0
0067 #define ASPEED_ADC_BAT_SENSING_DIV_1_3      1
0068 #define ASPEED_ADC_CTRL_INIT_RDY        BIT(8)
0069 #define ASPEED_ADC_CH7_MODE         BIT(12)
0070 #define ASPEED_ADC_CH7_NORMAL           0
0071 #define ASPEED_ADC_CH7_BAT          1
0072 #define ASPEED_ADC_BAT_SENSING_ENABLE       BIT(13)
0073 #define ASPEED_ADC_CTRL_CHANNEL         GENMASK(31, 16)
0074 #define ASPEED_ADC_CTRL_CHANNEL_ENABLE(ch)  FIELD_PREP(ASPEED_ADC_CTRL_CHANNEL, BIT(ch))
0075
0076 #define ASPEED_ADC_INIT_POLLING_TIME    500
0077 #define ASPEED_ADC_INIT_TIMEOUT     500000
0078 /*
0079  * When the sampling rate is too high, the ADC may not have enough charging
0080  * time, resulting in a low voltage value. Thus, the default uses a slow
0081  * sampling rate for most use cases.
0082  */
0083 #define ASPEED_ADC_DEF_SAMPLING_RATE    65000
0084
0085 struct aspeed_adc_trim_locate {
0086     const unsigned int offset;
0087     const unsigned int field;
0088 };
0089
0090 struct aspeed_adc_model_data {
0091     const char *model_name;
0092     unsigned int min_sampling_rate; // Hz
0093     unsigned int max_sampling_rate; // Hz
0094     unsigned int vref_fixed_mv;
0095     bool wait_init_sequence;
0096     bool need_prescaler;
0097     bool bat_sense_sup;
0098     u8 scaler_bit_width;
0099     unsigned int num_channels;
0100     const struct aspeed_adc_trim_locate *trim_locate;
0101 };
0102
0103 struct adc_gain {
0104     u8 mult;
0105     u8 div;
0106 };
0107
0108 struct aspeed_adc_data {
0109     struct device       *dev;
0110     const struct aspeed_adc_model_data *model_data;
0111     struct regulator    *regulator;
0112     void __iomem        *base;
0113     spinlock_t      clk_lock;
0114     struct clk_hw       *fixed_div_clk;
0115     struct clk_hw       *clk_prescaler;
0116     struct clk_hw       *clk_scaler;
0117     struct reset_control    *rst;
0118     int         vref_mv;
0119     u32         sample_period_ns;
0120     int         cv;
0121     bool            battery_sensing;
0122     struct adc_gain     battery_mode_gain;
0123 };
0124
0125 #define ASPEED_CHAN(_idx, _data_reg_addr) {         \
0126     .type = IIO_VOLTAGE,                    \
0127     .indexed = 1,                       \
0128     .channel = (_idx),                  \
0129     .address = (_data_reg_addr),                \
0130     .info_mask_separate = BIT(IIO_CHAN_INFO_RAW),       \
0131     .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) |  \
0132                 BIT(IIO_CHAN_INFO_SAMP_FREQ) |  \
0133                 BIT(IIO_CHAN_INFO_OFFSET),  \
0134 }
0135
0136 static const struct iio_chan_spec aspeed_adc_iio_channels[] = {
0137     ASPEED_CHAN(0, 0x10),
0138     ASPEED_CHAN(1, 0x12),
0139     ASPEED_CHAN(2, 0x14),
0140     ASPEED_CHAN(3, 0x16),
0141     ASPEED_CHAN(4, 0x18),
0142     ASPEED_CHAN(5, 0x1A),
0143     ASPEED_CHAN(6, 0x1C),
0144     ASPEED_CHAN(7, 0x1E),
0145     ASPEED_CHAN(8, 0x20),
0146     ASPEED_CHAN(9, 0x22),
0147     ASPEED_CHAN(10, 0x24),
0148     ASPEED_CHAN(11, 0x26),
0149     ASPEED_CHAN(12, 0x28),
0150     ASPEED_CHAN(13, 0x2A),
0151     ASPEED_CHAN(14, 0x2C),
0152     ASPEED_CHAN(15, 0x2E),
0153 };
0154
0155 #define ASPEED_BAT_CHAN(_idx, _data_reg_addr) {                 \
0156         .type = IIO_VOLTAGE,                        \
0157         .indexed = 1,                           \
0158         .channel = (_idx),                      \
0159         .address = (_data_reg_addr),                    \
0160         .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |          \
0161                       BIT(IIO_CHAN_INFO_OFFSET),        \
0162         .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) |      \
0163                         BIT(IIO_CHAN_INFO_SAMP_FREQ),   \
0164 }
0165 static const struct iio_chan_spec aspeed_adc_iio_bat_channels[] = {
0166     ASPEED_CHAN(0, 0x10),
0167     ASPEED_CHAN(1, 0x12),
0168     ASPEED_CHAN(2, 0x14),
0169     ASPEED_CHAN(3, 0x16),
0170     ASPEED_CHAN(4, 0x18),
0171     ASPEED_CHAN(5, 0x1A),
0172     ASPEED_CHAN(6, 0x1C),
0173     ASPEED_BAT_CHAN(7, 0x1E),
0174 };
0175
0176 static int aspeed_adc_set_trim_data(struct iio_dev *indio_dev)
0177 {
0178     struct device_node *syscon;
0179     struct regmap *scu;
0180     u32 scu_otp, trimming_val;
0181     struct aspeed_adc_data *data = iio_priv(indio_dev);
0182
0183     syscon = of_find_node_by_name(NULL, "syscon");
0184     if (syscon == NULL) {
0185         dev_warn(data->dev, "Couldn't find syscon node\n");
0186         return -EOPNOTSUPP;
0187     }
0188     scu = syscon_node_to_regmap(syscon);
0189     of_node_put(syscon);
0190     if (IS_ERR(scu)) {
0191         dev_warn(data->dev, "Failed to get syscon regmap\n");
0192         return -EOPNOTSUPP;
0193     }
0194     if (data->model_data->trim_locate) {
0195         if (regmap_read(scu, data->model_data->trim_locate->offset,
0196                 &scu_otp)) {
0197             dev_warn(data->dev,
0198                  "Failed to get adc trimming data\n");
0199             trimming_val = 0x8;
0200         } else {
0201             trimming_val =
0202                 ((scu_otp) &
0203                  (data->model_data->trim_locate->field)) >>
0204                 __ffs(data->model_data->trim_locate->field);
0205         }
0206         dev_dbg(data->dev,
0207             "trimming val = %d, offset = %08x, fields = %08x\n",
0208             trimming_val, data->model_data->trim_locate->offset,
0209             data->model_data->trim_locate->field);
0210         writel(trimming_val, data->base + ASPEED_REG_COMPENSATION_TRIM);
0211     }
0212     return 0;
0213 }
0214
0215 static int aspeed_adc_compensation(struct iio_dev *indio_dev)
0216 {
0217     struct aspeed_adc_data *data = iio_priv(indio_dev);
0218     u32 index, adc_raw = 0;
0219     u32 adc_engine_control_reg_val;
0220
0221     adc_engine_control_reg_val =
0222         readl(data->base + ASPEED_REG_ENGINE_CONTROL);
0223     adc_engine_control_reg_val &= ~ASPEED_ADC_OP_MODE;
0224     adc_engine_control_reg_val |=
0225         (FIELD_PREP(ASPEED_ADC_OP_MODE, ASPEED_ADC_OP_MODE_NORMAL) |
0226          ASPEED_ADC_ENGINE_ENABLE);
0227     /*
0228      * Enable compensating sensing:
0229      * After that, the input voltage of ADC will force to half of the reference
0230      * voltage. So the expected reading raw data will become half of the max
0231      * value. We can get compensating value = 0x200 - ADC read raw value.
0232      * It is recommended to average at least 10 samples to get a final CV.
0233      */
0234     writel(adc_engine_control_reg_val | ASPEED_ADC_CTRL_COMPENSATION |
0235                ASPEED_ADC_CTRL_CHANNEL_ENABLE(0),
0236            data->base + ASPEED_REG_ENGINE_CONTROL);
0237     /*
0238      * After enable compensating sensing mode need to wait some time for ADC stable
0239      * Experiment result is 1ms.
0240      */
0241     mdelay(1);
0242
0243     for (index = 0; index < 16; index++) {
0244         /*
0245          * Waiting for the sampling period ensures that the value acquired
0246          * is fresh each time.
0247          */
0248         ndelay(data->sample_period_ns);
0249         adc_raw += readw(data->base + aspeed_adc_iio_channels[0].address);
0250     }
0251     adc_raw >>= 4;
0252     data->cv = BIT(ASPEED_RESOLUTION_BITS - 1) - adc_raw;
0253     writel(adc_engine_control_reg_val,
0254            data->base + ASPEED_REG_ENGINE_CONTROL);
0255     dev_dbg(data->dev, "Compensating value = %d\n", data->cv);
0256
0257     return 0;
0258 }
0259
0260 static int aspeed_adc_set_sampling_rate(struct iio_dev *indio_dev, u32 rate)
0261 {
0262     struct aspeed_adc_data *data = iio_priv(indio_dev);
0263
0264     if (rate < data->model_data->min_sampling_rate ||
0265         rate > data->model_data->max_sampling_rate)
0266         return -EINVAL;
0267     /* Each sampling needs 12 clocks to convert.*/
0268     clk_set_rate(data->clk_scaler->clk, rate * ASPEED_CLOCKS_PER_SAMPLE);
0269     rate = clk_get_rate(data->clk_scaler->clk);
0270     data->sample_period_ns = DIV_ROUND_UP_ULL(
0271         (u64)NSEC_PER_SEC * ASPEED_CLOCKS_PER_SAMPLE, rate);
0272     dev_dbg(data->dev, "Adc clock = %d sample period = %d ns", rate,
0273         data->sample_period_ns);
0274
0275     return 0;
0276 }
0277
0278 static int aspeed_adc_read_raw(struct iio_dev *indio_dev,
0279                    struct iio_chan_spec const *chan,
0280                    int *val, int *val2, long mask)
0281 {
0282     struct aspeed_adc_data *data = iio_priv(indio_dev);
0283     u32 adc_engine_control_reg_val;
0284
0285     switch (mask) {
0286     case IIO_CHAN_INFO_RAW:
0287         if (data->battery_sensing && chan->channel == 7) {
0288             adc_engine_control_reg_val =
0289                 readl(data->base + ASPEED_REG_ENGINE_CONTROL);
0290             writel(adc_engine_control_reg_val |
0291                        FIELD_PREP(ASPEED_ADC_CH7_MODE,
0292                           ASPEED_ADC_CH7_BAT) |
0293                        ASPEED_ADC_BAT_SENSING_ENABLE,
0294                    data->base + ASPEED_REG_ENGINE_CONTROL);
0295             /*
0296              * After enable battery sensing mode need to wait some time for adc stable
0297              * Experiment result is 1ms.
0298              */
0299             mdelay(1);
0300             *val = readw(data->base + chan->address);
0301             *val = (*val * data->battery_mode_gain.mult) /
0302                    data->battery_mode_gain.div;
0303             /* Restore control register value */
0304             writel(adc_engine_control_reg_val,
0305                    data->base + ASPEED_REG_ENGINE_CONTROL);
0306         } else
0307             *val = readw(data->base + chan->address);
0308         return IIO_VAL_INT;
0309
0310     case IIO_CHAN_INFO_OFFSET:
0311         if (data->battery_sensing && chan->channel == 7)
0312             *val = (data->cv * data->battery_mode_gain.mult) /
0313                    data->battery_mode_gain.div;
0314         else
0315             *val = data->cv;
0316         return IIO_VAL_INT;
0317
0318     case IIO_CHAN_INFO_SCALE:
0319         *val = data->vref_mv;
0320         *val2 = ASPEED_RESOLUTION_BITS;
0321         return IIO_VAL_FRACTIONAL_LOG2;
0322
0323     case IIO_CHAN_INFO_SAMP_FREQ:
0324         *val = clk_get_rate(data->clk_scaler->clk) /
0325                 ASPEED_CLOCKS_PER_SAMPLE;
0326         return IIO_VAL_INT;
0327
0328     default:
0329         return -EINVAL;
0330     }
0331 }
0332
0333 static int aspeed_adc_write_raw(struct iio_dev *indio_dev,
0334                 struct iio_chan_spec const *chan,
0335                 int val, int val2, long mask)
0336 {
0337     switch (mask) {
0338     case IIO_CHAN_INFO_SAMP_FREQ:
0339         return aspeed_adc_set_sampling_rate(indio_dev, val);
0340
0341     case IIO_CHAN_INFO_SCALE:
0342     case IIO_CHAN_INFO_RAW:
0343         /*
0344          * Technically, these could be written but the only reasons
0345          * for doing so seem better handled in userspace.  EPERM is
0346          * returned to signal this is a policy choice rather than a
0347          * hardware limitation.
0348          */
0349         return -EPERM;
0350
0351     default:
0352         return -EINVAL;
0353     }
0354 }
0355
0356 static int aspeed_adc_reg_access(struct iio_dev *indio_dev,
0357                  unsigned int reg, unsigned int writeval,
0358                  unsigned int *readval)
0359 {
0360     struct aspeed_adc_data *data = iio_priv(indio_dev);
0361
0362     if (!readval || reg % 4 || reg > ASPEED_REG_MAX)
0363         return -EINVAL;
0364
0365     *readval = readl(data->base + reg);
0366
0367     return 0;
0368 }
0369
0370 static const struct iio_info aspeed_adc_iio_info = {
0371     .read_raw = aspeed_adc_read_raw,
0372     .write_raw = aspeed_adc_write_raw,
0373     .debugfs_reg_access = aspeed_adc_reg_access,
0374 };
0375
0376 static void aspeed_adc_unregister_fixed_divider(void *data)
0377 {
0378     struct clk_hw *clk = data;
0379
0380     clk_hw_unregister_fixed_factor(clk);
0381 }
0382
0383 static void aspeed_adc_reset_assert(void *data)
0384 {
0385     struct reset_control *rst = data;
0386
0387     reset_control_assert(rst);
0388 }
0389
0390 static void aspeed_adc_clk_disable_unprepare(void *data)
0391 {
0392     struct clk *clk = data;
0393
0394     clk_disable_unprepare(clk);
0395 }
0396
0397 static void aspeed_adc_power_down(void *data)
0398 {
0399     struct aspeed_adc_data *priv_data = data;
0400
0401     writel(FIELD_PREP(ASPEED_ADC_OP_MODE, ASPEED_ADC_OP_MODE_PWR_DOWN),
0402            priv_data->base + ASPEED_REG_ENGINE_CONTROL);
0403 }
0404
0405 static void aspeed_adc_reg_disable(void *data)
0406 {
0407     struct regulator *reg = data;
0408
0409     regulator_disable(reg);
0410 }
0411
0412 static int aspeed_adc_vref_config(struct iio_dev *indio_dev)
0413 {
0414     struct aspeed_adc_data *data = iio_priv(indio_dev);
0415     int ret;
0416     u32 adc_engine_control_reg_val;
0417
0418     if (data->model_data->vref_fixed_mv) {
0419         data->vref_mv = data->model_data->vref_fixed_mv;
0420         return 0;
0421     }
0422     adc_engine_control_reg_val =
0423         readl(data->base + ASPEED_REG_ENGINE_CONTROL);
0424     data->regulator = devm_regulator_get_optional(data->dev, "vref");
0425     if (!IS_ERR(data->regulator)) {
0426         ret = regulator_enable(data->regulator);
0427         if (ret)
0428             return ret;
0429         ret = devm_add_action_or_reset(
0430             data->dev, aspeed_adc_reg_disable, data->regulator);
0431         if (ret)
0432             return ret;
0433         data->vref_mv = regulator_get_voltage(data->regulator);
0434         /* Conversion from uV to mV */
0435         data->vref_mv /= 1000;
0436         if ((data->vref_mv >= 1550) && (data->vref_mv <= 2700))
0437             writel(adc_engine_control_reg_val |
0438                 FIELD_PREP(
0439                     ASPEED_ADC_REF_VOLTAGE,
0440                     ASPEED_ADC_REF_VOLTAGE_EXT_HIGH),
0441             data->base + ASPEED_REG_ENGINE_CONTROL);
0442         else if ((data->vref_mv >= 900) && (data->vref_mv <= 1650))
0443             writel(adc_engine_control_reg_val |
0444                 FIELD_PREP(
0445                     ASPEED_ADC_REF_VOLTAGE,
0446                     ASPEED_ADC_REF_VOLTAGE_EXT_LOW),
0447             data->base + ASPEED_REG_ENGINE_CONTROL);
0448         else {
0449             dev_err(data->dev, "Regulator voltage %d not support",
0450                 data->vref_mv);
0451             return -EOPNOTSUPP;
0452         }
0453     } else {
0454         if (PTR_ERR(data->regulator) != -ENODEV)
0455             return PTR_ERR(data->regulator);
0456         data->vref_mv = 2500000;
0457         of_property_read_u32(data->dev->of_node,
0458                      "aspeed,int-vref-microvolt",
0459                      &data->vref_mv);
0460         /* Conversion from uV to mV */
0461         data->vref_mv /= 1000;
0462         if (data->vref_mv == 2500)
0463             writel(adc_engine_control_reg_val |
0464                 FIELD_PREP(ASPEED_ADC_REF_VOLTAGE,
0465                         ASPEED_ADC_REF_VOLTAGE_2500mV),
0466             data->base + ASPEED_REG_ENGINE_CONTROL);
0467         else if (data->vref_mv == 1200)
0468             writel(adc_engine_control_reg_val |
0469                 FIELD_PREP(ASPEED_ADC_REF_VOLTAGE,
0470                         ASPEED_ADC_REF_VOLTAGE_1200mV),
0471             data->base + ASPEED_REG_ENGINE_CONTROL);
0472         else {
0473             dev_err(data->dev, "Voltage %d not support", data->vref_mv);
0474             return -EOPNOTSUPP;
0475         }
0476     }
0477
0478     return 0;
0479 }
0480
0481 static int aspeed_adc_probe(struct platform_device *pdev)
0482 {
0483     struct iio_dev *indio_dev;
0484     struct aspeed_adc_data *data;
0485     int ret;
0486     u32 adc_engine_control_reg_val;
0487     unsigned long scaler_flags = 0;
0488     char clk_name[32], clk_parent_name[32];
0489
0490     indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*data));
0491     if (!indio_dev)
0492         return -ENOMEM;
0493
0494     data = iio_priv(indio_dev);
0495     data->dev = &pdev->dev;
0496     data->model_data = of_device_get_match_data(&pdev->dev);
0497     platform_set_drvdata(pdev, indio_dev);
0498
0499     data->base = devm_platform_ioremap_resource(pdev, 0);
0500     if (IS_ERR(data->base))
0501         return PTR_ERR(data->base);
0502
0503     /* Register ADC clock prescaler with source specified by device tree. */
0504     spin_lock_init(&data->clk_lock);
0505     snprintf(clk_parent_name, ARRAY_SIZE(clk_parent_name), "%s",
0506          of_clk_get_parent_name(pdev->dev.of_node, 0));
0507     snprintf(clk_name, ARRAY_SIZE(clk_name), "%s-fixed-div",
0508          data->model_data->model_name);
0509     data->fixed_div_clk = clk_hw_register_fixed_factor(
0510         &pdev->dev, clk_name, clk_parent_name, 0, 1, 2);
0511     if (IS_ERR(data->fixed_div_clk))
0512         return PTR_ERR(data->fixed_div_clk);
0513
0514     ret = devm_add_action_or_reset(data->dev,
0515                        aspeed_adc_unregister_fixed_divider,
0516                        data->fixed_div_clk);
0517     if (ret)
0518         return ret;
0519     snprintf(clk_parent_name, ARRAY_SIZE(clk_parent_name), clk_name);
0520
0521     if (data->model_data->need_prescaler) {
0522         snprintf(clk_name, ARRAY_SIZE(clk_name), "%s-prescaler",
0523              data->model_data->model_name);
0524         data->clk_prescaler = devm_clk_hw_register_divider(
0525             &pdev->dev, clk_name, clk_parent_name, 0,
0526             data->base + ASPEED_REG_CLOCK_CONTROL, 17, 15, 0,
0527             &data->clk_lock);
0528         if (IS_ERR(data->clk_prescaler))
0529             return PTR_ERR(data->clk_prescaler);
0530         snprintf(clk_parent_name, ARRAY_SIZE(clk_parent_name),
0531              clk_name);
0532         scaler_flags = CLK_SET_RATE_PARENT;
0533     }
0534     /*
0535      * Register ADC clock scaler downstream from the prescaler. Allow rate
0536      * setting to adjust the prescaler as well.
0537      */
0538     snprintf(clk_name, ARRAY_SIZE(clk_name), "%s-scaler",
0539          data->model_data->model_name);
0540     data->clk_scaler = devm_clk_hw_register_divider(
0541         &pdev->dev, clk_name, clk_parent_name, scaler_flags,
0542         data->base + ASPEED_REG_CLOCK_CONTROL, 0,
0543         data->model_data->scaler_bit_width,
0544         data->model_data->need_prescaler ? CLK_DIVIDER_ONE_BASED : 0,
0545         &data->clk_lock);
0546     if (IS_ERR(data->clk_scaler))
0547         return PTR_ERR(data->clk_scaler);
0548
0549     data->rst = devm_reset_control_get_shared(&pdev->dev, NULL);
0550     if (IS_ERR(data->rst)) {
0551         dev_err(&pdev->dev,
0552             "invalid or missing reset controller device tree entry");
0553         return PTR_ERR(data->rst);
0554     }
0555     reset_control_deassert(data->rst);
0556
0557     ret = devm_add_action_or_reset(data->dev, aspeed_adc_reset_assert,
0558                        data->rst);
0559     if (ret)
0560         return ret;
0561
0562     ret = aspeed_adc_vref_config(indio_dev);
0563     if (ret)
0564         return ret;
0565
0566     if (of_find_property(data->dev->of_node, "aspeed,trim-data-valid",
0567                  NULL)) {
0568         ret = aspeed_adc_set_trim_data(indio_dev);
0569         if (ret)
0570             return ret;
0571     }
0572
0573     if (of_find_property(data->dev->of_node, "aspeed,battery-sensing",
0574                  NULL)) {
0575         if (data->model_data->bat_sense_sup) {
0576             data->battery_sensing = 1;
0577             if (readl(data->base + ASPEED_REG_ENGINE_CONTROL) &
0578                 ASPEED_ADC_BAT_SENSING_DIV) {
0579                 data->battery_mode_gain.mult = 3;
0580                 data->battery_mode_gain.div = 1;
0581             } else {
0582                 data->battery_mode_gain.mult = 3;
0583                 data->battery_mode_gain.div = 2;
0584             }
0585         } else
0586             dev_warn(&pdev->dev,
0587                  "Failed to enable battery-sensing mode\n");
0588     }
0589
0590     ret = clk_prepare_enable(data->clk_scaler->clk);
0591     if (ret)
0592         return ret;
0593     ret = devm_add_action_or_reset(data->dev,
0594                        aspeed_adc_clk_disable_unprepare,
0595                        data->clk_scaler->clk);
0596     if (ret)
0597         return ret;
0598     ret = aspeed_adc_set_sampling_rate(indio_dev,
0599                        ASPEED_ADC_DEF_SAMPLING_RATE);
0600     if (ret)
0601         return ret;
0602
0603     adc_engine_control_reg_val =
0604         readl(data->base + ASPEED_REG_ENGINE_CONTROL);
0605     adc_engine_control_reg_val |=
0606         FIELD_PREP(ASPEED_ADC_OP_MODE, ASPEED_ADC_OP_MODE_NORMAL) |
0607         ASPEED_ADC_ENGINE_ENABLE;
0608     /* Enable engine in normal mode. */
0609     writel(adc_engine_control_reg_val,
0610            data->base + ASPEED_REG_ENGINE_CONTROL);
0611
0612     ret = devm_add_action_or_reset(data->dev, aspeed_adc_power_down,
0613                     data);
0614     if (ret)
0615         return ret;
0616
0617     if (data->model_data->wait_init_sequence) {
0618         /* Wait for initial sequence complete. */
0619         ret = readl_poll_timeout(data->base + ASPEED_REG_ENGINE_CONTROL,
0620                      adc_engine_control_reg_val,
0621                      adc_engine_control_reg_val &
0622                      ASPEED_ADC_CTRL_INIT_RDY,
0623                      ASPEED_ADC_INIT_POLLING_TIME,
0624                      ASPEED_ADC_INIT_TIMEOUT);
0625         if (ret)
0626             return ret;
0627     }
0628
0629     aspeed_adc_compensation(indio_dev);
0630     /* Start all channels in normal mode. */
0631     adc_engine_control_reg_val =
0632         readl(data->base + ASPEED_REG_ENGINE_CONTROL);
0633     adc_engine_control_reg_val |= ASPEED_ADC_CTRL_CHANNEL;
0634     writel(adc_engine_control_reg_val,
0635            data->base + ASPEED_REG_ENGINE_CONTROL);
0636
0637     indio_dev->name = data->model_data->model_name;
0638     indio_dev->info = &aspeed_adc_iio_info;
0639     indio_dev->modes = INDIO_DIRECT_MODE;
0640     indio_dev->channels = data->battery_sensing ?
0641                         aspeed_adc_iio_bat_channels :
0642                         aspeed_adc_iio_channels;
0643     indio_dev->num_channels = data->model_data->num_channels;
0644
0645     ret = devm_iio_device_register(data->dev, indio_dev);
0646     return ret;
0647 }
0648
0649 static const struct aspeed_adc_trim_locate ast2500_adc_trim = {
0650     .offset = 0x154,
0651     .field = GENMASK(31, 28),
0652 };
0653
0654 static const struct aspeed_adc_trim_locate ast2600_adc0_trim = {
0655     .offset = 0x5d0,
0656     .field = GENMASK(3, 0),
0657 };
0658
0659 static const struct aspeed_adc_trim_locate ast2600_adc1_trim = {
0660     .offset = 0x5d0,
0661     .field = GENMASK(7, 4),
0662 };
0663
0664 static const struct aspeed_adc_model_data ast2400_model_data = {
0665     .model_name = "ast2400-adc",
0666     .vref_fixed_mv = 2500,
0667     .min_sampling_rate = 10000,
0668     .max_sampling_rate = 500000,
0669     .need_prescaler = true,
0670     .scaler_bit_width = 10,
0671     .num_channels = 16,
0672 };
0673
0674 static const struct aspeed_adc_model_data ast2500_model_data = {
0675     .model_name = "ast2500-adc",
0676     .vref_fixed_mv = 1800,
0677     .min_sampling_rate = 1,
0678     .max_sampling_rate = 1000000,
0679     .wait_init_sequence = true,
0680     .need_prescaler = true,
0681     .scaler_bit_width = 10,
0682     .num_channels = 16,
0683     .trim_locate = &ast2500_adc_trim,
0684 };
0685
0686 static const struct aspeed_adc_model_data ast2600_adc0_model_data = {
0687     .model_name = "ast2600-adc0",
0688     .min_sampling_rate = 10000,
0689     .max_sampling_rate = 500000,
0690     .wait_init_sequence = true,
0691     .bat_sense_sup = true,
0692     .scaler_bit_width = 16,
0693     .num_channels = 8,
0694     .trim_locate = &ast2600_adc0_trim,
0695 };
0696
0697 static const struct aspeed_adc_model_data ast2600_adc1_model_data = {
0698     .model_name = "ast2600-adc1",
0699     .min_sampling_rate = 10000,
0700     .max_sampling_rate = 500000,
0701     .wait_init_sequence = true,
0702     .bat_sense_sup = true,
0703     .scaler_bit_width = 16,
0704     .num_channels = 8,
0705     .trim_locate = &ast2600_adc1_trim,
0706 };
0707
0708 static const struct of_device_id aspeed_adc_matches[] = {
0709     { .compatible = "aspeed,ast2400-adc", .data = &ast2400_model_data },
0710     { .compatible = "aspeed,ast2500-adc", .data = &ast2500_model_data },
0711     { .compatible = "aspeed,ast2600-adc0", .data = &ast2600_adc0_model_data },
0712     { .compatible = "aspeed,ast2600-adc1", .data = &ast2600_adc1_model_data },
0713     {},
0714 };
0715 MODULE_DEVICE_TABLE(of, aspeed_adc_matches);
0716
0717 static struct platform_driver aspeed_adc_driver = {
0718     .probe = aspeed_adc_probe,
0719     .driver = {
0720         .name = KBUILD_MODNAME,
0721         .of_match_table = aspeed_adc_matches,
0722     }
0723 };
0724
0725 module_platform_driver(aspeed_adc_driver);
0726
0727 MODULE_AUTHOR("Rick Altherr <raltherr@google.com>");
0728 MODULE_DESCRIPTION("Aspeed AST2400/2500/2600 ADC Driver");
0729 MODULE_LICENSE("GPL");