iio/adc/adi-axi-adc.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Analog Devices Generic AXI ADC IP core
0004  * Link: https://wiki.analog.com/resources/fpga/docs/axi_adc_ip
0005  *
0006  * Copyright 2012-2020 Analog Devices Inc.
0007  */
0008
0009 #include <linux/bitfield.h>
0010 #include <linux/clk.h>
0011 #include <linux/io.h>
0012 #include <linux/delay.h>
0013 #include <linux/module.h>
0014 #include <linux/of_device.h>
0015 #include <linux/platform_device.h>
0016 #include <linux/slab.h>
0017
0018 #include <linux/iio/iio.h>
0019 #include <linux/iio/sysfs.h>
0020 #include <linux/iio/buffer.h>
0021 #include <linux/iio/buffer-dmaengine.h>
0022
0023 #include <linux/fpga/adi-axi-common.h>
0024 #include <linux/iio/adc/adi-axi-adc.h>
0025
0026 /*
0027  * Register definitions:
0028  *   https://wiki.analog.com/resources/fpga/docs/axi_adc_ip#register_map
0029  */
0030
0031 /* ADC controls */
0032
0033 #define ADI_AXI_REG_RSTN            0x0040
0034 #define   ADI_AXI_REG_RSTN_CE_N         BIT(2)
0035 #define   ADI_AXI_REG_RSTN_MMCM_RSTN        BIT(1)
0036 #define   ADI_AXI_REG_RSTN_RSTN         BIT(0)
0037
0038 /* ADC Channel controls */
0039
0040 #define ADI_AXI_REG_CHAN_CTRL(c)        (0x0400 + (c) * 0x40)
0041 #define   ADI_AXI_REG_CHAN_CTRL_LB_OWR      BIT(11)
0042 #define   ADI_AXI_REG_CHAN_CTRL_PN_SEL_OWR  BIT(10)
0043 #define   ADI_AXI_REG_CHAN_CTRL_IQCOR_EN    BIT(9)
0044 #define   ADI_AXI_REG_CHAN_CTRL_DCFILT_EN   BIT(8)
0045 #define   ADI_AXI_REG_CHAN_CTRL_FMT_SIGNEXT BIT(6)
0046 #define   ADI_AXI_REG_CHAN_CTRL_FMT_TYPE    BIT(5)
0047 #define   ADI_AXI_REG_CHAN_CTRL_FMT_EN      BIT(4)
0048 #define   ADI_AXI_REG_CHAN_CTRL_PN_TYPE_OWR BIT(1)
0049 #define   ADI_AXI_REG_CHAN_CTRL_ENABLE      BIT(0)
0050
0051 #define ADI_AXI_REG_CHAN_CTRL_DEFAULTS      \
0052     (ADI_AXI_REG_CHAN_CTRL_FMT_SIGNEXT |    \
0053      ADI_AXI_REG_CHAN_CTRL_FMT_EN |     \
0054      ADI_AXI_REG_CHAN_CTRL_ENABLE)
0055
0056 struct adi_axi_adc_core_info {
0057     unsigned int                version;
0058 };
0059
0060 struct adi_axi_adc_state {
0061     struct mutex                lock;
0062
0063     struct adi_axi_adc_client       *client;
0064     void __iomem                *regs;
0065 };
0066
0067 struct adi_axi_adc_client {
0068     struct list_head            entry;
0069     struct adi_axi_adc_conv         conv;
0070     struct adi_axi_adc_state        *state;
0071     struct device               *dev;
0072     const struct adi_axi_adc_core_info  *info;
0073 };
0074
0075 static LIST_HEAD(registered_clients);
0076 static DEFINE_MUTEX(registered_clients_lock);
0077
0078 static struct adi_axi_adc_client *conv_to_client(struct adi_axi_adc_conv *conv)
0079 {
0080     return container_of(conv, struct adi_axi_adc_client, conv);
0081 }
0082
0083 void *adi_axi_adc_conv_priv(struct adi_axi_adc_conv *conv)
0084 {
0085     struct adi_axi_adc_client *cl = conv_to_client(conv);
0086
0087     return (char *)cl + ALIGN(sizeof(struct adi_axi_adc_client),
0088                   IIO_DMA_MINALIGN);
0089 }
0090 EXPORT_SYMBOL_NS_GPL(adi_axi_adc_conv_priv, IIO_ADI_AXI);
0091
0092 static void adi_axi_adc_write(struct adi_axi_adc_state *st,
0093                   unsigned int reg,
0094                   unsigned int val)
0095 {
0096     iowrite32(val, st->regs + reg);
0097 }
0098
0099 static unsigned int adi_axi_adc_read(struct adi_axi_adc_state *st,
0100                      unsigned int reg)
0101 {
0102     return ioread32(st->regs + reg);
0103 }
0104
0105 static int adi_axi_adc_config_dma_buffer(struct device *dev,
0106                      struct iio_dev *indio_dev)
0107 {
0108     const char *dma_name;
0109
0110     if (!device_property_present(dev, "dmas"))
0111         return 0;
0112
0113     if (device_property_read_string(dev, "dma-names", &dma_name))
0114         dma_name = "rx";
0115
0116     return devm_iio_dmaengine_buffer_setup(indio_dev->dev.parent,
0117                            indio_dev, dma_name);
0118 }
0119
0120 static int adi_axi_adc_read_raw(struct iio_dev *indio_dev,
0121                 struct iio_chan_spec const *chan,
0122                 int *val, int *val2, long mask)
0123 {
0124     struct adi_axi_adc_state *st = iio_priv(indio_dev);
0125     struct adi_axi_adc_conv *conv = &st->client->conv;
0126
0127     if (!conv->read_raw)
0128         return -EOPNOTSUPP;
0129
0130     return conv->read_raw(conv, chan, val, val2, mask);
0131 }
0132
0133 static int adi_axi_adc_write_raw(struct iio_dev *indio_dev,
0134                  struct iio_chan_spec const *chan,
0135                  int val, int val2, long mask)
0136 {
0137     struct adi_axi_adc_state *st = iio_priv(indio_dev);
0138     struct adi_axi_adc_conv *conv = &st->client->conv;
0139
0140     if (!conv->write_raw)
0141         return -EOPNOTSUPP;
0142
0143     return conv->write_raw(conv, chan, val, val2, mask);
0144 }
0145
0146 static int adi_axi_adc_update_scan_mode(struct iio_dev *indio_dev,
0147                     const unsigned long *scan_mask)
0148 {
0149     struct adi_axi_adc_state *st = iio_priv(indio_dev);
0150     struct adi_axi_adc_conv *conv = &st->client->conv;
0151     unsigned int i, ctrl;
0152
0153     for (i = 0; i < conv->chip_info->num_channels; i++) {
0154         ctrl = adi_axi_adc_read(st, ADI_AXI_REG_CHAN_CTRL(i));
0155
0156         if (test_bit(i, scan_mask))
0157             ctrl |= ADI_AXI_REG_CHAN_CTRL_ENABLE;
0158         else
0159             ctrl &= ~ADI_AXI_REG_CHAN_CTRL_ENABLE;
0160
0161         adi_axi_adc_write(st, ADI_AXI_REG_CHAN_CTRL(i), ctrl);
0162     }
0163
0164     return 0;
0165 }
0166
0167 static struct adi_axi_adc_conv *adi_axi_adc_conv_register(struct device *dev,
0168                               size_t sizeof_priv)
0169 {
0170     struct adi_axi_adc_client *cl;
0171     size_t alloc_size;
0172
0173     alloc_size = ALIGN(sizeof(struct adi_axi_adc_client), IIO_DMA_MINALIGN);
0174     if (sizeof_priv)
0175         alloc_size += ALIGN(sizeof_priv, IIO_DMA_MINALIGN);
0176
0177     cl = kzalloc(alloc_size, GFP_KERNEL);
0178     if (!cl)
0179         return ERR_PTR(-ENOMEM);
0180
0181     mutex_lock(&registered_clients_lock);
0182
0183     cl->dev = get_device(dev);
0184
0185     list_add_tail(&cl->entry, &registered_clients);
0186
0187     mutex_unlock(&registered_clients_lock);
0188
0189     return &cl->conv;
0190 }
0191
0192 static void adi_axi_adc_conv_unregister(struct adi_axi_adc_conv *conv)
0193 {
0194     struct adi_axi_adc_client *cl = conv_to_client(conv);
0195
0196     mutex_lock(&registered_clients_lock);
0197
0198     list_del(&cl->entry);
0199     put_device(cl->dev);
0200
0201     mutex_unlock(&registered_clients_lock);
0202
0203     kfree(cl);
0204 }
0205
0206 static void devm_adi_axi_adc_conv_release(void *conv)
0207 {
0208     adi_axi_adc_conv_unregister(conv);
0209 }
0210
0211 struct adi_axi_adc_conv *devm_adi_axi_adc_conv_register(struct device *dev,
0212                             size_t sizeof_priv)
0213 {
0214     struct adi_axi_adc_conv *conv;
0215     int ret;
0216
0217     conv = adi_axi_adc_conv_register(dev, sizeof_priv);
0218     if (IS_ERR(conv))
0219         return conv;
0220
0221     ret = devm_add_action_or_reset(dev, devm_adi_axi_adc_conv_release,
0222                        conv);
0223     if (ret)
0224         return ERR_PTR(ret);
0225
0226     return conv;
0227 }
0228 EXPORT_SYMBOL_NS_GPL(devm_adi_axi_adc_conv_register, IIO_ADI_AXI);
0229
0230 static ssize_t in_voltage_scale_available_show(struct device *dev,
0231                            struct device_attribute *attr,
0232                            char *buf)
0233 {
0234     struct iio_dev *indio_dev = dev_to_iio_dev(dev);
0235     struct adi_axi_adc_state *st = iio_priv(indio_dev);
0236     struct adi_axi_adc_conv *conv = &st->client->conv;
0237     size_t len = 0;
0238     int i;
0239
0240     for (i = 0; i < conv->chip_info->num_scales; i++) {
0241         const unsigned int *s = conv->chip_info->scale_table[i];
0242
0243         len += scnprintf(buf + len, PAGE_SIZE - len,
0244                  "%u.%06u ", s[0], s[1]);
0245     }
0246     buf[len - 1] = '\n';
0247
0248     return len;
0249 }
0250
0251 static IIO_DEVICE_ATTR_RO(in_voltage_scale_available, 0);
0252
0253 enum {
0254     ADI_AXI_ATTR_SCALE_AVAIL,
0255 };
0256
0257 #define ADI_AXI_ATTR(_en_, _file_)          \
0258     [ADI_AXI_ATTR_##_en_] = &iio_dev_attr_##_file_.dev_attr.attr
0259
0260 static struct attribute *adi_axi_adc_attributes[] = {
0261     ADI_AXI_ATTR(SCALE_AVAIL, in_voltage_scale_available),
0262     NULL
0263 };
0264
0265 static umode_t axi_adc_attr_is_visible(struct kobject *kobj,
0266                        struct attribute *attr, int n)
0267 {
0268     struct device *dev = kobj_to_dev(kobj);
0269     struct iio_dev *indio_dev = dev_to_iio_dev(dev);
0270     struct adi_axi_adc_state *st = iio_priv(indio_dev);
0271     struct adi_axi_adc_conv *conv = &st->client->conv;
0272
0273     switch (n) {
0274     case ADI_AXI_ATTR_SCALE_AVAIL:
0275         if (!conv->chip_info->num_scales)
0276             return 0;
0277         return attr->mode;
0278     default:
0279         return attr->mode;
0280     }
0281 }
0282
0283 static const struct attribute_group adi_axi_adc_attribute_group = {
0284     .attrs = adi_axi_adc_attributes,
0285     .is_visible = axi_adc_attr_is_visible,
0286 };
0287
0288 static const struct iio_info adi_axi_adc_info = {
0289     .read_raw = &adi_axi_adc_read_raw,
0290     .write_raw = &adi_axi_adc_write_raw,
0291     .attrs = &adi_axi_adc_attribute_group,
0292     .update_scan_mode = &adi_axi_adc_update_scan_mode,
0293 };
0294
0295 static const struct adi_axi_adc_core_info adi_axi_adc_10_0_a_info = {
0296     .version = ADI_AXI_PCORE_VER(10, 0, 'a'),
0297 };
0298
0299 static struct adi_axi_adc_client *adi_axi_adc_attach_client(struct device *dev)
0300 {
0301     const struct adi_axi_adc_core_info *info;
0302     struct adi_axi_adc_client *cl;
0303     struct device_node *cln;
0304
0305     info = of_device_get_match_data(dev);
0306     if (!info)
0307         return ERR_PTR(-ENODEV);
0308
0309     cln = of_parse_phandle(dev->of_node, "adi,adc-dev", 0);
0310     if (!cln) {
0311         dev_err(dev, "No 'adi,adc-dev' node defined\n");
0312         return ERR_PTR(-ENODEV);
0313     }
0314
0315     mutex_lock(&registered_clients_lock);
0316
0317     list_for_each_entry(cl, &registered_clients, entry) {
0318         if (!cl->dev)
0319             continue;
0320
0321         if (cl->dev->of_node != cln)
0322             continue;
0323
0324         if (!try_module_get(cl->dev->driver->owner)) {
0325             mutex_unlock(&registered_clients_lock);
0326             of_node_put(cln);
0327             return ERR_PTR(-ENODEV);
0328         }
0329
0330         get_device(cl->dev);
0331         cl->info = info;
0332         mutex_unlock(&registered_clients_lock);
0333         of_node_put(cln);
0334         return cl;
0335     }
0336
0337     mutex_unlock(&registered_clients_lock);
0338     of_node_put(cln);
0339
0340     return ERR_PTR(-EPROBE_DEFER);
0341 }
0342
0343 static int adi_axi_adc_setup_channels(struct device *dev,
0344                       struct adi_axi_adc_state *st)
0345 {
0346     struct adi_axi_adc_conv *conv = &st->client->conv;
0347     int i, ret;
0348
0349     if (conv->preenable_setup) {
0350         ret = conv->preenable_setup(conv);
0351         if (ret)
0352             return ret;
0353     }
0354
0355     for (i = 0; i < conv->chip_info->num_channels; i++) {
0356         adi_axi_adc_write(st, ADI_AXI_REG_CHAN_CTRL(i),
0357                   ADI_AXI_REG_CHAN_CTRL_DEFAULTS);
0358     }
0359
0360     return 0;
0361 }
0362
0363 static void axi_adc_reset(struct adi_axi_adc_state *st)
0364 {
0365     adi_axi_adc_write(st, ADI_AXI_REG_RSTN, 0);
0366     mdelay(10);
0367     adi_axi_adc_write(st, ADI_AXI_REG_RSTN, ADI_AXI_REG_RSTN_MMCM_RSTN);
0368     mdelay(10);
0369     adi_axi_adc_write(st, ADI_AXI_REG_RSTN,
0370               ADI_AXI_REG_RSTN_RSTN | ADI_AXI_REG_RSTN_MMCM_RSTN);
0371 }
0372
0373 static void adi_axi_adc_cleanup(void *data)
0374 {
0375     struct adi_axi_adc_client *cl = data;
0376
0377     put_device(cl->dev);
0378     module_put(cl->dev->driver->owner);
0379 }
0380
0381 static int adi_axi_adc_probe(struct platform_device *pdev)
0382 {
0383     struct adi_axi_adc_conv *conv;
0384     struct iio_dev *indio_dev;
0385     struct adi_axi_adc_client *cl;
0386     struct adi_axi_adc_state *st;
0387     unsigned int ver;
0388     int ret;
0389
0390     cl = adi_axi_adc_attach_client(&pdev->dev);
0391     if (IS_ERR(cl))
0392         return PTR_ERR(cl);
0393
0394     ret = devm_add_action_or_reset(&pdev->dev, adi_axi_adc_cleanup, cl);
0395     if (ret)
0396         return ret;
0397
0398     indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*st));
0399     if (indio_dev == NULL)
0400         return -ENOMEM;
0401
0402     st = iio_priv(indio_dev);
0403     st->client = cl;
0404     cl->state = st;
0405     mutex_init(&st->lock);
0406
0407     st->regs = devm_platform_ioremap_resource(pdev, 0);
0408     if (IS_ERR(st->regs))
0409         return PTR_ERR(st->regs);
0410
0411     conv = &st->client->conv;
0412
0413     axi_adc_reset(st);
0414
0415     ver = adi_axi_adc_read(st, ADI_AXI_REG_VERSION);
0416
0417     if (cl->info->version > ver) {
0418         dev_err(&pdev->dev,
0419             "IP core version is too old. Expected %d.%.2d.%c, Reported %d.%.2d.%c\n",
0420             ADI_AXI_PCORE_VER_MAJOR(cl->info->version),
0421             ADI_AXI_PCORE_VER_MINOR(cl->info->version),
0422             ADI_AXI_PCORE_VER_PATCH(cl->info->version),
0423             ADI_AXI_PCORE_VER_MAJOR(ver),
0424             ADI_AXI_PCORE_VER_MINOR(ver),
0425             ADI_AXI_PCORE_VER_PATCH(ver));
0426         return -ENODEV;
0427     }
0428
0429     indio_dev->info = &adi_axi_adc_info;
0430     indio_dev->name = "adi-axi-adc";
0431     indio_dev->modes = INDIO_DIRECT_MODE;
0432     indio_dev->num_channels = conv->chip_info->num_channels;
0433     indio_dev->channels = conv->chip_info->channels;
0434
0435     ret = adi_axi_adc_config_dma_buffer(&pdev->dev, indio_dev);
0436     if (ret)
0437         return ret;
0438
0439     ret = adi_axi_adc_setup_channels(&pdev->dev, st);
0440     if (ret)
0441         return ret;
0442
0443     ret = devm_iio_device_register(&pdev->dev, indio_dev);
0444     if (ret)
0445         return ret;
0446
0447     dev_info(&pdev->dev, "AXI ADC IP core (%d.%.2d.%c) probed\n",
0448          ADI_AXI_PCORE_VER_MAJOR(ver),
0449          ADI_AXI_PCORE_VER_MINOR(ver),
0450          ADI_AXI_PCORE_VER_PATCH(ver));
0451
0452     return 0;
0453 }
0454
0455 /* Match table for of_platform binding */
0456 static const struct of_device_id adi_axi_adc_of_match[] = {
0457     { .compatible = "adi,axi-adc-10.0.a", .data = &adi_axi_adc_10_0_a_info },
0458     { /* end of list */ }
0459 };
0460 MODULE_DEVICE_TABLE(of, adi_axi_adc_of_match);
0461
0462 static struct platform_driver adi_axi_adc_driver = {
0463     .driver = {
0464         .name = KBUILD_MODNAME,
0465         .of_match_table = adi_axi_adc_of_match,
0466     },
0467     .probe = adi_axi_adc_probe,
0468 };
0469 module_platform_driver(adi_axi_adc_driver);
0470
0471 MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>");
0472 MODULE_DESCRIPTION("Analog Devices Generic AXI ADC IP core driver");
0473 MODULE_LICENSE("GPL v2");