iio/adc/ad9467.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Analog Devices AD9467 SPI ADC driver
0004  *
0005  * Copyright 2012-2020 Analog Devices Inc.
0006  */
0007
0008 #include <linux/module.h>
0009 #include <linux/device.h>
0010 #include <linux/kernel.h>
0011 #include <linux/slab.h>
0012 #include <linux/spi/spi.h>
0013 #include <linux/err.h>
0014 #include <linux/delay.h>
0015 #include <linux/gpio/consumer.h>
0016 #include <linux/of_device.h>
0017
0018
0019 #include <linux/iio/iio.h>
0020 #include <linux/iio/sysfs.h>
0021
0022 #include <linux/clk.h>
0023
0024 #include <linux/iio/adc/adi-axi-adc.h>
0025
0026 /*
0027  * ADI High-Speed ADC common spi interface registers
0028  * See Application-Note AN-877:
0029  *   https://www.analog.com/media/en/technical-documentation/application-notes/AN-877.pdf
0030  */
0031
0032 #define AN877_ADC_REG_CHIP_PORT_CONF        0x00
0033 #define AN877_ADC_REG_CHIP_ID           0x01
0034 #define AN877_ADC_REG_CHIP_GRADE        0x02
0035 #define AN877_ADC_REG_CHAN_INDEX        0x05
0036 #define AN877_ADC_REG_TRANSFER          0xFF
0037 #define AN877_ADC_REG_MODES         0x08
0038 #define AN877_ADC_REG_TEST_IO           0x0D
0039 #define AN877_ADC_REG_ADC_INPUT         0x0F
0040 #define AN877_ADC_REG_OFFSET            0x10
0041 #define AN877_ADC_REG_OUTPUT_MODE       0x14
0042 #define AN877_ADC_REG_OUTPUT_ADJUST     0x15
0043 #define AN877_ADC_REG_OUTPUT_PHASE      0x16
0044 #define AN877_ADC_REG_OUTPUT_DELAY      0x17
0045 #define AN877_ADC_REG_VREF          0x18
0046 #define AN877_ADC_REG_ANALOG_INPUT      0x2C
0047
0048 /* AN877_ADC_REG_TEST_IO */
0049 #define AN877_ADC_TESTMODE_OFF          0x0
0050 #define AN877_ADC_TESTMODE_MIDSCALE_SHORT   0x1
0051 #define AN877_ADC_TESTMODE_POS_FULLSCALE    0x2
0052 #define AN877_ADC_TESTMODE_NEG_FULLSCALE    0x3
0053 #define AN877_ADC_TESTMODE_ALT_CHECKERBOARD 0x4
0054 #define AN877_ADC_TESTMODE_PN23_SEQ     0x5
0055 #define AN877_ADC_TESTMODE_PN9_SEQ      0x6
0056 #define AN877_ADC_TESTMODE_ONE_ZERO_TOGGLE  0x7
0057 #define AN877_ADC_TESTMODE_USER         0x8
0058 #define AN877_ADC_TESTMODE_BIT_TOGGLE       0x9
0059 #define AN877_ADC_TESTMODE_SYNC         0xA
0060 #define AN877_ADC_TESTMODE_ONE_BIT_HIGH     0xB
0061 #define AN877_ADC_TESTMODE_MIXED_BIT_FREQUENCY  0xC
0062 #define AN877_ADC_TESTMODE_RAMP         0xF
0063
0064 /* AN877_ADC_REG_TRANSFER */
0065 #define AN877_ADC_TRANSFER_SYNC         0x1
0066
0067 /* AN877_ADC_REG_OUTPUT_MODE */
0068 #define AN877_ADC_OUTPUT_MODE_OFFSET_BINARY 0x0
0069 #define AN877_ADC_OUTPUT_MODE_TWOS_COMPLEMENT   0x1
0070 #define AN877_ADC_OUTPUT_MODE_GRAY_CODE     0x2
0071
0072 /* AN877_ADC_REG_OUTPUT_PHASE */
0073 #define AN877_ADC_OUTPUT_EVEN_ODD_MODE_EN   0x20
0074 #define AN877_ADC_INVERT_DCO_CLK        0x80
0075
0076 /* AN877_ADC_REG_OUTPUT_DELAY */
0077 #define AN877_ADC_DCO_DELAY_ENABLE      0x80
0078
0079 /*
0080  * Analog Devices AD9265 16-Bit, 125/105/80 MSPS ADC
0081  */
0082
0083 #define CHIPID_AD9265           0x64
0084 #define AD9265_DEF_OUTPUT_MODE      0x40
0085 #define AD9265_REG_VREF_MASK        0xC0
0086
0087 /*
0088  * Analog Devices AD9434 12-Bit, 370/500 MSPS ADC
0089  */
0090
0091 #define CHIPID_AD9434           0x6A
0092 #define AD9434_DEF_OUTPUT_MODE      0x00
0093 #define AD9434_REG_VREF_MASK        0xC0
0094
0095 /*
0096  * Analog Devices AD9467 16-Bit, 200/250 MSPS ADC
0097  */
0098
0099 #define CHIPID_AD9467           0x50
0100 #define AD9467_DEF_OUTPUT_MODE      0x08
0101 #define AD9467_REG_VREF_MASK        0x0F
0102
0103 enum {
0104     ID_AD9265,
0105     ID_AD9434,
0106     ID_AD9467,
0107 };
0108
0109 struct ad9467_chip_info {
0110     struct adi_axi_adc_chip_info    axi_adc_info;
0111     unsigned int            default_output_mode;
0112     unsigned int            vref_mask;
0113 };
0114
0115 #define to_ad9467_chip_info(_info)  \
0116     container_of(_info, struct ad9467_chip_info, axi_adc_info)
0117
0118 struct ad9467_state {
0119     struct spi_device       *spi;
0120     struct clk          *clk;
0121     unsigned int            output_mode;
0122
0123     struct gpio_desc        *pwrdown_gpio;
0124     struct gpio_desc        *reset_gpio;
0125 };
0126
0127 static int ad9467_spi_read(struct spi_device *spi, unsigned int reg)
0128 {
0129     unsigned char tbuf[2], rbuf[1];
0130     int ret;
0131
0132     tbuf[0] = 0x80 | (reg >> 8);
0133     tbuf[1] = reg & 0xFF;
0134
0135     ret = spi_write_then_read(spi,
0136                   tbuf, ARRAY_SIZE(tbuf),
0137                   rbuf, ARRAY_SIZE(rbuf));
0138
0139     if (ret < 0)
0140         return ret;
0141
0142     return rbuf[0];
0143 }
0144
0145 static int ad9467_spi_write(struct spi_device *spi, unsigned int reg,
0146                 unsigned int val)
0147 {
0148     unsigned char buf[3];
0149
0150     buf[0] = reg >> 8;
0151     buf[1] = reg & 0xFF;
0152     buf[2] = val;
0153
0154     return spi_write(spi, buf, ARRAY_SIZE(buf));
0155 }
0156
0157 static int ad9467_reg_access(struct adi_axi_adc_conv *conv, unsigned int reg,
0158                  unsigned int writeval, unsigned int *readval)
0159 {
0160     struct ad9467_state *st = adi_axi_adc_conv_priv(conv);
0161     struct spi_device *spi = st->spi;
0162     int ret;
0163
0164     if (readval == NULL) {
0165         ret = ad9467_spi_write(spi, reg, writeval);
0166         ad9467_spi_write(spi, AN877_ADC_REG_TRANSFER,
0167                  AN877_ADC_TRANSFER_SYNC);
0168         return ret;
0169     }
0170
0171     ret = ad9467_spi_read(spi, reg);
0172     if (ret < 0)
0173         return ret;
0174     *readval = ret;
0175
0176     return 0;
0177 }
0178
0179 static const unsigned int ad9265_scale_table[][2] = {
0180     {1250, 0x00}, {1500, 0x40}, {1750, 0x80}, {2000, 0xC0},
0181 };
0182
0183 static const unsigned int ad9434_scale_table[][2] = {
0184     {1600, 0x1C}, {1580, 0x1D}, {1550, 0x1E}, {1520, 0x1F}, {1500, 0x00},
0185     {1470, 0x01}, {1440, 0x02}, {1420, 0x03}, {1390, 0x04}, {1360, 0x05},
0186     {1340, 0x06}, {1310, 0x07}, {1280, 0x08}, {1260, 0x09}, {1230, 0x0A},
0187     {1200, 0x0B}, {1180, 0x0C},
0188 };
0189
0190 static const unsigned int ad9467_scale_table[][2] = {
0191     {2000, 0}, {2100, 6}, {2200, 7},
0192     {2300, 8}, {2400, 9}, {2500, 10},
0193 };
0194
0195 static void __ad9467_get_scale(struct adi_axi_adc_conv *conv, int index,
0196                    unsigned int *val, unsigned int *val2)
0197 {
0198     const struct adi_axi_adc_chip_info *info = conv->chip_info;
0199     const struct iio_chan_spec *chan = &info->channels[0];
0200     unsigned int tmp;
0201
0202     tmp = (info->scale_table[index][0] * 1000000ULL) >>
0203             chan->scan_type.realbits;
0204     *val = tmp / 1000000;
0205     *val2 = tmp % 1000000;
0206 }
0207
0208 #define AD9467_CHAN(_chan, _si, _bits, _sign)               \
0209 {                                   \
0210     .type = IIO_VOLTAGE,                        \
0211     .indexed = 1,                           \
0212     .channel = _chan,                       \
0213     .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) |      \
0214         BIT(IIO_CHAN_INFO_SAMP_FREQ),               \
0215     .scan_index = _si,                      \
0216     .scan_type = {                          \
0217         .sign = _sign,                      \
0218         .realbits = _bits,                  \
0219         .storagebits = 16,                  \
0220     },                              \
0221 }
0222
0223 static const struct iio_chan_spec ad9434_channels[] = {
0224     AD9467_CHAN(0, 0, 12, 'S'),
0225 };
0226
0227 static const struct iio_chan_spec ad9467_channels[] = {
0228     AD9467_CHAN(0, 0, 16, 'S'),
0229 };
0230
0231 static const struct ad9467_chip_info ad9467_chip_tbl[] = {
0232     [ID_AD9265] = {
0233         .axi_adc_info = {
0234             .id = CHIPID_AD9265,
0235             .max_rate = 125000000UL,
0236             .scale_table = ad9265_scale_table,
0237             .num_scales = ARRAY_SIZE(ad9265_scale_table),
0238             .channels = ad9467_channels,
0239             .num_channels = ARRAY_SIZE(ad9467_channels),
0240         },
0241         .default_output_mode = AD9265_DEF_OUTPUT_MODE,
0242         .vref_mask = AD9265_REG_VREF_MASK,
0243     },
0244     [ID_AD9434] = {
0245         .axi_adc_info = {
0246             .id = CHIPID_AD9434,
0247             .max_rate = 500000000UL,
0248             .scale_table = ad9434_scale_table,
0249             .num_scales = ARRAY_SIZE(ad9434_scale_table),
0250             .channels = ad9434_channels,
0251             .num_channels = ARRAY_SIZE(ad9434_channels),
0252         },
0253         .default_output_mode = AD9434_DEF_OUTPUT_MODE,
0254         .vref_mask = AD9434_REG_VREF_MASK,
0255     },
0256     [ID_AD9467] = {
0257         .axi_adc_info = {
0258             .id = CHIPID_AD9467,
0259             .max_rate = 250000000UL,
0260             .scale_table = ad9467_scale_table,
0261             .num_scales = ARRAY_SIZE(ad9467_scale_table),
0262             .channels = ad9467_channels,
0263             .num_channels = ARRAY_SIZE(ad9467_channels),
0264         },
0265         .default_output_mode = AD9467_DEF_OUTPUT_MODE,
0266         .vref_mask = AD9467_REG_VREF_MASK,
0267     },
0268 };
0269
0270 static int ad9467_get_scale(struct adi_axi_adc_conv *conv, int *val, int *val2)
0271 {
0272     const struct adi_axi_adc_chip_info *info = conv->chip_info;
0273     const struct ad9467_chip_info *info1 = to_ad9467_chip_info(info);
0274     struct ad9467_state *st = adi_axi_adc_conv_priv(conv);
0275     unsigned int i, vref_val;
0276
0277     vref_val = ad9467_spi_read(st->spi, AN877_ADC_REG_VREF);
0278
0279     vref_val &= info1->vref_mask;
0280
0281     for (i = 0; i < info->num_scales; i++) {
0282         if (vref_val == info->scale_table[i][1])
0283             break;
0284     }
0285
0286     if (i == info->num_scales)
0287         return -ERANGE;
0288
0289     __ad9467_get_scale(conv, i, val, val2);
0290
0291     return IIO_VAL_INT_PLUS_MICRO;
0292 }
0293
0294 static int ad9467_set_scale(struct adi_axi_adc_conv *conv, int val, int val2)
0295 {
0296     const struct adi_axi_adc_chip_info *info = conv->chip_info;
0297     struct ad9467_state *st = adi_axi_adc_conv_priv(conv);
0298     unsigned int scale_val[2];
0299     unsigned int i;
0300
0301     if (val != 0)
0302         return -EINVAL;
0303
0304     for (i = 0; i < info->num_scales; i++) {
0305         __ad9467_get_scale(conv, i, &scale_val[0], &scale_val[1]);
0306         if (scale_val[0] != val || scale_val[1] != val2)
0307             continue;
0308
0309         ad9467_spi_write(st->spi, AN877_ADC_REG_VREF,
0310                  info->scale_table[i][1]);
0311         ad9467_spi_write(st->spi, AN877_ADC_REG_TRANSFER,
0312                  AN877_ADC_TRANSFER_SYNC);
0313         return 0;
0314     }
0315
0316     return -EINVAL;
0317 }
0318
0319 static int ad9467_read_raw(struct adi_axi_adc_conv *conv,
0320                struct iio_chan_spec const *chan,
0321                int *val, int *val2, long m)
0322 {
0323     struct ad9467_state *st = adi_axi_adc_conv_priv(conv);
0324
0325     switch (m) {
0326     case IIO_CHAN_INFO_SCALE:
0327         return ad9467_get_scale(conv, val, val2);
0328     case IIO_CHAN_INFO_SAMP_FREQ:
0329         *val = clk_get_rate(st->clk);
0330
0331         return IIO_VAL_INT;
0332     default:
0333         return -EINVAL;
0334     }
0335 }
0336
0337 static int ad9467_write_raw(struct adi_axi_adc_conv *conv,
0338                 struct iio_chan_spec const *chan,
0339                 int val, int val2, long mask)
0340 {
0341     const struct adi_axi_adc_chip_info *info = conv->chip_info;
0342     struct ad9467_state *st = adi_axi_adc_conv_priv(conv);
0343     long r_clk;
0344
0345     switch (mask) {
0346     case IIO_CHAN_INFO_SCALE:
0347         return ad9467_set_scale(conv, val, val2);
0348     case IIO_CHAN_INFO_SAMP_FREQ:
0349         r_clk = clk_round_rate(st->clk, val);
0350         if (r_clk < 0 || r_clk > info->max_rate) {
0351             dev_warn(&st->spi->dev,
0352                  "Error setting ADC sample rate %ld", r_clk);
0353             return -EINVAL;
0354         }
0355
0356         return clk_set_rate(st->clk, r_clk);
0357     default:
0358         return -EINVAL;
0359     }
0360 }
0361
0362 static int ad9467_outputmode_set(struct spi_device *spi, unsigned int mode)
0363 {
0364     int ret;
0365
0366     ret = ad9467_spi_write(spi, AN877_ADC_REG_OUTPUT_MODE, mode);
0367     if (ret < 0)
0368         return ret;
0369
0370     return ad9467_spi_write(spi, AN877_ADC_REG_TRANSFER,
0371                 AN877_ADC_TRANSFER_SYNC);
0372 }
0373
0374 static int ad9467_preenable_setup(struct adi_axi_adc_conv *conv)
0375 {
0376     struct ad9467_state *st = adi_axi_adc_conv_priv(conv);
0377
0378     return ad9467_outputmode_set(st->spi, st->output_mode);
0379 }
0380
0381 static void ad9467_clk_disable(void *data)
0382 {
0383     struct ad9467_state *st = data;
0384
0385     clk_disable_unprepare(st->clk);
0386 }
0387
0388 static int ad9467_probe(struct spi_device *spi)
0389 {
0390     const struct ad9467_chip_info *info;
0391     struct adi_axi_adc_conv *conv;
0392     struct ad9467_state *st;
0393     unsigned int id;
0394     int ret;
0395
0396     info = of_device_get_match_data(&spi->dev);
0397     if (!info)
0398         return -ENODEV;
0399
0400     conv = devm_adi_axi_adc_conv_register(&spi->dev, sizeof(*st));
0401     if (IS_ERR(conv))
0402         return PTR_ERR(conv);
0403
0404     st = adi_axi_adc_conv_priv(conv);
0405     st->spi = spi;
0406
0407     st->clk = devm_clk_get(&spi->dev, "adc-clk");
0408     if (IS_ERR(st->clk))
0409         return PTR_ERR(st->clk);
0410
0411     ret = clk_prepare_enable(st->clk);
0412     if (ret < 0)
0413         return ret;
0414
0415     ret = devm_add_action_or_reset(&spi->dev, ad9467_clk_disable, st);
0416     if (ret)
0417         return ret;
0418
0419     st->pwrdown_gpio = devm_gpiod_get_optional(&spi->dev, "powerdown",
0420                            GPIOD_OUT_LOW);
0421     if (IS_ERR(st->pwrdown_gpio))
0422         return PTR_ERR(st->pwrdown_gpio);
0423
0424     st->reset_gpio = devm_gpiod_get_optional(&spi->dev, "reset",
0425                          GPIOD_OUT_LOW);
0426     if (IS_ERR(st->reset_gpio))
0427         return PTR_ERR(st->reset_gpio);
0428
0429     if (st->reset_gpio) {
0430         udelay(1);
0431         ret = gpiod_direction_output(st->reset_gpio, 1);
0432         if (ret)
0433             return ret;
0434         mdelay(10);
0435     }
0436
0437     conv->chip_info = &info->axi_adc_info;
0438
0439     id = ad9467_spi_read(spi, AN877_ADC_REG_CHIP_ID);
0440     if (id != conv->chip_info->id) {
0441         dev_err(&spi->dev, "Mismatch CHIP_ID, got 0x%X, expected 0x%X\n",
0442             id, conv->chip_info->id);
0443         return -ENODEV;
0444     }
0445
0446     conv->reg_access = ad9467_reg_access;
0447     conv->write_raw = ad9467_write_raw;
0448     conv->read_raw = ad9467_read_raw;
0449     conv->preenable_setup = ad9467_preenable_setup;
0450
0451     st->output_mode = info->default_output_mode |
0452               AN877_ADC_OUTPUT_MODE_TWOS_COMPLEMENT;
0453
0454     return 0;
0455 }
0456
0457 static const struct of_device_id ad9467_of_match[] = {
0458     { .compatible = "adi,ad9265", .data = &ad9467_chip_tbl[ID_AD9265], },
0459     { .compatible = "adi,ad9434", .data = &ad9467_chip_tbl[ID_AD9434], },
0460     { .compatible = "adi,ad9467", .data = &ad9467_chip_tbl[ID_AD9467], },
0461     {}
0462 };
0463 MODULE_DEVICE_TABLE(of, ad9467_of_match);
0464
0465 static struct spi_driver ad9467_driver = {
0466     .driver = {
0467         .name = "ad9467",
0468         .of_match_table = ad9467_of_match,
0469     },
0470     .probe = ad9467_probe,
0471 };
0472 module_spi_driver(ad9467_driver);
0473
0474 MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>");
0475 MODULE_DESCRIPTION("Analog Devices AD9467 ADC driver");
0476 MODULE_LICENSE("GPL v2");
0477 MODULE_IMPORT_NS(IIO_ADI_AXI);