iio/adc/ad7949.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /* ad7949.c - Analog Devices ADC driver 14/16 bits 4/8 channels
0003  *
0004  * Copyright (C) 2018 CMC NV
0005  *
0006  * https://www.analog.com/media/en/technical-documentation/data-sheets/AD7949.pdf
0007  */
0008
0009 #include <linux/delay.h>
0010 #include <linux/iio/iio.h>
0011 #include <linux/module.h>
0012 #include <linux/regulator/consumer.h>
0013 #include <linux/spi/spi.h>
0014 #include <linux/bitfield.h>
0015
0016 #define AD7949_CFG_MASK_TOTAL       GENMASK(13, 0)
0017
0018 /* CFG: Configuration Update */
0019 #define AD7949_CFG_MASK_OVERWRITE   BIT(13)
0020
0021 /* INCC: Input Channel Configuration */
0022 #define AD7949_CFG_MASK_INCC        GENMASK(12, 10)
0023 #define AD7949_CFG_VAL_INCC_UNIPOLAR_GND    7
0024 #define AD7949_CFG_VAL_INCC_UNIPOLAR_COMM   6
0025 #define AD7949_CFG_VAL_INCC_UNIPOLAR_DIFF   4
0026 #define AD7949_CFG_VAL_INCC_TEMP        3
0027 #define AD7949_CFG_VAL_INCC_BIPOLAR     2
0028 #define AD7949_CFG_VAL_INCC_BIPOLAR_DIFF    0
0029
0030 /* INX: Input channel Selection in a binary fashion */
0031 #define AD7949_CFG_MASK_INX     GENMASK(9, 7)
0032
0033 /* BW: select bandwidth for low-pass filter. Full or Quarter */
0034 #define AD7949_CFG_MASK_BW_FULL     BIT(6)
0035
0036 /* REF: reference/buffer selection */
0037 #define AD7949_CFG_MASK_REF     GENMASK(5, 3)
0038 #define AD7949_CFG_VAL_REF_EXT_TEMP_BUF     3
0039 #define AD7949_CFG_VAL_REF_EXT_TEMP     2
0040 #define AD7949_CFG_VAL_REF_INT_4096     1
0041 #define AD7949_CFG_VAL_REF_INT_2500     0
0042 #define AD7949_CFG_VAL_REF_EXTERNAL     BIT(1)
0043
0044 /* SEQ: channel sequencer. Allows for scanning channels */
0045 #define AD7949_CFG_MASK_SEQ     GENMASK(2, 1)
0046
0047 /* RB: Read back the CFG register */
0048 #define AD7949_CFG_MASK_RBN     BIT(0)
0049
0050 enum {
0051     ID_AD7949 = 0,
0052     ID_AD7682,
0053     ID_AD7689,
0054 };
0055
0056 struct ad7949_adc_spec {
0057     u8 num_channels;
0058     u8 resolution;
0059 };
0060
0061 static const struct ad7949_adc_spec ad7949_adc_spec[] = {
0062     [ID_AD7949] = { .num_channels = 8, .resolution = 14 },
0063     [ID_AD7682] = { .num_channels = 4, .resolution = 16 },
0064     [ID_AD7689] = { .num_channels = 8, .resolution = 16 },
0065 };
0066
0067 /**
0068  * struct ad7949_adc_chip - AD ADC chip
0069  * @lock: protects write sequences
0070  * @vref: regulator generating Vref
0071  * @indio_dev: reference to iio structure
0072  * @spi: reference to spi structure
0073  * @refsel: reference selection
0074  * @resolution: resolution of the chip
0075  * @cfg: copy of the configuration register
0076  * @current_channel: current channel in use
0077  * @buffer: buffer to send / receive data to / from device
0078  * @buf8b: be16 buffer to exchange data with the device in 8-bit transfers
0079  */
0080 struct ad7949_adc_chip {
0081     struct mutex lock;
0082     struct regulator *vref;
0083     struct iio_dev *indio_dev;
0084     struct spi_device *spi;
0085     u32 refsel;
0086     u8 resolution;
0087     u16 cfg;
0088     unsigned int current_channel;
0089     u16 buffer __aligned(IIO_DMA_MINALIGN);
0090     __be16 buf8b;
0091 };
0092
0093 static int ad7949_spi_write_cfg(struct ad7949_adc_chip *ad7949_adc, u16 val,
0094                 u16 mask)
0095 {
0096     int ret;
0097
0098     ad7949_adc->cfg = (val & mask) | (ad7949_adc->cfg & ~mask);
0099
0100     switch (ad7949_adc->spi->bits_per_word) {
0101     case 16:
0102         ad7949_adc->buffer = ad7949_adc->cfg << 2;
0103         ret = spi_write(ad7949_adc->spi, &ad7949_adc->buffer, 2);
0104         break;
0105     case 14:
0106         ad7949_adc->buffer = ad7949_adc->cfg;
0107         ret = spi_write(ad7949_adc->spi, &ad7949_adc->buffer, 2);
0108         break;
0109     case 8:
0110         /* Here, type is big endian as it must be sent in two transfers */
0111         ad7949_adc->buf8b = cpu_to_be16(ad7949_adc->cfg << 2);
0112         ret = spi_write(ad7949_adc->spi, &ad7949_adc->buf8b, 2);
0113         break;
0114     default:
0115         dev_err(&ad7949_adc->indio_dev->dev, "unsupported BPW\n");
0116         return -EINVAL;
0117     }
0118
0119     /*
0120      * This delay is to avoid a new request before the required time to
0121      * send a new command to the device
0122      */
0123     udelay(2);
0124     return ret;
0125 }
0126
0127 static int ad7949_spi_read_channel(struct ad7949_adc_chip *ad7949_adc, int *val,
0128                    unsigned int channel)
0129 {
0130     int ret;
0131     int i;
0132
0133     /*
0134      * 1: write CFG for sample N and read old data (sample N-2)
0135      * 2: if CFG was not changed since sample N-1 then we'll get good data
0136      *    at the next xfer, so we bail out now, otherwise we write something
0137      *    and we read garbage (sample N-1 configuration).
0138      */
0139     for (i = 0; i < 2; i++) {
0140         ret = ad7949_spi_write_cfg(ad7949_adc,
0141                        FIELD_PREP(AD7949_CFG_MASK_INX, channel),
0142                        AD7949_CFG_MASK_INX);
0143         if (ret)
0144             return ret;
0145         if (channel == ad7949_adc->current_channel)
0146             break;
0147     }
0148
0149     /* 3: write something and read actual data */
0150     if (ad7949_adc->spi->bits_per_word == 8)
0151         ret = spi_read(ad7949_adc->spi, &ad7949_adc->buf8b, 2);
0152     else
0153         ret = spi_read(ad7949_adc->spi, &ad7949_adc->buffer, 2);
0154
0155     if (ret)
0156         return ret;
0157
0158     /*
0159      * This delay is to avoid a new request before the required time to
0160      * send a new command to the device
0161      */
0162     udelay(2);
0163
0164     ad7949_adc->current_channel = channel;
0165
0166     switch (ad7949_adc->spi->bits_per_word) {
0167     case 16:
0168         *val = ad7949_adc->buffer;
0169         /* Shift-out padding bits */
0170         *val >>= 16 - ad7949_adc->resolution;
0171         break;
0172     case 14:
0173         *val = ad7949_adc->buffer & GENMASK(13, 0);
0174         break;
0175     case 8:
0176         /* Here, type is big endian as data was sent in two transfers */
0177         *val = be16_to_cpu(ad7949_adc->buf8b);
0178         /* Shift-out padding bits */
0179         *val >>= 16 - ad7949_adc->resolution;
0180         break;
0181     default:
0182         dev_err(&ad7949_adc->indio_dev->dev, "unsupported BPW\n");
0183         return -EINVAL;
0184     }
0185
0186     return 0;
0187 }
0188
0189 #define AD7949_ADC_CHANNEL(chan) {              \
0190     .type = IIO_VOLTAGE,                    \
0191     .indexed = 1,                       \
0192     .channel = (chan),                  \
0193     .info_mask_separate = BIT(IIO_CHAN_INFO_RAW),       \
0194     .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),   \
0195 }
0196
0197 static const struct iio_chan_spec ad7949_adc_channels[] = {
0198     AD7949_ADC_CHANNEL(0),
0199     AD7949_ADC_CHANNEL(1),
0200     AD7949_ADC_CHANNEL(2),
0201     AD7949_ADC_CHANNEL(3),
0202     AD7949_ADC_CHANNEL(4),
0203     AD7949_ADC_CHANNEL(5),
0204     AD7949_ADC_CHANNEL(6),
0205     AD7949_ADC_CHANNEL(7),
0206 };
0207
0208 static int ad7949_spi_read_raw(struct iio_dev *indio_dev,
0209                struct iio_chan_spec const *chan,
0210                int *val, int *val2, long mask)
0211 {
0212     struct ad7949_adc_chip *ad7949_adc = iio_priv(indio_dev);
0213     int ret;
0214
0215     if (!val)
0216         return -EINVAL;
0217
0218     switch (mask) {
0219     case IIO_CHAN_INFO_RAW:
0220         mutex_lock(&ad7949_adc->lock);
0221         ret = ad7949_spi_read_channel(ad7949_adc, val, chan->channel);
0222         mutex_unlock(&ad7949_adc->lock);
0223
0224         if (ret < 0)
0225             return ret;
0226
0227         return IIO_VAL_INT;
0228
0229     case IIO_CHAN_INFO_SCALE:
0230         switch (ad7949_adc->refsel) {
0231         case AD7949_CFG_VAL_REF_INT_2500:
0232             *val = 2500;
0233             break;
0234         case AD7949_CFG_VAL_REF_INT_4096:
0235             *val = 4096;
0236             break;
0237         case AD7949_CFG_VAL_REF_EXT_TEMP:
0238         case AD7949_CFG_VAL_REF_EXT_TEMP_BUF:
0239             ret = regulator_get_voltage(ad7949_adc->vref);
0240             if (ret < 0)
0241                 return ret;
0242
0243             /* convert value back to mV */
0244             *val = ret / 1000;
0245             break;
0246         }
0247
0248         *val2 = (1 << ad7949_adc->resolution) - 1;
0249         return IIO_VAL_FRACTIONAL;
0250     }
0251
0252     return -EINVAL;
0253 }
0254
0255 static int ad7949_spi_reg_access(struct iio_dev *indio_dev,
0256             unsigned int reg, unsigned int writeval,
0257             unsigned int *readval)
0258 {
0259     struct ad7949_adc_chip *ad7949_adc = iio_priv(indio_dev);
0260     int ret = 0;
0261
0262     if (readval)
0263         *readval = ad7949_adc->cfg;
0264     else
0265         ret = ad7949_spi_write_cfg(ad7949_adc, writeval,
0266                        AD7949_CFG_MASK_TOTAL);
0267
0268     return ret;
0269 }
0270
0271 static const struct iio_info ad7949_spi_info = {
0272     .read_raw = ad7949_spi_read_raw,
0273     .debugfs_reg_access = ad7949_spi_reg_access,
0274 };
0275
0276 static int ad7949_spi_init(struct ad7949_adc_chip *ad7949_adc)
0277 {
0278     int ret;
0279     int val;
0280     u16 cfg;
0281
0282     ad7949_adc->current_channel = 0;
0283
0284     cfg = FIELD_PREP(AD7949_CFG_MASK_OVERWRITE, 1) |
0285         FIELD_PREP(AD7949_CFG_MASK_INCC, AD7949_CFG_VAL_INCC_UNIPOLAR_GND) |
0286         FIELD_PREP(AD7949_CFG_MASK_INX, ad7949_adc->current_channel) |
0287         FIELD_PREP(AD7949_CFG_MASK_BW_FULL, 1) |
0288         FIELD_PREP(AD7949_CFG_MASK_REF, ad7949_adc->refsel) |
0289         FIELD_PREP(AD7949_CFG_MASK_SEQ, 0x0) |
0290         FIELD_PREP(AD7949_CFG_MASK_RBN, 1);
0291
0292     ret = ad7949_spi_write_cfg(ad7949_adc, cfg, AD7949_CFG_MASK_TOTAL);
0293
0294     /*
0295      * Do two dummy conversions to apply the first configuration setting.
0296      * Required only after the start up of the device.
0297      */
0298     ad7949_spi_read_channel(ad7949_adc, &val, ad7949_adc->current_channel);
0299     ad7949_spi_read_channel(ad7949_adc, &val, ad7949_adc->current_channel);
0300
0301     return ret;
0302 }
0303
0304 static void ad7949_disable_reg(void *reg)
0305 {
0306     regulator_disable(reg);
0307 }
0308
0309 static int ad7949_spi_probe(struct spi_device *spi)
0310 {
0311     u32 spi_ctrl_mask = spi->controller->bits_per_word_mask;
0312     struct device *dev = &spi->dev;
0313     const struct ad7949_adc_spec *spec;
0314     struct ad7949_adc_chip *ad7949_adc;
0315     struct iio_dev *indio_dev;
0316     u32 tmp;
0317     int ret;
0318
0319     indio_dev = devm_iio_device_alloc(dev, sizeof(*ad7949_adc));
0320     if (!indio_dev) {
0321         dev_err(dev, "can not allocate iio device\n");
0322         return -ENOMEM;
0323     }
0324
0325     indio_dev->info = &ad7949_spi_info;
0326     indio_dev->name = spi_get_device_id(spi)->name;
0327     indio_dev->modes = INDIO_DIRECT_MODE;
0328     indio_dev->channels = ad7949_adc_channels;
0329     spi_set_drvdata(spi, indio_dev);
0330
0331     ad7949_adc = iio_priv(indio_dev);
0332     ad7949_adc->indio_dev = indio_dev;
0333     ad7949_adc->spi = spi;
0334
0335     spec = &ad7949_adc_spec[spi_get_device_id(spi)->driver_data];
0336     indio_dev->num_channels = spec->num_channels;
0337     ad7949_adc->resolution = spec->resolution;
0338
0339     /* Set SPI bits per word */
0340     if (spi_ctrl_mask & SPI_BPW_MASK(ad7949_adc->resolution)) {
0341         spi->bits_per_word = ad7949_adc->resolution;
0342     } else if (spi_ctrl_mask == SPI_BPW_MASK(16)) {
0343         spi->bits_per_word = 16;
0344     } else if (spi_ctrl_mask == SPI_BPW_MASK(8)) {
0345         spi->bits_per_word = 8;
0346     } else {
0347         dev_err(dev, "unable to find common BPW with spi controller\n");
0348         return -EINVAL;
0349     }
0350
0351     /* Setup internal voltage reference */
0352     tmp = 4096000;
0353     device_property_read_u32(dev, "adi,internal-ref-microvolt", &tmp);
0354
0355     switch (tmp) {
0356     case 2500000:
0357         ad7949_adc->refsel = AD7949_CFG_VAL_REF_INT_2500;
0358         break;
0359     case 4096000:
0360         ad7949_adc->refsel = AD7949_CFG_VAL_REF_INT_4096;
0361         break;
0362     default:
0363         dev_err(dev, "unsupported internal voltage reference\n");
0364         return -EINVAL;
0365     }
0366
0367     /* Setup external voltage reference, buffered? */
0368     ad7949_adc->vref = devm_regulator_get_optional(dev, "vrefin");
0369     if (IS_ERR(ad7949_adc->vref)) {
0370         ret = PTR_ERR(ad7949_adc->vref);
0371         if (ret != -ENODEV)
0372             return ret;
0373         /* unbuffered? */
0374         ad7949_adc->vref = devm_regulator_get_optional(dev, "vref");
0375         if (IS_ERR(ad7949_adc->vref)) {
0376             ret = PTR_ERR(ad7949_adc->vref);
0377             if (ret != -ENODEV)
0378                 return ret;
0379         } else {
0380             ad7949_adc->refsel = AD7949_CFG_VAL_REF_EXT_TEMP;
0381         }
0382     } else {
0383         ad7949_adc->refsel = AD7949_CFG_VAL_REF_EXT_TEMP_BUF;
0384     }
0385
0386     if (ad7949_adc->refsel & AD7949_CFG_VAL_REF_EXTERNAL) {
0387         ret = regulator_enable(ad7949_adc->vref);
0388         if (ret < 0) {
0389             dev_err(dev, "fail to enable regulator\n");
0390             return ret;
0391         }
0392
0393         ret = devm_add_action_or_reset(dev, ad7949_disable_reg,
0394                            ad7949_adc->vref);
0395         if (ret)
0396             return ret;
0397     }
0398
0399     mutex_init(&ad7949_adc->lock);
0400
0401     ret = ad7949_spi_init(ad7949_adc);
0402     if (ret) {
0403         dev_err(dev, "fail to init this device: %d\n", ret);
0404         return ret;
0405     }
0406
0407     ret = devm_iio_device_register(dev, indio_dev);
0408     if (ret)
0409         dev_err(dev, "fail to register iio device: %d\n", ret);
0410
0411     return ret;
0412 }
0413
0414 static const struct of_device_id ad7949_spi_of_id[] = {
0415     { .compatible = "adi,ad7949" },
0416     { .compatible = "adi,ad7682" },
0417     { .compatible = "adi,ad7689" },
0418     { }
0419 };
0420 MODULE_DEVICE_TABLE(of, ad7949_spi_of_id);
0421
0422 static const struct spi_device_id ad7949_spi_id[] = {
0423     { "ad7949", ID_AD7949  },
0424     { "ad7682", ID_AD7682 },
0425     { "ad7689", ID_AD7689 },
0426     { }
0427 };
0428 MODULE_DEVICE_TABLE(spi, ad7949_spi_id);
0429
0430 static struct spi_driver ad7949_spi_driver = {
0431     .driver = {
0432         .name       = "ad7949",
0433         .of_match_table = ad7949_spi_of_id,
0434     },
0435     .probe    = ad7949_spi_probe,
0436     .id_table = ad7949_spi_id,
0437 };
0438 module_spi_driver(ad7949_spi_driver);
0439
0440 MODULE_AUTHOR("Charles-Antoine Couret <charles-antoine.couret@essensium.com>");
0441 MODULE_DESCRIPTION("Analog Devices 14/16-bit 8-channel ADC driver");
0442 MODULE_LICENSE("GPL v2");