iio/adc/ad7923.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * AD7904/AD7914/AD7923/AD7924/AD7908/AD7918/AD7928 SPI ADC driver
0004  *
0005  * Copyright 2011 Analog Devices Inc (from AD7923 Driver)
0006  * Copyright 2012 CS Systemes d'Information
0007  */
0008
0009 #include <linux/device.h>
0010 #include <linux/kernel.h>
0011 #include <linux/slab.h>
0012 #include <linux/sysfs.h>
0013 #include <linux/spi/spi.h>
0014 #include <linux/regulator/consumer.h>
0015 #include <linux/err.h>
0016 #include <linux/delay.h>
0017 #include <linux/module.h>
0018 #include <linux/interrupt.h>
0019
0020 #include <linux/iio/iio.h>
0021 #include <linux/iio/sysfs.h>
0022 #include <linux/iio/buffer.h>
0023 #include <linux/iio/trigger_consumer.h>
0024 #include <linux/iio/triggered_buffer.h>
0025
0026 #define AD7923_WRITE_CR     BIT(11)     /* write control register */
0027 #define AD7923_RANGE        BIT(1)      /* range to REFin */
0028 #define AD7923_CODING       BIT(0)      /* coding is straight binary */
0029 #define AD7923_PM_MODE_AS   (1)     /* auto shutdown */
0030 #define AD7923_PM_MODE_FS   (2)     /* full shutdown */
0031 #define AD7923_PM_MODE_OPS  (3)     /* normal operation */
0032 #define AD7923_SEQUENCE_OFF (0)     /* no sequence fonction */
0033 #define AD7923_SEQUENCE_PROTECT (2)     /* no interrupt write cycle */
0034 #define AD7923_SEQUENCE_ON  (3)     /* continuous sequence */
0035
0036
0037 #define AD7923_PM_MODE_WRITE(mode)  ((mode) << 4)    /* write mode */
0038 #define AD7923_CHANNEL_WRITE(channel)   ((channel) << 6) /* write channel */
0039 #define AD7923_SEQUENCE_WRITE(sequence) ((((sequence) & 1) << 3) \
0040                     + (((sequence) & 2) << 9))
0041                         /* write sequence fonction */
0042 /* left shift for CR : bit 11 transmit in first */
0043 #define AD7923_SHIFT_REGISTER   4
0044
0045 /* val = value, dec = left shift, bits = number of bits of the mask */
0046 #define EXTRACT(val, dec, bits)     (((val) >> (dec)) & ((1 << (bits)) - 1))
0047
0048 struct ad7923_state {
0049     struct spi_device       *spi;
0050     struct spi_transfer     ring_xfer[5];
0051     struct spi_transfer     scan_single_xfer[2];
0052     struct spi_message      ring_msg;
0053     struct spi_message      scan_single_msg;
0054
0055     struct regulator        *reg;
0056
0057     unsigned int            settings;
0058
0059     /*
0060      * DMA (thus cache coherency maintenance) may require the
0061      * transfer buffers to live in their own cache lines.
0062      * Ensure rx_buf can be directly used in iio_push_to_buffers_with_timetamp
0063      * Length = 8 channels + 4 extra for 8 byte timestamp
0064      */
0065     __be16              rx_buf[12] __aligned(IIO_DMA_MINALIGN);
0066     __be16              tx_buf[4];
0067 };
0068
0069 struct ad7923_chip_info {
0070     const struct iio_chan_spec *channels;
0071     unsigned int num_channels;
0072 };
0073
0074 enum ad7923_id {
0075     AD7904,
0076     AD7914,
0077     AD7924,
0078     AD7908,
0079     AD7918,
0080     AD7928
0081 };
0082
0083 #define AD7923_V_CHAN(index, bits)                  \
0084     {                               \
0085         .type = IIO_VOLTAGE,                    \
0086         .indexed = 1,                       \
0087         .channel = index,                   \
0088         .info_mask_separate = BIT(IIO_CHAN_INFO_RAW),       \
0089         .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),   \
0090         .address = index,                   \
0091         .scan_index = index,                    \
0092         .scan_type = {                      \
0093             .sign = 'u',                    \
0094             .realbits = (bits),             \
0095             .storagebits = 16,              \
0096             .endianness = IIO_BE,               \
0097         },                          \
0098     }
0099
0100 #define DECLARE_AD7923_CHANNELS(name, bits) \
0101 const struct iio_chan_spec name ## _channels[] = { \
0102     AD7923_V_CHAN(0, bits), \
0103     AD7923_V_CHAN(1, bits), \
0104     AD7923_V_CHAN(2, bits), \
0105     AD7923_V_CHAN(3, bits), \
0106     IIO_CHAN_SOFT_TIMESTAMP(4), \
0107 }
0108
0109 #define DECLARE_AD7908_CHANNELS(name, bits) \
0110 const struct iio_chan_spec name ## _channels[] = { \
0111     AD7923_V_CHAN(0, bits), \
0112     AD7923_V_CHAN(1, bits), \
0113     AD7923_V_CHAN(2, bits), \
0114     AD7923_V_CHAN(3, bits), \
0115     AD7923_V_CHAN(4, bits), \
0116     AD7923_V_CHAN(5, bits), \
0117     AD7923_V_CHAN(6, bits), \
0118     AD7923_V_CHAN(7, bits), \
0119     IIO_CHAN_SOFT_TIMESTAMP(8), \
0120 }
0121
0122 static DECLARE_AD7923_CHANNELS(ad7904, 8);
0123 static DECLARE_AD7923_CHANNELS(ad7914, 10);
0124 static DECLARE_AD7923_CHANNELS(ad7924, 12);
0125 static DECLARE_AD7908_CHANNELS(ad7908, 8);
0126 static DECLARE_AD7908_CHANNELS(ad7918, 10);
0127 static DECLARE_AD7908_CHANNELS(ad7928, 12);
0128
0129 static const struct ad7923_chip_info ad7923_chip_info[] = {
0130     [AD7904] = {
0131         .channels = ad7904_channels,
0132         .num_channels = ARRAY_SIZE(ad7904_channels),
0133     },
0134     [AD7914] = {
0135         .channels = ad7914_channels,
0136         .num_channels = ARRAY_SIZE(ad7914_channels),
0137     },
0138     [AD7924] = {
0139         .channels = ad7924_channels,
0140         .num_channels = ARRAY_SIZE(ad7924_channels),
0141     },
0142     [AD7908] = {
0143         .channels = ad7908_channels,
0144         .num_channels = ARRAY_SIZE(ad7908_channels),
0145     },
0146     [AD7918] = {
0147         .channels = ad7918_channels,
0148         .num_channels = ARRAY_SIZE(ad7918_channels),
0149     },
0150     [AD7928] = {
0151         .channels = ad7928_channels,
0152         .num_channels = ARRAY_SIZE(ad7928_channels),
0153     },
0154 };
0155
0156 /*
0157  * ad7923_update_scan_mode() setup the spi transfer buffer for the new scan mask
0158  */
0159 static int ad7923_update_scan_mode(struct iio_dev *indio_dev,
0160                    const unsigned long *active_scan_mask)
0161 {
0162     struct ad7923_state *st = iio_priv(indio_dev);
0163     int i, cmd, len;
0164
0165     len = 0;
0166     /*
0167      * For this driver the last channel is always the software timestamp so
0168      * skip that one.
0169      */
0170     for_each_set_bit(i, active_scan_mask, indio_dev->num_channels - 1) {
0171         cmd = AD7923_WRITE_CR | AD7923_CHANNEL_WRITE(i) |
0172             AD7923_SEQUENCE_WRITE(AD7923_SEQUENCE_OFF) |
0173             st->settings;
0174         cmd <<= AD7923_SHIFT_REGISTER;
0175         st->tx_buf[len++] = cpu_to_be16(cmd);
0176     }
0177     /* build spi ring message */
0178     st->ring_xfer[0].tx_buf = &st->tx_buf[0];
0179     st->ring_xfer[0].len = len;
0180     st->ring_xfer[0].cs_change = 1;
0181
0182     spi_message_init(&st->ring_msg);
0183     spi_message_add_tail(&st->ring_xfer[0], &st->ring_msg);
0184
0185     for (i = 0; i < len; i++) {
0186         st->ring_xfer[i + 1].rx_buf = &st->rx_buf[i];
0187         st->ring_xfer[i + 1].len = 2;
0188         st->ring_xfer[i + 1].cs_change = 1;
0189         spi_message_add_tail(&st->ring_xfer[i + 1], &st->ring_msg);
0190     }
0191     /* make sure last transfer cs_change is not set */
0192     st->ring_xfer[i + 1].cs_change = 0;
0193
0194     return 0;
0195 }
0196
0197 static irqreturn_t ad7923_trigger_handler(int irq, void *p)
0198 {
0199     struct iio_poll_func *pf = p;
0200     struct iio_dev *indio_dev = pf->indio_dev;
0201     struct ad7923_state *st = iio_priv(indio_dev);
0202     int b_sent;
0203
0204     b_sent = spi_sync(st->spi, &st->ring_msg);
0205     if (b_sent)
0206         goto done;
0207
0208     iio_push_to_buffers_with_timestamp(indio_dev, st->rx_buf,
0209                        iio_get_time_ns(indio_dev));
0210
0211 done:
0212     iio_trigger_notify_done(indio_dev->trig);
0213
0214     return IRQ_HANDLED;
0215 }
0216
0217 static int ad7923_scan_direct(struct ad7923_state *st, unsigned int ch)
0218 {
0219     int ret, cmd;
0220
0221     cmd = AD7923_WRITE_CR | AD7923_CHANNEL_WRITE(ch) |
0222         AD7923_SEQUENCE_WRITE(AD7923_SEQUENCE_OFF) |
0223         st->settings;
0224     cmd <<= AD7923_SHIFT_REGISTER;
0225     st->tx_buf[0] = cpu_to_be16(cmd);
0226
0227     ret = spi_sync(st->spi, &st->scan_single_msg);
0228     if (ret)
0229         return ret;
0230
0231     return be16_to_cpu(st->rx_buf[0]);
0232 }
0233
0234 static int ad7923_get_range(struct ad7923_state *st)
0235 {
0236     int vref;
0237
0238     vref = regulator_get_voltage(st->reg);
0239     if (vref < 0)
0240         return vref;
0241
0242     vref /= 1000;
0243
0244     if (!(st->settings & AD7923_RANGE))
0245         vref *= 2;
0246
0247     return vref;
0248 }
0249
0250 static int ad7923_read_raw(struct iio_dev *indio_dev,
0251                struct iio_chan_spec const *chan,
0252                int *val,
0253                int *val2,
0254                long m)
0255 {
0256     int ret;
0257     struct ad7923_state *st = iio_priv(indio_dev);
0258
0259     switch (m) {
0260     case IIO_CHAN_INFO_RAW:
0261         ret = iio_device_claim_direct_mode(indio_dev);
0262         if (ret)
0263             return ret;
0264         ret = ad7923_scan_direct(st, chan->address);
0265         iio_device_release_direct_mode(indio_dev);
0266
0267         if (ret < 0)
0268             return ret;
0269
0270         if (chan->address == EXTRACT(ret, 12, 4))
0271             *val = EXTRACT(ret, 0, 12);
0272         else
0273             return -EIO;
0274
0275         return IIO_VAL_INT;
0276     case IIO_CHAN_INFO_SCALE:
0277         ret = ad7923_get_range(st);
0278         if (ret < 0)
0279             return ret;
0280         *val = ret;
0281         *val2 = chan->scan_type.realbits;
0282         return IIO_VAL_FRACTIONAL_LOG2;
0283     }
0284     return -EINVAL;
0285 }
0286
0287 static const struct iio_info ad7923_info = {
0288     .read_raw = &ad7923_read_raw,
0289     .update_scan_mode = ad7923_update_scan_mode,
0290 };
0291
0292 static void ad7923_regulator_disable(void *data)
0293 {
0294     struct ad7923_state *st = data;
0295
0296     regulator_disable(st->reg);
0297 }
0298
0299 static int ad7923_probe(struct spi_device *spi)
0300 {
0301     struct ad7923_state *st;
0302     struct iio_dev *indio_dev;
0303     const struct ad7923_chip_info *info;
0304     int ret;
0305
0306     indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
0307     if (!indio_dev)
0308         return -ENOMEM;
0309
0310     st = iio_priv(indio_dev);
0311
0312     st->spi = spi;
0313     st->settings = AD7923_CODING | AD7923_RANGE |
0314             AD7923_PM_MODE_WRITE(AD7923_PM_MODE_OPS);
0315
0316     info = &ad7923_chip_info[spi_get_device_id(spi)->driver_data];
0317
0318     indio_dev->name = spi_get_device_id(spi)->name;
0319     indio_dev->modes = INDIO_DIRECT_MODE;
0320     indio_dev->channels = info->channels;
0321     indio_dev->num_channels = info->num_channels;
0322     indio_dev->info = &ad7923_info;
0323
0324     /* Setup default message */
0325
0326     st->scan_single_xfer[0].tx_buf = &st->tx_buf[0];
0327     st->scan_single_xfer[0].len = 2;
0328     st->scan_single_xfer[0].cs_change = 1;
0329     st->scan_single_xfer[1].rx_buf = &st->rx_buf[0];
0330     st->scan_single_xfer[1].len = 2;
0331
0332     spi_message_init(&st->scan_single_msg);
0333     spi_message_add_tail(&st->scan_single_xfer[0], &st->scan_single_msg);
0334     spi_message_add_tail(&st->scan_single_xfer[1], &st->scan_single_msg);
0335
0336     st->reg = devm_regulator_get(&spi->dev, "refin");
0337     if (IS_ERR(st->reg))
0338         return PTR_ERR(st->reg);
0339
0340     ret = regulator_enable(st->reg);
0341     if (ret)
0342         return ret;
0343
0344     ret = devm_add_action_or_reset(&spi->dev, ad7923_regulator_disable, st);
0345     if (ret)
0346         return ret;
0347
0348     ret = devm_iio_triggered_buffer_setup(&spi->dev, indio_dev, NULL,
0349                           &ad7923_trigger_handler, NULL);
0350     if (ret)
0351         return ret;
0352
0353     return devm_iio_device_register(&spi->dev, indio_dev);
0354 }
0355
0356 static const struct spi_device_id ad7923_id[] = {
0357     {"ad7904", AD7904},
0358     {"ad7914", AD7914},
0359     {"ad7923", AD7924},
0360     {"ad7924", AD7924},
0361     {"ad7908", AD7908},
0362     {"ad7918", AD7918},
0363     {"ad7928", AD7928},
0364     {}
0365 };
0366 MODULE_DEVICE_TABLE(spi, ad7923_id);
0367
0368 static const struct of_device_id ad7923_of_match[] = {
0369     { .compatible = "adi,ad7904", },
0370     { .compatible = "adi,ad7914", },
0371     { .compatible = "adi,ad7923", },
0372     { .compatible = "adi,ad7924", },
0373     { .compatible = "adi,ad7908", },
0374     { .compatible = "adi,ad7918", },
0375     { .compatible = "adi,ad7928", },
0376     { },
0377 };
0378 MODULE_DEVICE_TABLE(of, ad7923_of_match);
0379
0380 static struct spi_driver ad7923_driver = {
0381     .driver = {
0382         .name   = "ad7923",
0383         .of_match_table = ad7923_of_match,
0384     },
0385     .probe      = ad7923_probe,
0386     .id_table   = ad7923_id,
0387 };
0388 module_spi_driver(ad7923_driver);
0389
0390 MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>");
0391 MODULE_AUTHOR("Patrick Vasseur <patrick.vasseur@c-s.fr>");
0392 MODULE_DESCRIPTION("Analog Devices AD7923 and similar ADC");
0393 MODULE_LICENSE("GPL v2");