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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * AD7785/AD7792/AD7793/AD7794/AD7795 SPI ADC driver
0004  *
0005  * Copyright 2011-2012 Analog Devices Inc.
0006  */
0007 
0008 #include <linux/interrupt.h>
0009 #include <linux/device.h>
0010 #include <linux/kernel.h>
0011 #include <linux/slab.h>
0012 #include <linux/sysfs.h>
0013 #include <linux/spi/spi.h>
0014 #include <linux/regulator/consumer.h>
0015 #include <linux/err.h>
0016 #include <linux/sched.h>
0017 #include <linux/delay.h>
0018 #include <linux/module.h>
0019 
0020 #include <linux/iio/iio.h>
0021 #include <linux/iio/sysfs.h>
0022 #include <linux/iio/buffer.h>
0023 #include <linux/iio/trigger.h>
0024 #include <linux/iio/trigger_consumer.h>
0025 #include <linux/iio/triggered_buffer.h>
0026 #include <linux/iio/adc/ad_sigma_delta.h>
0027 #include <linux/platform_data/ad7793.h>
0028 
0029 /* Registers */
0030 #define AD7793_REG_COMM     0 /* Communications Register (WO, 8-bit) */
0031 #define AD7793_REG_STAT     0 /* Status Register         (RO, 8-bit) */
0032 #define AD7793_REG_MODE     1 /* Mode Register       (RW, 16-bit */
0033 #define AD7793_REG_CONF     2 /* Configuration Register  (RW, 16-bit) */
0034 #define AD7793_REG_DATA     3 /* Data Register       (RO, 16-/24-bit) */
0035 #define AD7793_REG_ID       4 /* ID Register         (RO, 8-bit) */
0036 #define AD7793_REG_IO       5 /* IO Register         (RO, 8-bit) */
0037 #define AD7793_REG_OFFSET   6 /* Offset Register         (RW, 16-bit
0038                    * (AD7792)/24-bit (AD7793)) */
0039 #define AD7793_REG_FULLSALE 7 /* Full-Scale Register
0040                    * (RW, 16-bit (AD7792)/24-bit (AD7793)) */
0041 
0042 /* Communications Register Bit Designations (AD7793_REG_COMM) */
0043 #define AD7793_COMM_WEN     (1 << 7) /* Write Enable */
0044 #define AD7793_COMM_WRITE   (0 << 6) /* Write Operation */
0045 #define AD7793_COMM_READ    (1 << 6) /* Read Operation */
0046 #define AD7793_COMM_ADDR(x) (((x) & 0x7) << 3) /* Register Address */
0047 #define AD7793_COMM_CREAD   (1 << 2) /* Continuous Read of Data Register */
0048 
0049 /* Status Register Bit Designations (AD7793_REG_STAT) */
0050 #define AD7793_STAT_RDY     (1 << 7) /* Ready */
0051 #define AD7793_STAT_ERR     (1 << 6) /* Error (Overrange, Underrange) */
0052 #define AD7793_STAT_CH3     (1 << 2) /* Channel 3 */
0053 #define AD7793_STAT_CH2     (1 << 1) /* Channel 2 */
0054 #define AD7793_STAT_CH1     (1 << 0) /* Channel 1 */
0055 
0056 /* Mode Register Bit Designations (AD7793_REG_MODE) */
0057 #define AD7793_MODE_SEL(x)  (((x) & 0x7) << 13) /* Operation Mode Select */
0058 #define AD7793_MODE_SEL_MASK    (0x7 << 13) /* Operation Mode Select mask */
0059 #define AD7793_MODE_CLKSRC(x)   (((x) & 0x3) << 6) /* ADC Clock Source Select */
0060 #define AD7793_MODE_RATE(x) ((x) & 0xF) /* Filter Update Rate Select */
0061 
0062 #define AD7793_MODE_CONT        0 /* Continuous Conversion Mode */
0063 #define AD7793_MODE_SINGLE      1 /* Single Conversion Mode */
0064 #define AD7793_MODE_IDLE        2 /* Idle Mode */
0065 #define AD7793_MODE_PWRDN       3 /* Power-Down Mode */
0066 #define AD7793_MODE_CAL_INT_ZERO    4 /* Internal Zero-Scale Calibration */
0067 #define AD7793_MODE_CAL_INT_FULL    5 /* Internal Full-Scale Calibration */
0068 #define AD7793_MODE_CAL_SYS_ZERO    6 /* System Zero-Scale Calibration */
0069 #define AD7793_MODE_CAL_SYS_FULL    7 /* System Full-Scale Calibration */
0070 
0071 #define AD7793_CLK_INT      0 /* Internal 64 kHz Clock not
0072                    * available at the CLK pin */
0073 #define AD7793_CLK_INT_CO   1 /* Internal 64 kHz Clock available
0074                    * at the CLK pin */
0075 #define AD7793_CLK_EXT      2 /* External 64 kHz Clock */
0076 #define AD7793_CLK_EXT_DIV2 3 /* External Clock divided by 2 */
0077 
0078 /* Configuration Register Bit Designations (AD7793_REG_CONF) */
0079 #define AD7793_CONF_VBIAS(x)    (((x) & 0x3) << 14) /* Bias Voltage
0080                              * Generator Enable */
0081 #define AD7793_CONF_BO_EN   (1 << 13) /* Burnout Current Enable */
0082 #define AD7793_CONF_UNIPOLAR    (1 << 12) /* Unipolar/Bipolar Enable */
0083 #define AD7793_CONF_BOOST   (1 << 11) /* Boost Enable */
0084 #define AD7793_CONF_GAIN(x) (((x) & 0x7) << 8) /* Gain Select */
0085 #define AD7793_CONF_REFSEL(x)   ((x) << 6) /* INT/EXT Reference Select */
0086 #define AD7793_CONF_BUF     (1 << 4) /* Buffered Mode Enable */
0087 #define AD7793_CONF_CHAN(x) ((x) & 0xf) /* Channel select */
0088 #define AD7793_CONF_CHAN_MASK   0xf /* Channel select mask */
0089 
0090 #define AD7793_CH_AIN1P_AIN1M   0 /* AIN1(+) - AIN1(-) */
0091 #define AD7793_CH_AIN2P_AIN2M   1 /* AIN2(+) - AIN2(-) */
0092 #define AD7793_CH_AIN3P_AIN3M   2 /* AIN3(+) - AIN3(-) */
0093 #define AD7793_CH_AIN1M_AIN1M   3 /* AIN1(-) - AIN1(-) */
0094 #define AD7793_CH_TEMP      6 /* Temp Sensor */
0095 #define AD7793_CH_AVDD_MONITOR  7 /* AVDD Monitor */
0096 
0097 #define AD7795_CH_AIN4P_AIN4M   4 /* AIN4(+) - AIN4(-) */
0098 #define AD7795_CH_AIN5P_AIN5M   5 /* AIN5(+) - AIN5(-) */
0099 #define AD7795_CH_AIN6P_AIN6M   6 /* AIN6(+) - AIN6(-) */
0100 #define AD7795_CH_AIN1M_AIN1M   8 /* AIN1(-) - AIN1(-) */
0101 
0102 /* ID Register Bit Designations (AD7793_REG_ID) */
0103 #define AD7785_ID       0x3
0104 #define AD7792_ID       0xA
0105 #define AD7793_ID       0xB
0106 #define AD7794_ID       0xF
0107 #define AD7795_ID       0xF
0108 #define AD7796_ID       0xA
0109 #define AD7797_ID       0xB
0110 #define AD7798_ID       0x8
0111 #define AD7799_ID       0x9
0112 #define AD7793_ID_MASK      0xF
0113 
0114 /* IO (Excitation Current Sources) Register Bit Designations (AD7793_REG_IO) */
0115 #define AD7793_IO_IEXC1_IOUT1_IEXC2_IOUT2   0 /* IEXC1 connect to IOUT1,
0116                            * IEXC2 connect to IOUT2 */
0117 #define AD7793_IO_IEXC1_IOUT2_IEXC2_IOUT1   1 /* IEXC1 connect to IOUT2,
0118                            * IEXC2 connect to IOUT1 */
0119 #define AD7793_IO_IEXC1_IEXC2_IOUT1     2 /* Both current sources
0120                            * IEXC1,2 connect to IOUT1 */
0121 #define AD7793_IO_IEXC1_IEXC2_IOUT2     3 /* Both current sources
0122                            * IEXC1,2 connect to IOUT2 */
0123 
0124 #define AD7793_IO_IXCEN_10uA    (1 << 0) /* Excitation Current 10uA */
0125 #define AD7793_IO_IXCEN_210uA   (2 << 0) /* Excitation Current 210uA */
0126 #define AD7793_IO_IXCEN_1mA (3 << 0) /* Excitation Current 1mA */
0127 
0128 /* NOTE:
0129  * The AD7792/AD7793 features a dual use data out ready DOUT/RDY output.
0130  * In order to avoid contentions on the SPI bus, it's therefore necessary
0131  * to use spi bus locking.
0132  *
0133  * The DOUT/RDY output must also be wired to an interrupt capable GPIO.
0134  */
0135 
0136 #define AD7793_FLAG_HAS_CLKSEL      BIT(0)
0137 #define AD7793_FLAG_HAS_REFSEL      BIT(1)
0138 #define AD7793_FLAG_HAS_VBIAS       BIT(2)
0139 #define AD7793_HAS_EXITATION_CURRENT    BIT(3)
0140 #define AD7793_FLAG_HAS_GAIN        BIT(4)
0141 #define AD7793_FLAG_HAS_BUFFER      BIT(5)
0142 
0143 struct ad7793_chip_info {
0144     unsigned int id;
0145     const struct iio_chan_spec *channels;
0146     unsigned int num_channels;
0147     unsigned int flags;
0148 
0149     const struct iio_info *iio_info;
0150     const u16 *sample_freq_avail;
0151 };
0152 
0153 struct ad7793_state {
0154     const struct ad7793_chip_info   *chip_info;
0155     struct regulator        *reg;
0156     u16             int_vref_mv;
0157     u16             mode;
0158     u16             conf;
0159     u32             scale_avail[8][2];
0160 
0161     struct ad_sigma_delta       sd;
0162 
0163 };
0164 
0165 enum ad7793_supported_device_ids {
0166     ID_AD7785,
0167     ID_AD7792,
0168     ID_AD7793,
0169     ID_AD7794,
0170     ID_AD7795,
0171     ID_AD7796,
0172     ID_AD7797,
0173     ID_AD7798,
0174     ID_AD7799,
0175 };
0176 
0177 static struct ad7793_state *ad_sigma_delta_to_ad7793(struct ad_sigma_delta *sd)
0178 {
0179     return container_of(sd, struct ad7793_state, sd);
0180 }
0181 
0182 static int ad7793_set_channel(struct ad_sigma_delta *sd, unsigned int channel)
0183 {
0184     struct ad7793_state *st = ad_sigma_delta_to_ad7793(sd);
0185 
0186     st->conf &= ~AD7793_CONF_CHAN_MASK;
0187     st->conf |= AD7793_CONF_CHAN(channel);
0188 
0189     return ad_sd_write_reg(&st->sd, AD7793_REG_CONF, 2, st->conf);
0190 }
0191 
0192 static int ad7793_set_mode(struct ad_sigma_delta *sd,
0193                enum ad_sigma_delta_mode mode)
0194 {
0195     struct ad7793_state *st = ad_sigma_delta_to_ad7793(sd);
0196 
0197     st->mode &= ~AD7793_MODE_SEL_MASK;
0198     st->mode |= AD7793_MODE_SEL(mode);
0199 
0200     return ad_sd_write_reg(&st->sd, AD7793_REG_MODE, 2, st->mode);
0201 }
0202 
0203 static const struct ad_sigma_delta_info ad7793_sigma_delta_info = {
0204     .set_channel = ad7793_set_channel,
0205     .set_mode = ad7793_set_mode,
0206     .has_registers = true,
0207     .addr_shift = 3,
0208     .read_mask = BIT(6),
0209     .irq_flags = IRQF_TRIGGER_FALLING,
0210 };
0211 
0212 static const struct ad_sd_calib_data ad7793_calib_arr[6] = {
0213     {AD7793_MODE_CAL_INT_ZERO, AD7793_CH_AIN1P_AIN1M},
0214     {AD7793_MODE_CAL_INT_FULL, AD7793_CH_AIN1P_AIN1M},
0215     {AD7793_MODE_CAL_INT_ZERO, AD7793_CH_AIN2P_AIN2M},
0216     {AD7793_MODE_CAL_INT_FULL, AD7793_CH_AIN2P_AIN2M},
0217     {AD7793_MODE_CAL_INT_ZERO, AD7793_CH_AIN3P_AIN3M},
0218     {AD7793_MODE_CAL_INT_FULL, AD7793_CH_AIN3P_AIN3M}
0219 };
0220 
0221 static int ad7793_calibrate_all(struct ad7793_state *st)
0222 {
0223     return ad_sd_calibrate_all(&st->sd, ad7793_calib_arr,
0224                    ARRAY_SIZE(ad7793_calib_arr));
0225 }
0226 
0227 static int ad7793_check_platform_data(struct ad7793_state *st,
0228     const struct ad7793_platform_data *pdata)
0229 {
0230     if ((pdata->current_source_direction == AD7793_IEXEC1_IEXEC2_IOUT1 ||
0231         pdata->current_source_direction == AD7793_IEXEC1_IEXEC2_IOUT2) &&
0232         ((pdata->exitation_current != AD7793_IX_10uA) &&
0233         (pdata->exitation_current != AD7793_IX_210uA)))
0234         return -EINVAL;
0235 
0236     if (!(st->chip_info->flags & AD7793_FLAG_HAS_CLKSEL) &&
0237         pdata->clock_src != AD7793_CLK_SRC_INT)
0238         return -EINVAL;
0239 
0240     if (!(st->chip_info->flags & AD7793_FLAG_HAS_REFSEL) &&
0241         pdata->refsel != AD7793_REFSEL_REFIN1)
0242         return -EINVAL;
0243 
0244     if (!(st->chip_info->flags & AD7793_FLAG_HAS_VBIAS) &&
0245         pdata->bias_voltage != AD7793_BIAS_VOLTAGE_DISABLED)
0246         return -EINVAL;
0247 
0248     if (!(st->chip_info->flags & AD7793_HAS_EXITATION_CURRENT) &&
0249         pdata->exitation_current != AD7793_IX_DISABLED)
0250         return -EINVAL;
0251 
0252     return 0;
0253 }
0254 
0255 static int ad7793_setup(struct iio_dev *indio_dev,
0256     const struct ad7793_platform_data *pdata,
0257     unsigned int vref_mv)
0258 {
0259     struct ad7793_state *st = iio_priv(indio_dev);
0260     int i, ret;
0261     unsigned long long scale_uv;
0262     u32 id;
0263 
0264     ret = ad7793_check_platform_data(st, pdata);
0265     if (ret)
0266         return ret;
0267 
0268     /* reset the serial interface */
0269     ret = ad_sd_reset(&st->sd, 32);
0270     if (ret < 0)
0271         goto out;
0272     usleep_range(500, 2000); /* Wait for at least 500us */
0273 
0274     /* write/read test for device presence */
0275     ret = ad_sd_read_reg(&st->sd, AD7793_REG_ID, 1, &id);
0276     if (ret)
0277         goto out;
0278 
0279     id &= AD7793_ID_MASK;
0280 
0281     if (id != st->chip_info->id) {
0282         ret = -ENODEV;
0283         dev_err(&st->sd.spi->dev, "device ID query failed\n");
0284         goto out;
0285     }
0286 
0287     st->mode = AD7793_MODE_RATE(1);
0288     st->conf = 0;
0289 
0290     if (st->chip_info->flags & AD7793_FLAG_HAS_CLKSEL)
0291         st->mode |= AD7793_MODE_CLKSRC(pdata->clock_src);
0292     if (st->chip_info->flags & AD7793_FLAG_HAS_REFSEL)
0293         st->conf |= AD7793_CONF_REFSEL(pdata->refsel);
0294     if (st->chip_info->flags & AD7793_FLAG_HAS_VBIAS)
0295         st->conf |= AD7793_CONF_VBIAS(pdata->bias_voltage);
0296     if (pdata->buffered || !(st->chip_info->flags & AD7793_FLAG_HAS_BUFFER))
0297         st->conf |= AD7793_CONF_BUF;
0298     if (pdata->boost_enable &&
0299         (st->chip_info->flags & AD7793_FLAG_HAS_VBIAS))
0300         st->conf |= AD7793_CONF_BOOST;
0301     if (pdata->burnout_current)
0302         st->conf |= AD7793_CONF_BO_EN;
0303     if (pdata->unipolar)
0304         st->conf |= AD7793_CONF_UNIPOLAR;
0305 
0306     if (!(st->chip_info->flags & AD7793_FLAG_HAS_GAIN))
0307         st->conf |= AD7793_CONF_GAIN(7);
0308 
0309     ret = ad7793_set_mode(&st->sd, AD_SD_MODE_IDLE);
0310     if (ret)
0311         goto out;
0312 
0313     ret = ad7793_set_channel(&st->sd, 0);
0314     if (ret)
0315         goto out;
0316 
0317     if (st->chip_info->flags & AD7793_HAS_EXITATION_CURRENT) {
0318         ret = ad_sd_write_reg(&st->sd, AD7793_REG_IO, 1,
0319                 pdata->exitation_current |
0320                 (pdata->current_source_direction << 2));
0321         if (ret)
0322             goto out;
0323     }
0324 
0325     ret = ad7793_calibrate_all(st);
0326     if (ret)
0327         goto out;
0328 
0329     /* Populate available ADC input ranges */
0330     for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++) {
0331         scale_uv = ((u64)vref_mv * 100000000)
0332             >> (st->chip_info->channels[0].scan_type.realbits -
0333             (!!(st->conf & AD7793_CONF_UNIPOLAR) ? 0 : 1));
0334         scale_uv >>= i;
0335 
0336         st->scale_avail[i][1] = do_div(scale_uv, 100000000) * 10;
0337         st->scale_avail[i][0] = scale_uv;
0338     }
0339 
0340     return 0;
0341 out:
0342     dev_err(&st->sd.spi->dev, "setup failed\n");
0343     return ret;
0344 }
0345 
0346 static const u16 ad7793_sample_freq_avail[16] = {0, 470, 242, 123, 62, 50, 39,
0347                     33, 19, 17, 16, 12, 10, 8, 6, 4};
0348 
0349 static const u16 ad7797_sample_freq_avail[16] = {0, 0, 0, 123, 62, 50, 0,
0350                     33, 0, 17, 16, 12, 10, 8, 6, 4};
0351 
0352 static IIO_CONST_ATTR_SAMP_FREQ_AVAIL(
0353     "470 242 123 62 50 39 33 19 17 16 12 10 8 6 4");
0354 
0355 static IIO_CONST_ATTR_NAMED(sampling_frequency_available_ad7797,
0356     sampling_frequency_available, "123 62 50 33 17 16 12 10 8 6 4");
0357 
0358 static int ad7793_read_avail(struct iio_dev *indio_dev,
0359                  struct iio_chan_spec const *chan,
0360                  const int **vals, int *type, int *length,
0361                  long mask)
0362 {
0363     struct ad7793_state *st = iio_priv(indio_dev);
0364 
0365     switch (mask) {
0366     case IIO_CHAN_INFO_SCALE:
0367         *vals = (int *)st->scale_avail;
0368         *type = IIO_VAL_INT_PLUS_NANO;
0369         /* Values are stored in a 2D matrix  */
0370         *length = ARRAY_SIZE(st->scale_avail) * 2;
0371 
0372         return IIO_AVAIL_LIST;
0373     default:
0374         return -EINVAL;
0375     }
0376 }
0377 
0378 static struct attribute *ad7793_attributes[] = {
0379     &iio_const_attr_sampling_frequency_available.dev_attr.attr,
0380     NULL
0381 };
0382 
0383 static const struct attribute_group ad7793_attribute_group = {
0384     .attrs = ad7793_attributes,
0385 };
0386 
0387 static struct attribute *ad7797_attributes[] = {
0388     &iio_const_attr_sampling_frequency_available_ad7797.dev_attr.attr,
0389     NULL
0390 };
0391 
0392 static const struct attribute_group ad7797_attribute_group = {
0393     .attrs = ad7797_attributes,
0394 };
0395 
0396 static int ad7793_read_raw(struct iio_dev *indio_dev,
0397                struct iio_chan_spec const *chan,
0398                int *val,
0399                int *val2,
0400                long m)
0401 {
0402     struct ad7793_state *st = iio_priv(indio_dev);
0403     int ret;
0404     unsigned long long scale_uv;
0405     bool unipolar = !!(st->conf & AD7793_CONF_UNIPOLAR);
0406 
0407     switch (m) {
0408     case IIO_CHAN_INFO_RAW:
0409         ret = ad_sigma_delta_single_conversion(indio_dev, chan, val);
0410         if (ret < 0)
0411             return ret;
0412 
0413         return IIO_VAL_INT;
0414 
0415     case IIO_CHAN_INFO_SCALE:
0416         switch (chan->type) {
0417         case IIO_VOLTAGE:
0418             if (chan->differential) {
0419                 *val = st->
0420                     scale_avail[(st->conf >> 8) & 0x7][0];
0421                 *val2 = st->
0422                     scale_avail[(st->conf >> 8) & 0x7][1];
0423                 return IIO_VAL_INT_PLUS_NANO;
0424             }
0425             /* 1170mV / 2^23 * 6 */
0426             scale_uv = (1170ULL * 1000000000ULL * 6ULL);
0427             break;
0428         case IIO_TEMP:
0429                 /* 1170mV / 0.81 mV/C / 2^23 */
0430                 scale_uv = 1444444444444444ULL;
0431             break;
0432         default:
0433             return -EINVAL;
0434         }
0435 
0436         scale_uv >>= (chan->scan_type.realbits - (unipolar ? 0 : 1));
0437         *val = 0;
0438         *val2 = scale_uv;
0439         return IIO_VAL_INT_PLUS_NANO;
0440     case IIO_CHAN_INFO_OFFSET:
0441         if (!unipolar)
0442             *val = -(1 << (chan->scan_type.realbits - 1));
0443         else
0444             *val = 0;
0445 
0446         /* Kelvin to Celsius */
0447         if (chan->type == IIO_TEMP) {
0448             unsigned long long offset;
0449             unsigned int shift;
0450 
0451             shift = chan->scan_type.realbits - (unipolar ? 0 : 1);
0452             offset = 273ULL << shift;
0453             do_div(offset, 1444);
0454             *val -= offset;
0455         }
0456         return IIO_VAL_INT;
0457     case IIO_CHAN_INFO_SAMP_FREQ:
0458         *val = st->chip_info
0459                    ->sample_freq_avail[AD7793_MODE_RATE(st->mode)];
0460         return IIO_VAL_INT;
0461     }
0462     return -EINVAL;
0463 }
0464 
0465 static int ad7793_write_raw(struct iio_dev *indio_dev,
0466                    struct iio_chan_spec const *chan,
0467                    int val,
0468                    int val2,
0469                    long mask)
0470 {
0471     struct ad7793_state *st = iio_priv(indio_dev);
0472     int ret, i;
0473     unsigned int tmp;
0474 
0475     ret = iio_device_claim_direct_mode(indio_dev);
0476     if (ret)
0477         return ret;
0478 
0479     switch (mask) {
0480     case IIO_CHAN_INFO_SCALE:
0481         ret = -EINVAL;
0482         for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++)
0483             if (val2 == st->scale_avail[i][1]) {
0484                 ret = 0;
0485                 tmp = st->conf;
0486                 st->conf &= ~AD7793_CONF_GAIN(-1);
0487                 st->conf |= AD7793_CONF_GAIN(i);
0488 
0489                 if (tmp == st->conf)
0490                     break;
0491 
0492                 ad_sd_write_reg(&st->sd, AD7793_REG_CONF,
0493                         sizeof(st->conf), st->conf);
0494                 ad7793_calibrate_all(st);
0495                 break;
0496             }
0497         break;
0498     case IIO_CHAN_INFO_SAMP_FREQ:
0499         if (!val) {
0500             ret = -EINVAL;
0501             break;
0502         }
0503 
0504         for (i = 0; i < 16; i++)
0505             if (val == st->chip_info->sample_freq_avail[i])
0506                 break;
0507 
0508         if (i == 16) {
0509             ret = -EINVAL;
0510             break;
0511         }
0512 
0513         st->mode &= ~AD7793_MODE_RATE(-1);
0514         st->mode |= AD7793_MODE_RATE(i);
0515         ad_sd_write_reg(&st->sd, AD7793_REG_MODE, sizeof(st->mode),
0516                 st->mode);
0517         break;
0518     default:
0519         ret = -EINVAL;
0520     }
0521 
0522     iio_device_release_direct_mode(indio_dev);
0523     return ret;
0524 }
0525 
0526 static int ad7793_write_raw_get_fmt(struct iio_dev *indio_dev,
0527                    struct iio_chan_spec const *chan,
0528                    long mask)
0529 {
0530     return IIO_VAL_INT_PLUS_NANO;
0531 }
0532 
0533 static const struct iio_info ad7793_info = {
0534     .read_raw = &ad7793_read_raw,
0535     .write_raw = &ad7793_write_raw,
0536     .write_raw_get_fmt = &ad7793_write_raw_get_fmt,
0537     .read_avail = ad7793_read_avail,
0538     .attrs = &ad7793_attribute_group,
0539     .validate_trigger = ad_sd_validate_trigger,
0540 };
0541 
0542 static const struct iio_info ad7797_info = {
0543     .read_raw = &ad7793_read_raw,
0544     .write_raw = &ad7793_write_raw,
0545     .write_raw_get_fmt = &ad7793_write_raw_get_fmt,
0546     .attrs = &ad7797_attribute_group,
0547     .validate_trigger = ad_sd_validate_trigger,
0548 };
0549 
0550 #define __AD7793_CHANNEL(_si, _channel1, _channel2, _address, _bits, \
0551     _storagebits, _shift, _extend_name, _type, _mask_type_av, _mask_all) \
0552     { \
0553         .type = (_type), \
0554         .differential = (_channel2 == -1 ? 0 : 1), \
0555         .indexed = 1, \
0556         .channel = (_channel1), \
0557         .channel2 = (_channel2), \
0558         .address = (_address), \
0559         .extend_name = (_extend_name), \
0560         .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
0561             BIT(IIO_CHAN_INFO_OFFSET), \
0562         .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
0563         .info_mask_shared_by_type_available = (_mask_type_av), \
0564         .info_mask_shared_by_all = _mask_all, \
0565         .scan_index = (_si), \
0566         .scan_type = { \
0567             .sign = 'u', \
0568             .realbits = (_bits), \
0569             .storagebits = (_storagebits), \
0570             .shift = (_shift), \
0571             .endianness = IIO_BE, \
0572         }, \
0573     }
0574 
0575 #define AD7793_DIFF_CHANNEL(_si, _channel1, _channel2, _address, _bits, \
0576     _storagebits, _shift) \
0577     __AD7793_CHANNEL(_si, _channel1, _channel2, _address, _bits, \
0578         _storagebits, _shift, NULL, IIO_VOLTAGE, \
0579         BIT(IIO_CHAN_INFO_SCALE), \
0580         BIT(IIO_CHAN_INFO_SAMP_FREQ))
0581 
0582 #define AD7793_SHORTED_CHANNEL(_si, _channel, _address, _bits, \
0583     _storagebits, _shift) \
0584     __AD7793_CHANNEL(_si, _channel, _channel, _address, _bits, \
0585         _storagebits, _shift, "shorted", IIO_VOLTAGE, \
0586         BIT(IIO_CHAN_INFO_SCALE), \
0587         BIT(IIO_CHAN_INFO_SAMP_FREQ))
0588 
0589 #define AD7793_TEMP_CHANNEL(_si, _address, _bits, _storagebits, _shift) \
0590     __AD7793_CHANNEL(_si, 0, -1, _address, _bits, \
0591         _storagebits, _shift, NULL, IIO_TEMP, \
0592         0, \
0593         BIT(IIO_CHAN_INFO_SAMP_FREQ))
0594 
0595 #define AD7793_SUPPLY_CHANNEL(_si, _channel, _address, _bits, _storagebits, \
0596     _shift) \
0597     __AD7793_CHANNEL(_si, _channel, -1, _address, _bits, \
0598         _storagebits, _shift, "supply", IIO_VOLTAGE, \
0599         0, \
0600         BIT(IIO_CHAN_INFO_SAMP_FREQ))
0601 
0602 #define AD7797_DIFF_CHANNEL(_si, _channel1, _channel2, _address, _bits, \
0603     _storagebits, _shift) \
0604     __AD7793_CHANNEL(_si, _channel1, _channel2, _address, _bits, \
0605         _storagebits, _shift, NULL, IIO_VOLTAGE, \
0606         0, \
0607         BIT(IIO_CHAN_INFO_SAMP_FREQ))
0608 
0609 #define AD7797_SHORTED_CHANNEL(_si, _channel, _address, _bits, \
0610     _storagebits, _shift) \
0611     __AD7793_CHANNEL(_si, _channel, _channel, _address, _bits, \
0612         _storagebits, _shift, "shorted", IIO_VOLTAGE, \
0613         0, \
0614         BIT(IIO_CHAN_INFO_SAMP_FREQ))
0615 
0616 #define DECLARE_AD7793_CHANNELS(_name, _b, _sb, _s) \
0617 const struct iio_chan_spec _name##_channels[] = { \
0618     AD7793_DIFF_CHANNEL(0, 0, 0, AD7793_CH_AIN1P_AIN1M, (_b), (_sb), (_s)), \
0619     AD7793_DIFF_CHANNEL(1, 1, 1, AD7793_CH_AIN2P_AIN2M, (_b), (_sb), (_s)), \
0620     AD7793_DIFF_CHANNEL(2, 2, 2, AD7793_CH_AIN3P_AIN3M, (_b), (_sb), (_s)), \
0621     AD7793_SHORTED_CHANNEL(3, 0, AD7793_CH_AIN1M_AIN1M, (_b), (_sb), (_s)), \
0622     AD7793_TEMP_CHANNEL(4, AD7793_CH_TEMP, (_b), (_sb), (_s)), \
0623     AD7793_SUPPLY_CHANNEL(5, 3, AD7793_CH_AVDD_MONITOR, (_b), (_sb), (_s)), \
0624     IIO_CHAN_SOFT_TIMESTAMP(6), \
0625 }
0626 
0627 #define DECLARE_AD7795_CHANNELS(_name, _b, _sb) \
0628 const struct iio_chan_spec _name##_channels[] = { \
0629     AD7793_DIFF_CHANNEL(0, 0, 0, AD7793_CH_AIN1P_AIN1M, (_b), (_sb), 0), \
0630     AD7793_DIFF_CHANNEL(1, 1, 1, AD7793_CH_AIN2P_AIN2M, (_b), (_sb), 0), \
0631     AD7793_DIFF_CHANNEL(2, 2, 2, AD7793_CH_AIN3P_AIN3M, (_b), (_sb), 0), \
0632     AD7793_DIFF_CHANNEL(3, 3, 3, AD7795_CH_AIN4P_AIN4M, (_b), (_sb), 0), \
0633     AD7793_DIFF_CHANNEL(4, 4, 4, AD7795_CH_AIN5P_AIN5M, (_b), (_sb), 0), \
0634     AD7793_DIFF_CHANNEL(5, 5, 5, AD7795_CH_AIN6P_AIN6M, (_b), (_sb), 0), \
0635     AD7793_SHORTED_CHANNEL(6, 0, AD7795_CH_AIN1M_AIN1M, (_b), (_sb), 0), \
0636     AD7793_TEMP_CHANNEL(7, AD7793_CH_TEMP, (_b), (_sb), 0), \
0637     AD7793_SUPPLY_CHANNEL(8, 3, AD7793_CH_AVDD_MONITOR, (_b), (_sb), 0), \
0638     IIO_CHAN_SOFT_TIMESTAMP(9), \
0639 }
0640 
0641 #define DECLARE_AD7797_CHANNELS(_name, _b, _sb) \
0642 const struct iio_chan_spec _name##_channels[] = { \
0643     AD7797_DIFF_CHANNEL(0, 0, 0, AD7793_CH_AIN1P_AIN1M, (_b), (_sb), 0), \
0644     AD7797_SHORTED_CHANNEL(1, 0, AD7793_CH_AIN1M_AIN1M, (_b), (_sb), 0), \
0645     AD7793_TEMP_CHANNEL(2, AD7793_CH_TEMP, (_b), (_sb), 0), \
0646     AD7793_SUPPLY_CHANNEL(3, 3, AD7793_CH_AVDD_MONITOR, (_b), (_sb), 0), \
0647     IIO_CHAN_SOFT_TIMESTAMP(4), \
0648 }
0649 
0650 #define DECLARE_AD7799_CHANNELS(_name, _b, _sb) \
0651 const struct iio_chan_spec _name##_channels[] = { \
0652     AD7793_DIFF_CHANNEL(0, 0, 0, AD7793_CH_AIN1P_AIN1M, (_b), (_sb), 0), \
0653     AD7793_DIFF_CHANNEL(1, 1, 1, AD7793_CH_AIN2P_AIN2M, (_b), (_sb), 0), \
0654     AD7793_DIFF_CHANNEL(2, 2, 2, AD7793_CH_AIN3P_AIN3M, (_b), (_sb), 0), \
0655     AD7793_SHORTED_CHANNEL(3, 0, AD7793_CH_AIN1M_AIN1M, (_b), (_sb), 0), \
0656     AD7793_SUPPLY_CHANNEL(4, 3, AD7793_CH_AVDD_MONITOR, (_b), (_sb), 0), \
0657     IIO_CHAN_SOFT_TIMESTAMP(5), \
0658 }
0659 
0660 static DECLARE_AD7793_CHANNELS(ad7785, 20, 32, 4);
0661 static DECLARE_AD7793_CHANNELS(ad7792, 16, 32, 0);
0662 static DECLARE_AD7793_CHANNELS(ad7793, 24, 32, 0);
0663 static DECLARE_AD7795_CHANNELS(ad7794, 16, 32);
0664 static DECLARE_AD7795_CHANNELS(ad7795, 24, 32);
0665 static DECLARE_AD7797_CHANNELS(ad7796, 16, 16);
0666 static DECLARE_AD7797_CHANNELS(ad7797, 24, 32);
0667 static DECLARE_AD7799_CHANNELS(ad7798, 16, 16);
0668 static DECLARE_AD7799_CHANNELS(ad7799, 24, 32);
0669 
0670 static const struct ad7793_chip_info ad7793_chip_info_tbl[] = {
0671     [ID_AD7785] = {
0672         .id = AD7785_ID,
0673         .channels = ad7785_channels,
0674         .num_channels = ARRAY_SIZE(ad7785_channels),
0675         .iio_info = &ad7793_info,
0676         .sample_freq_avail = ad7793_sample_freq_avail,
0677         .flags = AD7793_FLAG_HAS_CLKSEL |
0678             AD7793_FLAG_HAS_REFSEL |
0679             AD7793_FLAG_HAS_VBIAS |
0680             AD7793_HAS_EXITATION_CURRENT |
0681             AD7793_FLAG_HAS_GAIN |
0682             AD7793_FLAG_HAS_BUFFER,
0683     },
0684     [ID_AD7792] = {
0685         .id = AD7792_ID,
0686         .channels = ad7792_channels,
0687         .num_channels = ARRAY_SIZE(ad7792_channels),
0688         .iio_info = &ad7793_info,
0689         .sample_freq_avail = ad7793_sample_freq_avail,
0690         .flags = AD7793_FLAG_HAS_CLKSEL |
0691             AD7793_FLAG_HAS_REFSEL |
0692             AD7793_FLAG_HAS_VBIAS |
0693             AD7793_HAS_EXITATION_CURRENT |
0694             AD7793_FLAG_HAS_GAIN |
0695             AD7793_FLAG_HAS_BUFFER,
0696     },
0697     [ID_AD7793] = {
0698         .id = AD7793_ID,
0699         .channels = ad7793_channels,
0700         .num_channels = ARRAY_SIZE(ad7793_channels),
0701         .iio_info = &ad7793_info,
0702         .sample_freq_avail = ad7793_sample_freq_avail,
0703         .flags = AD7793_FLAG_HAS_CLKSEL |
0704             AD7793_FLAG_HAS_REFSEL |
0705             AD7793_FLAG_HAS_VBIAS |
0706             AD7793_HAS_EXITATION_CURRENT |
0707             AD7793_FLAG_HAS_GAIN |
0708             AD7793_FLAG_HAS_BUFFER,
0709     },
0710     [ID_AD7794] = {
0711         .id = AD7794_ID,
0712         .channels = ad7794_channels,
0713         .num_channels = ARRAY_SIZE(ad7794_channels),
0714         .iio_info = &ad7793_info,
0715         .sample_freq_avail = ad7793_sample_freq_avail,
0716         .flags = AD7793_FLAG_HAS_CLKSEL |
0717             AD7793_FLAG_HAS_REFSEL |
0718             AD7793_FLAG_HAS_VBIAS |
0719             AD7793_HAS_EXITATION_CURRENT |
0720             AD7793_FLAG_HAS_GAIN |
0721             AD7793_FLAG_HAS_BUFFER,
0722     },
0723     [ID_AD7795] = {
0724         .id = AD7795_ID,
0725         .channels = ad7795_channels,
0726         .num_channels = ARRAY_SIZE(ad7795_channels),
0727         .iio_info = &ad7793_info,
0728         .sample_freq_avail = ad7793_sample_freq_avail,
0729         .flags = AD7793_FLAG_HAS_CLKSEL |
0730             AD7793_FLAG_HAS_REFSEL |
0731             AD7793_FLAG_HAS_VBIAS |
0732             AD7793_HAS_EXITATION_CURRENT |
0733             AD7793_FLAG_HAS_GAIN |
0734             AD7793_FLAG_HAS_BUFFER,
0735     },
0736     [ID_AD7796] = {
0737         .id = AD7796_ID,
0738         .channels = ad7796_channels,
0739         .num_channels = ARRAY_SIZE(ad7796_channels),
0740         .iio_info = &ad7797_info,
0741         .sample_freq_avail = ad7797_sample_freq_avail,
0742         .flags = AD7793_FLAG_HAS_CLKSEL,
0743     },
0744     [ID_AD7797] = {
0745         .id = AD7797_ID,
0746         .channels = ad7797_channels,
0747         .num_channels = ARRAY_SIZE(ad7797_channels),
0748         .iio_info = &ad7797_info,
0749         .sample_freq_avail = ad7797_sample_freq_avail,
0750         .flags = AD7793_FLAG_HAS_CLKSEL,
0751     },
0752     [ID_AD7798] = {
0753         .id = AD7798_ID,
0754         .channels = ad7798_channels,
0755         .num_channels = ARRAY_SIZE(ad7798_channels),
0756         .iio_info = &ad7793_info,
0757         .sample_freq_avail = ad7793_sample_freq_avail,
0758         .flags = AD7793_FLAG_HAS_GAIN |
0759             AD7793_FLAG_HAS_BUFFER,
0760     },
0761     [ID_AD7799] = {
0762         .id = AD7799_ID,
0763         .channels = ad7799_channels,
0764         .num_channels = ARRAY_SIZE(ad7799_channels),
0765         .iio_info = &ad7793_info,
0766         .sample_freq_avail = ad7793_sample_freq_avail,
0767         .flags = AD7793_FLAG_HAS_GAIN |
0768             AD7793_FLAG_HAS_BUFFER,
0769     },
0770 };
0771 
0772 static void ad7793_reg_disable(void *reg)
0773 {
0774     regulator_disable(reg);
0775 }
0776 
0777 static int ad7793_probe(struct spi_device *spi)
0778 {
0779     const struct ad7793_platform_data *pdata = spi->dev.platform_data;
0780     struct ad7793_state *st;
0781     struct iio_dev *indio_dev;
0782     int ret, vref_mv = 0;
0783 
0784     if (!pdata) {
0785         dev_err(&spi->dev, "no platform data?\n");
0786         return -ENODEV;
0787     }
0788 
0789     if (!spi->irq) {
0790         dev_err(&spi->dev, "no IRQ?\n");
0791         return -ENODEV;
0792     }
0793 
0794     indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
0795     if (indio_dev == NULL)
0796         return -ENOMEM;
0797 
0798     st = iio_priv(indio_dev);
0799 
0800     ad_sd_init(&st->sd, indio_dev, spi, &ad7793_sigma_delta_info);
0801 
0802     if (pdata->refsel != AD7793_REFSEL_INTERNAL) {
0803         st->reg = devm_regulator_get(&spi->dev, "refin");
0804         if (IS_ERR(st->reg))
0805             return PTR_ERR(st->reg);
0806 
0807         ret = regulator_enable(st->reg);
0808         if (ret)
0809             return ret;
0810 
0811         ret = devm_add_action_or_reset(&spi->dev, ad7793_reg_disable, st->reg);
0812         if (ret)
0813             return ret;
0814 
0815         vref_mv = regulator_get_voltage(st->reg);
0816         if (vref_mv < 0)
0817             return vref_mv;
0818 
0819         vref_mv /= 1000;
0820     } else {
0821         vref_mv = 1170; /* Build-in ref */
0822     }
0823 
0824     st->chip_info =
0825         &ad7793_chip_info_tbl[spi_get_device_id(spi)->driver_data];
0826 
0827     indio_dev->name = spi_get_device_id(spi)->name;
0828     indio_dev->modes = INDIO_DIRECT_MODE;
0829     indio_dev->channels = st->chip_info->channels;
0830     indio_dev->num_channels = st->chip_info->num_channels;
0831     indio_dev->info = st->chip_info->iio_info;
0832 
0833     ret = devm_ad_sd_setup_buffer_and_trigger(&spi->dev, indio_dev);
0834     if (ret)
0835         return ret;
0836 
0837     ret = ad7793_setup(indio_dev, pdata, vref_mv);
0838     if (ret)
0839         return ret;
0840 
0841     return devm_iio_device_register(&spi->dev, indio_dev);
0842 }
0843 
0844 static const struct spi_device_id ad7793_id[] = {
0845     {"ad7785", ID_AD7785},
0846     {"ad7792", ID_AD7792},
0847     {"ad7793", ID_AD7793},
0848     {"ad7794", ID_AD7794},
0849     {"ad7795", ID_AD7795},
0850     {"ad7796", ID_AD7796},
0851     {"ad7797", ID_AD7797},
0852     {"ad7798", ID_AD7798},
0853     {"ad7799", ID_AD7799},
0854     {}
0855 };
0856 MODULE_DEVICE_TABLE(spi, ad7793_id);
0857 
0858 static struct spi_driver ad7793_driver = {
0859     .driver = {
0860         .name   = "ad7793",
0861     },
0862     .probe      = ad7793_probe,
0863     .id_table   = ad7793_id,
0864 };
0865 module_spi_driver(ad7793_driver);
0866 
0867 MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>");
0868 MODULE_DESCRIPTION("Analog Devices AD7793 and similar ADCs");
0869 MODULE_LICENSE("GPL v2");
0870 MODULE_IMPORT_NS(IIO_AD_SIGMA_DELTA);
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