Back to home page

OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Analog Devices AD7768-1 SPI ADC driver
0004  *
0005  * Copyright 2017 Analog Devices Inc.
0006  */
0007 #include <linux/bitfield.h>
0008 #include <linux/clk.h>
0009 #include <linux/delay.h>
0010 #include <linux/device.h>
0011 #include <linux/err.h>
0012 #include <linux/gpio/consumer.h>
0013 #include <linux/kernel.h>
0014 #include <linux/module.h>
0015 #include <linux/regulator/consumer.h>
0016 #include <linux/sysfs.h>
0017 #include <linux/spi/spi.h>
0018 
0019 #include <linux/iio/buffer.h>
0020 #include <linux/iio/iio.h>
0021 #include <linux/iio/sysfs.h>
0022 #include <linux/iio/trigger.h>
0023 #include <linux/iio/triggered_buffer.h>
0024 #include <linux/iio/trigger_consumer.h>
0025 
0026 /* AD7768 registers definition */
0027 #define AD7768_REG_CHIP_TYPE        0x3
0028 #define AD7768_REG_PROD_ID_L        0x4
0029 #define AD7768_REG_PROD_ID_H        0x5
0030 #define AD7768_REG_CHIP_GRADE       0x6
0031 #define AD7768_REG_SCRATCH_PAD      0x0A
0032 #define AD7768_REG_VENDOR_L     0x0C
0033 #define AD7768_REG_VENDOR_H     0x0D
0034 #define AD7768_REG_INTERFACE_FORMAT 0x14
0035 #define AD7768_REG_POWER_CLOCK      0x15
0036 #define AD7768_REG_ANALOG       0x16
0037 #define AD7768_REG_ANALOG2      0x17
0038 #define AD7768_REG_CONVERSION       0x18
0039 #define AD7768_REG_DIGITAL_FILTER   0x19
0040 #define AD7768_REG_SINC3_DEC_RATE_MSB   0x1A
0041 #define AD7768_REG_SINC3_DEC_RATE_LSB   0x1B
0042 #define AD7768_REG_DUTY_CYCLE_RATIO 0x1C
0043 #define AD7768_REG_SYNC_RESET       0x1D
0044 #define AD7768_REG_GPIO_CONTROL     0x1E
0045 #define AD7768_REG_GPIO_WRITE       0x1F
0046 #define AD7768_REG_GPIO_READ        0x20
0047 #define AD7768_REG_OFFSET_HI        0x21
0048 #define AD7768_REG_OFFSET_MID       0x22
0049 #define AD7768_REG_OFFSET_LO        0x23
0050 #define AD7768_REG_GAIN_HI      0x24
0051 #define AD7768_REG_GAIN_MID     0x25
0052 #define AD7768_REG_GAIN_LO      0x26
0053 #define AD7768_REG_SPI_DIAG_ENABLE  0x28
0054 #define AD7768_REG_ADC_DIAG_ENABLE  0x29
0055 #define AD7768_REG_DIG_DIAG_ENABLE  0x2A
0056 #define AD7768_REG_ADC_DATA     0x2C
0057 #define AD7768_REG_MASTER_STATUS    0x2D
0058 #define AD7768_REG_SPI_DIAG_STATUS  0x2E
0059 #define AD7768_REG_ADC_DIAG_STATUS  0x2F
0060 #define AD7768_REG_DIG_DIAG_STATUS  0x30
0061 #define AD7768_REG_MCLK_COUNTER     0x31
0062 
0063 /* AD7768_REG_POWER_CLOCK */
0064 #define AD7768_PWR_MCLK_DIV_MSK     GENMASK(5, 4)
0065 #define AD7768_PWR_MCLK_DIV(x)      FIELD_PREP(AD7768_PWR_MCLK_DIV_MSK, x)
0066 #define AD7768_PWR_PWRMODE_MSK      GENMASK(1, 0)
0067 #define AD7768_PWR_PWRMODE(x)       FIELD_PREP(AD7768_PWR_PWRMODE_MSK, x)
0068 
0069 /* AD7768_REG_DIGITAL_FILTER */
0070 #define AD7768_DIG_FIL_FIL_MSK      GENMASK(6, 4)
0071 #define AD7768_DIG_FIL_FIL(x)       FIELD_PREP(AD7768_DIG_FIL_FIL_MSK, x)
0072 #define AD7768_DIG_FIL_DEC_MSK      GENMASK(2, 0)
0073 #define AD7768_DIG_FIL_DEC_RATE(x)  FIELD_PREP(AD7768_DIG_FIL_DEC_MSK, x)
0074 
0075 /* AD7768_REG_CONVERSION */
0076 #define AD7768_CONV_MODE_MSK        GENMASK(2, 0)
0077 #define AD7768_CONV_MODE(x)     FIELD_PREP(AD7768_CONV_MODE_MSK, x)
0078 
0079 #define AD7768_RD_FLAG_MSK(x)       (BIT(6) | ((x) & 0x3F))
0080 #define AD7768_WR_FLAG_MSK(x)       ((x) & 0x3F)
0081 
0082 enum ad7768_conv_mode {
0083     AD7768_CONTINUOUS,
0084     AD7768_ONE_SHOT,
0085     AD7768_SINGLE,
0086     AD7768_PERIODIC,
0087     AD7768_STANDBY
0088 };
0089 
0090 enum ad7768_pwrmode {
0091     AD7768_ECO_MODE = 0,
0092     AD7768_MED_MODE = 2,
0093     AD7768_FAST_MODE = 3
0094 };
0095 
0096 enum ad7768_mclk_div {
0097     AD7768_MCLK_DIV_16,
0098     AD7768_MCLK_DIV_8,
0099     AD7768_MCLK_DIV_4,
0100     AD7768_MCLK_DIV_2
0101 };
0102 
0103 enum ad7768_dec_rate {
0104     AD7768_DEC_RATE_32 = 0,
0105     AD7768_DEC_RATE_64 = 1,
0106     AD7768_DEC_RATE_128 = 2,
0107     AD7768_DEC_RATE_256 = 3,
0108     AD7768_DEC_RATE_512 = 4,
0109     AD7768_DEC_RATE_1024 = 5,
0110     AD7768_DEC_RATE_8 = 9,
0111     AD7768_DEC_RATE_16 = 10
0112 };
0113 
0114 struct ad7768_clk_configuration {
0115     enum ad7768_mclk_div mclk_div;
0116     enum ad7768_dec_rate dec_rate;
0117     unsigned int clk_div;
0118     enum ad7768_pwrmode pwrmode;
0119 };
0120 
0121 static const struct ad7768_clk_configuration ad7768_clk_config[] = {
0122     { AD7768_MCLK_DIV_2, AD7768_DEC_RATE_8, 16,  AD7768_FAST_MODE },
0123     { AD7768_MCLK_DIV_2, AD7768_DEC_RATE_16, 32,  AD7768_FAST_MODE },
0124     { AD7768_MCLK_DIV_2, AD7768_DEC_RATE_32, 64, AD7768_FAST_MODE },
0125     { AD7768_MCLK_DIV_2, AD7768_DEC_RATE_64, 128, AD7768_FAST_MODE },
0126     { AD7768_MCLK_DIV_2, AD7768_DEC_RATE_128, 256, AD7768_FAST_MODE },
0127     { AD7768_MCLK_DIV_4, AD7768_DEC_RATE_128, 512, AD7768_MED_MODE },
0128     { AD7768_MCLK_DIV_4, AD7768_DEC_RATE_256, 1024, AD7768_MED_MODE },
0129     { AD7768_MCLK_DIV_4, AD7768_DEC_RATE_512, 2048, AD7768_MED_MODE },
0130     { AD7768_MCLK_DIV_4, AD7768_DEC_RATE_1024, 4096, AD7768_MED_MODE },
0131     { AD7768_MCLK_DIV_8, AD7768_DEC_RATE_1024, 8192, AD7768_MED_MODE },
0132     { AD7768_MCLK_DIV_16, AD7768_DEC_RATE_1024, 16384, AD7768_ECO_MODE },
0133 };
0134 
0135 static const struct iio_chan_spec ad7768_channels[] = {
0136     {
0137         .type = IIO_VOLTAGE,
0138         .info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
0139         .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),
0140         .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ),
0141         .indexed = 1,
0142         .channel = 0,
0143         .scan_index = 0,
0144         .scan_type = {
0145             .sign = 'u',
0146             .realbits = 24,
0147             .storagebits = 32,
0148             .shift = 8,
0149             .endianness = IIO_BE,
0150         },
0151     },
0152 };
0153 
0154 struct ad7768_state {
0155     struct spi_device *spi;
0156     struct regulator *vref;
0157     struct mutex lock;
0158     struct clk *mclk;
0159     unsigned int mclk_freq;
0160     unsigned int samp_freq;
0161     struct completion completion;
0162     struct iio_trigger *trig;
0163     struct gpio_desc *gpio_sync_in;
0164     const char *labels[ARRAY_SIZE(ad7768_channels)];
0165     /*
0166      * DMA (thus cache coherency maintenance) may require the
0167      * transfer buffers to live in their own cache lines.
0168      */
0169     union {
0170         struct {
0171             __be32 chan;
0172             s64 timestamp;
0173         } scan;
0174         __be32 d32;
0175         u8 d8[2];
0176     } data __aligned(IIO_DMA_MINALIGN);
0177 };
0178 
0179 static int ad7768_spi_reg_read(struct ad7768_state *st, unsigned int addr,
0180                    unsigned int len)
0181 {
0182     unsigned int shift;
0183     int ret;
0184 
0185     shift = 32 - (8 * len);
0186     st->data.d8[0] = AD7768_RD_FLAG_MSK(addr);
0187 
0188     ret = spi_write_then_read(st->spi, st->data.d8, 1,
0189                   &st->data.d32, len);
0190     if (ret < 0)
0191         return ret;
0192 
0193     return (be32_to_cpu(st->data.d32) >> shift);
0194 }
0195 
0196 static int ad7768_spi_reg_write(struct ad7768_state *st,
0197                 unsigned int addr,
0198                 unsigned int val)
0199 {
0200     st->data.d8[0] = AD7768_WR_FLAG_MSK(addr);
0201     st->data.d8[1] = val & 0xFF;
0202 
0203     return spi_write(st->spi, st->data.d8, 2);
0204 }
0205 
0206 static int ad7768_set_mode(struct ad7768_state *st,
0207                enum ad7768_conv_mode mode)
0208 {
0209     int regval;
0210 
0211     regval = ad7768_spi_reg_read(st, AD7768_REG_CONVERSION, 1);
0212     if (regval < 0)
0213         return regval;
0214 
0215     regval &= ~AD7768_CONV_MODE_MSK;
0216     regval |= AD7768_CONV_MODE(mode);
0217 
0218     return ad7768_spi_reg_write(st, AD7768_REG_CONVERSION, regval);
0219 }
0220 
0221 static int ad7768_scan_direct(struct iio_dev *indio_dev)
0222 {
0223     struct ad7768_state *st = iio_priv(indio_dev);
0224     int readval, ret;
0225 
0226     reinit_completion(&st->completion);
0227 
0228     ret = ad7768_set_mode(st, AD7768_ONE_SHOT);
0229     if (ret < 0)
0230         return ret;
0231 
0232     ret = wait_for_completion_timeout(&st->completion,
0233                       msecs_to_jiffies(1000));
0234     if (!ret)
0235         return -ETIMEDOUT;
0236 
0237     readval = ad7768_spi_reg_read(st, AD7768_REG_ADC_DATA, 3);
0238     if (readval < 0)
0239         return readval;
0240     /*
0241      * Any SPI configuration of the AD7768-1 can only be
0242      * performed in continuous conversion mode.
0243      */
0244     ret = ad7768_set_mode(st, AD7768_CONTINUOUS);
0245     if (ret < 0)
0246         return ret;
0247 
0248     return readval;
0249 }
0250 
0251 static int ad7768_reg_access(struct iio_dev *indio_dev,
0252                  unsigned int reg,
0253                  unsigned int writeval,
0254                  unsigned int *readval)
0255 {
0256     struct ad7768_state *st = iio_priv(indio_dev);
0257     int ret;
0258 
0259     mutex_lock(&st->lock);
0260     if (readval) {
0261         ret = ad7768_spi_reg_read(st, reg, 1);
0262         if (ret < 0)
0263             goto err_unlock;
0264         *readval = ret;
0265         ret = 0;
0266     } else {
0267         ret = ad7768_spi_reg_write(st, reg, writeval);
0268     }
0269 err_unlock:
0270     mutex_unlock(&st->lock);
0271 
0272     return ret;
0273 }
0274 
0275 static int ad7768_set_dig_fil(struct ad7768_state *st,
0276                   enum ad7768_dec_rate dec_rate)
0277 {
0278     unsigned int mode;
0279     int ret;
0280 
0281     if (dec_rate == AD7768_DEC_RATE_8 || dec_rate == AD7768_DEC_RATE_16)
0282         mode = AD7768_DIG_FIL_FIL(dec_rate);
0283     else
0284         mode = AD7768_DIG_FIL_DEC_RATE(dec_rate);
0285 
0286     ret = ad7768_spi_reg_write(st, AD7768_REG_DIGITAL_FILTER, mode);
0287     if (ret < 0)
0288         return ret;
0289 
0290     /* A sync-in pulse is required every time the filter dec rate changes */
0291     gpiod_set_value(st->gpio_sync_in, 1);
0292     gpiod_set_value(st->gpio_sync_in, 0);
0293 
0294     return 0;
0295 }
0296 
0297 static int ad7768_set_freq(struct ad7768_state *st,
0298                unsigned int freq)
0299 {
0300     unsigned int diff_new, diff_old, pwr_mode, i, idx;
0301     int res, ret;
0302 
0303     diff_old = U32_MAX;
0304     idx = 0;
0305 
0306     res = DIV_ROUND_CLOSEST(st->mclk_freq, freq);
0307 
0308     /* Find the closest match for the desired sampling frequency */
0309     for (i = 0; i < ARRAY_SIZE(ad7768_clk_config); i++) {
0310         diff_new = abs(res - ad7768_clk_config[i].clk_div);
0311         if (diff_new < diff_old) {
0312             diff_old = diff_new;
0313             idx = i;
0314         }
0315     }
0316 
0317     /*
0318      * Set both the mclk_div and pwrmode with a single write to the
0319      * POWER_CLOCK register
0320      */
0321     pwr_mode = AD7768_PWR_MCLK_DIV(ad7768_clk_config[idx].mclk_div) |
0322            AD7768_PWR_PWRMODE(ad7768_clk_config[idx].pwrmode);
0323     ret = ad7768_spi_reg_write(st, AD7768_REG_POWER_CLOCK, pwr_mode);
0324     if (ret < 0)
0325         return ret;
0326 
0327     ret =  ad7768_set_dig_fil(st, ad7768_clk_config[idx].dec_rate);
0328     if (ret < 0)
0329         return ret;
0330 
0331     st->samp_freq = DIV_ROUND_CLOSEST(st->mclk_freq,
0332                       ad7768_clk_config[idx].clk_div);
0333 
0334     return 0;
0335 }
0336 
0337 static ssize_t ad7768_sampling_freq_avail(struct device *dev,
0338                       struct device_attribute *attr,
0339                       char *buf)
0340 {
0341     struct iio_dev *indio_dev = dev_to_iio_dev(dev);
0342     struct ad7768_state *st = iio_priv(indio_dev);
0343     unsigned int freq;
0344     int i, len = 0;
0345 
0346     for (i = 0; i < ARRAY_SIZE(ad7768_clk_config); i++) {
0347         freq = DIV_ROUND_CLOSEST(st->mclk_freq,
0348                      ad7768_clk_config[i].clk_div);
0349         len += scnprintf(buf + len, PAGE_SIZE - len, "%d ", freq);
0350     }
0351 
0352     buf[len - 1] = '\n';
0353 
0354     return len;
0355 }
0356 
0357 static IIO_DEV_ATTR_SAMP_FREQ_AVAIL(ad7768_sampling_freq_avail);
0358 
0359 static int ad7768_read_raw(struct iio_dev *indio_dev,
0360                struct iio_chan_spec const *chan,
0361                int *val, int *val2, long info)
0362 {
0363     struct ad7768_state *st = iio_priv(indio_dev);
0364     int scale_uv, ret;
0365 
0366     switch (info) {
0367     case IIO_CHAN_INFO_RAW:
0368         ret = iio_device_claim_direct_mode(indio_dev);
0369         if (ret)
0370             return ret;
0371 
0372         ret = ad7768_scan_direct(indio_dev);
0373         if (ret >= 0)
0374             *val = ret;
0375 
0376         iio_device_release_direct_mode(indio_dev);
0377         if (ret < 0)
0378             return ret;
0379 
0380         return IIO_VAL_INT;
0381 
0382     case IIO_CHAN_INFO_SCALE:
0383         scale_uv = regulator_get_voltage(st->vref);
0384         if (scale_uv < 0)
0385             return scale_uv;
0386 
0387         *val = (scale_uv * 2) / 1000;
0388         *val2 = chan->scan_type.realbits;
0389 
0390         return IIO_VAL_FRACTIONAL_LOG2;
0391 
0392     case IIO_CHAN_INFO_SAMP_FREQ:
0393         *val = st->samp_freq;
0394 
0395         return IIO_VAL_INT;
0396     }
0397 
0398     return -EINVAL;
0399 }
0400 
0401 static int ad7768_write_raw(struct iio_dev *indio_dev,
0402                 struct iio_chan_spec const *chan,
0403                 int val, int val2, long info)
0404 {
0405     struct ad7768_state *st = iio_priv(indio_dev);
0406 
0407     switch (info) {
0408     case IIO_CHAN_INFO_SAMP_FREQ:
0409         return ad7768_set_freq(st, val);
0410     default:
0411         return -EINVAL;
0412     }
0413 }
0414 
0415 static int ad7768_read_label(struct iio_dev *indio_dev,
0416     const struct iio_chan_spec *chan, char *label)
0417 {
0418     struct ad7768_state *st = iio_priv(indio_dev);
0419 
0420     return sprintf(label, "%s\n", st->labels[chan->channel]);
0421 }
0422 
0423 static struct attribute *ad7768_attributes[] = {
0424     &iio_dev_attr_sampling_frequency_available.dev_attr.attr,
0425     NULL
0426 };
0427 
0428 static const struct attribute_group ad7768_group = {
0429     .attrs = ad7768_attributes,
0430 };
0431 
0432 static const struct iio_info ad7768_info = {
0433     .attrs = &ad7768_group,
0434     .read_raw = &ad7768_read_raw,
0435     .write_raw = &ad7768_write_raw,
0436     .read_label = ad7768_read_label,
0437     .debugfs_reg_access = &ad7768_reg_access,
0438 };
0439 
0440 static int ad7768_setup(struct ad7768_state *st)
0441 {
0442     int ret;
0443 
0444     /*
0445      * Two writes to the SPI_RESET[1:0] bits are required to initiate
0446      * a software reset. The bits must first be set to 11, and then
0447      * to 10. When the sequence is detected, the reset occurs.
0448      * See the datasheet, page 70.
0449      */
0450     ret = ad7768_spi_reg_write(st, AD7768_REG_SYNC_RESET, 0x3);
0451     if (ret)
0452         return ret;
0453 
0454     ret = ad7768_spi_reg_write(st, AD7768_REG_SYNC_RESET, 0x2);
0455     if (ret)
0456         return ret;
0457 
0458     st->gpio_sync_in = devm_gpiod_get(&st->spi->dev, "adi,sync-in",
0459                       GPIOD_OUT_LOW);
0460     if (IS_ERR(st->gpio_sync_in))
0461         return PTR_ERR(st->gpio_sync_in);
0462 
0463     /* Set the default sampling frequency to 32000 kSPS */
0464     return ad7768_set_freq(st, 32000);
0465 }
0466 
0467 static irqreturn_t ad7768_trigger_handler(int irq, void *p)
0468 {
0469     struct iio_poll_func *pf = p;
0470     struct iio_dev *indio_dev = pf->indio_dev;
0471     struct ad7768_state *st = iio_priv(indio_dev);
0472     int ret;
0473 
0474     mutex_lock(&st->lock);
0475 
0476     ret = spi_read(st->spi, &st->data.scan.chan, 3);
0477     if (ret < 0)
0478         goto err_unlock;
0479 
0480     iio_push_to_buffers_with_timestamp(indio_dev, &st->data.scan,
0481                        iio_get_time_ns(indio_dev));
0482 
0483 err_unlock:
0484     iio_trigger_notify_done(indio_dev->trig);
0485     mutex_unlock(&st->lock);
0486 
0487     return IRQ_HANDLED;
0488 }
0489 
0490 static irqreturn_t ad7768_interrupt(int irq, void *dev_id)
0491 {
0492     struct iio_dev *indio_dev = dev_id;
0493     struct ad7768_state *st = iio_priv(indio_dev);
0494 
0495     if (iio_buffer_enabled(indio_dev))
0496         iio_trigger_poll(st->trig);
0497     else
0498         complete(&st->completion);
0499 
0500     return IRQ_HANDLED;
0501 };
0502 
0503 static int ad7768_buffer_postenable(struct iio_dev *indio_dev)
0504 {
0505     struct ad7768_state *st = iio_priv(indio_dev);
0506 
0507     /*
0508      * Write a 1 to the LSB of the INTERFACE_FORMAT register to enter
0509      * continuous read mode. Subsequent data reads do not require an
0510      * initial 8-bit write to query the ADC_DATA register.
0511      */
0512     return ad7768_spi_reg_write(st, AD7768_REG_INTERFACE_FORMAT, 0x01);
0513 }
0514 
0515 static int ad7768_buffer_predisable(struct iio_dev *indio_dev)
0516 {
0517     struct ad7768_state *st = iio_priv(indio_dev);
0518 
0519     /*
0520      * To exit continuous read mode, perform a single read of the ADC_DATA
0521      * reg (0x2C), which allows further configuration of the device.
0522      */
0523     return ad7768_spi_reg_read(st, AD7768_REG_ADC_DATA, 3);
0524 }
0525 
0526 static const struct iio_buffer_setup_ops ad7768_buffer_ops = {
0527     .postenable = &ad7768_buffer_postenable,
0528     .predisable = &ad7768_buffer_predisable,
0529 };
0530 
0531 static const struct iio_trigger_ops ad7768_trigger_ops = {
0532     .validate_device = iio_trigger_validate_own_device,
0533 };
0534 
0535 static void ad7768_regulator_disable(void *data)
0536 {
0537     struct ad7768_state *st = data;
0538 
0539     regulator_disable(st->vref);
0540 }
0541 
0542 static void ad7768_clk_disable(void *data)
0543 {
0544     struct ad7768_state *st = data;
0545 
0546     clk_disable_unprepare(st->mclk);
0547 }
0548 
0549 static int ad7768_set_channel_label(struct iio_dev *indio_dev,
0550                         int num_channels)
0551 {
0552     struct ad7768_state *st = iio_priv(indio_dev);
0553     struct device *device = indio_dev->dev.parent;
0554     struct fwnode_handle *fwnode;
0555     struct fwnode_handle *child;
0556     const char *label;
0557     int crt_ch = 0;
0558 
0559     fwnode = dev_fwnode(device);
0560     fwnode_for_each_child_node(fwnode, child) {
0561         if (fwnode_property_read_u32(child, "reg", &crt_ch))
0562             continue;
0563 
0564         if (crt_ch >= num_channels)
0565             continue;
0566 
0567         if (fwnode_property_read_string(child, "label", &label))
0568             continue;
0569 
0570         st->labels[crt_ch] = label;
0571     }
0572 
0573     return 0;
0574 }
0575 
0576 static int ad7768_probe(struct spi_device *spi)
0577 {
0578     struct ad7768_state *st;
0579     struct iio_dev *indio_dev;
0580     int ret;
0581 
0582     indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
0583     if (!indio_dev)
0584         return -ENOMEM;
0585 
0586     st = iio_priv(indio_dev);
0587     st->spi = spi;
0588 
0589     st->vref = devm_regulator_get(&spi->dev, "vref");
0590     if (IS_ERR(st->vref))
0591         return PTR_ERR(st->vref);
0592 
0593     ret = regulator_enable(st->vref);
0594     if (ret) {
0595         dev_err(&spi->dev, "Failed to enable specified vref supply\n");
0596         return ret;
0597     }
0598 
0599     ret = devm_add_action_or_reset(&spi->dev, ad7768_regulator_disable, st);
0600     if (ret)
0601         return ret;
0602 
0603     st->mclk = devm_clk_get(&spi->dev, "mclk");
0604     if (IS_ERR(st->mclk))
0605         return PTR_ERR(st->mclk);
0606 
0607     ret = clk_prepare_enable(st->mclk);
0608     if (ret < 0)
0609         return ret;
0610 
0611     ret = devm_add_action_or_reset(&spi->dev, ad7768_clk_disable, st);
0612     if (ret)
0613         return ret;
0614 
0615     st->mclk_freq = clk_get_rate(st->mclk);
0616 
0617     mutex_init(&st->lock);
0618 
0619     indio_dev->channels = ad7768_channels;
0620     indio_dev->num_channels = ARRAY_SIZE(ad7768_channels);
0621     indio_dev->name = spi_get_device_id(spi)->name;
0622     indio_dev->info = &ad7768_info;
0623     indio_dev->modes = INDIO_DIRECT_MODE;
0624 
0625     ret = ad7768_setup(st);
0626     if (ret < 0) {
0627         dev_err(&spi->dev, "AD7768 setup failed\n");
0628         return ret;
0629     }
0630 
0631     st->trig = devm_iio_trigger_alloc(&spi->dev, "%s-dev%d",
0632                       indio_dev->name,
0633                       iio_device_id(indio_dev));
0634     if (!st->trig)
0635         return -ENOMEM;
0636 
0637     st->trig->ops = &ad7768_trigger_ops;
0638     iio_trigger_set_drvdata(st->trig, indio_dev);
0639     ret = devm_iio_trigger_register(&spi->dev, st->trig);
0640     if (ret)
0641         return ret;
0642 
0643     indio_dev->trig = iio_trigger_get(st->trig);
0644 
0645     init_completion(&st->completion);
0646 
0647     ret = ad7768_set_channel_label(indio_dev, ARRAY_SIZE(ad7768_channels));
0648     if (ret)
0649         return ret;
0650 
0651     ret = devm_request_irq(&spi->dev, spi->irq,
0652                    &ad7768_interrupt,
0653                    IRQF_TRIGGER_RISING | IRQF_ONESHOT,
0654                    indio_dev->name, indio_dev);
0655     if (ret)
0656         return ret;
0657 
0658     ret = devm_iio_triggered_buffer_setup(&spi->dev, indio_dev,
0659                           &iio_pollfunc_store_time,
0660                           &ad7768_trigger_handler,
0661                           &ad7768_buffer_ops);
0662     if (ret)
0663         return ret;
0664 
0665     return devm_iio_device_register(&spi->dev, indio_dev);
0666 }
0667 
0668 static const struct spi_device_id ad7768_id_table[] = {
0669     { "ad7768-1", 0 },
0670     {}
0671 };
0672 MODULE_DEVICE_TABLE(spi, ad7768_id_table);
0673 
0674 static const struct of_device_id ad7768_of_match[] = {
0675     { .compatible = "adi,ad7768-1" },
0676     { },
0677 };
0678 MODULE_DEVICE_TABLE(of, ad7768_of_match);
0679 
0680 static struct spi_driver ad7768_driver = {
0681     .driver = {
0682         .name = "ad7768-1",
0683         .of_match_table = ad7768_of_match,
0684     },
0685     .probe = ad7768_probe,
0686     .id_table = ad7768_id_table,
0687 };
0688 module_spi_driver(ad7768_driver);
0689 
0690 MODULE_AUTHOR("Stefan Popa <stefan.popa@analog.com>");
0691 MODULE_DESCRIPTION("Analog Devices AD7768-1 ADC driver");
0692 MODULE_LICENSE("GPL v2");
[ Source navigation ] [ Diff markup ] [ Identifier search ] [ general search ]

This page was automatically generated by the 2.1.0 LXR engine.

The LXR team
Valid CSS 2.1! Valid HTML 4.01!