iio/adc/ad7476.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Analog Devices AD7466/7/8 AD7476/5/7/8 (A) SPI ADC driver
0004  * TI ADC081S/ADC101S/ADC121S 8/10/12-bit SPI ADC driver
0005  *
0006  * Copyright 2010 Analog Devices Inc.
0007  */
0008
0009 #include <linux/device.h>
0010 #include <linux/kernel.h>
0011 #include <linux/slab.h>
0012 #include <linux/sysfs.h>
0013 #include <linux/spi/spi.h>
0014 #include <linux/regulator/consumer.h>
0015 #include <linux/gpio/consumer.h>
0016 #include <linux/err.h>
0017 #include <linux/module.h>
0018 #include <linux/bitops.h>
0019 #include <linux/delay.h>
0020
0021 #include <linux/iio/iio.h>
0022 #include <linux/iio/sysfs.h>
0023 #include <linux/iio/buffer.h>
0024 #include <linux/iio/trigger_consumer.h>
0025 #include <linux/iio/triggered_buffer.h>
0026
0027 struct ad7476_state;
0028
0029 struct ad7476_chip_info {
0030     unsigned int            int_vref_uv;
0031     struct iio_chan_spec        channel[2];
0032     /* channels used when convst gpio is defined */
0033     struct iio_chan_spec        convst_channel[2];
0034     void (*reset)(struct ad7476_state *);
0035     bool                has_vref;
0036     bool                has_vdrive;
0037 };
0038
0039 struct ad7476_state {
0040     struct spi_device       *spi;
0041     const struct ad7476_chip_info   *chip_info;
0042     struct regulator        *ref_reg;
0043     struct gpio_desc        *convst_gpio;
0044     struct spi_transfer     xfer;
0045     struct spi_message      msg;
0046     /*
0047      * DMA (thus cache coherency maintenance) may require the
0048      * transfer buffers to live in their own cache lines.
0049      * Make the buffer large enough for one 16 bit sample and one 64 bit
0050      * aligned 64 bit timestamp.
0051      */
0052     unsigned char data[ALIGN(2, sizeof(s64)) + sizeof(s64)] __aligned(IIO_DMA_MINALIGN);
0053 };
0054
0055 enum ad7476_supported_device_ids {
0056     ID_AD7091,
0057     ID_AD7091R,
0058     ID_AD7273,
0059     ID_AD7274,
0060     ID_AD7276,
0061     ID_AD7277,
0062     ID_AD7278,
0063     ID_AD7466,
0064     ID_AD7467,
0065     ID_AD7468,
0066     ID_AD7475,
0067     ID_AD7495,
0068     ID_AD7940,
0069     ID_ADC081S,
0070     ID_ADC101S,
0071     ID_ADC121S,
0072     ID_ADS7866,
0073     ID_ADS7867,
0074     ID_ADS7868,
0075     ID_LTC2314_14,
0076 };
0077
0078 static void ad7091_convst(struct ad7476_state *st)
0079 {
0080     if (!st->convst_gpio)
0081         return;
0082
0083     gpiod_set_value(st->convst_gpio, 0);
0084     udelay(1); /* CONVST pulse width: 10 ns min */
0085     gpiod_set_value(st->convst_gpio, 1);
0086     udelay(1); /* Conversion time: 650 ns max */
0087 }
0088
0089 static irqreturn_t ad7476_trigger_handler(int irq, void  *p)
0090 {
0091     struct iio_poll_func *pf = p;
0092     struct iio_dev *indio_dev = pf->indio_dev;
0093     struct ad7476_state *st = iio_priv(indio_dev);
0094     int b_sent;
0095
0096     ad7091_convst(st);
0097
0098     b_sent = spi_sync(st->spi, &st->msg);
0099     if (b_sent < 0)
0100         goto done;
0101
0102     iio_push_to_buffers_with_timestamp(indio_dev, st->data,
0103         iio_get_time_ns(indio_dev));
0104 done:
0105     iio_trigger_notify_done(indio_dev->trig);
0106
0107     return IRQ_HANDLED;
0108 }
0109
0110 static void ad7091_reset(struct ad7476_state *st)
0111 {
0112     /* Any transfers with 8 scl cycles will reset the device */
0113     spi_read(st->spi, st->data, 1);
0114 }
0115
0116 static int ad7476_scan_direct(struct ad7476_state *st)
0117 {
0118     int ret;
0119
0120     ad7091_convst(st);
0121
0122     ret = spi_sync(st->spi, &st->msg);
0123     if (ret)
0124         return ret;
0125
0126     return be16_to_cpup((__be16 *)st->data);
0127 }
0128
0129 static int ad7476_read_raw(struct iio_dev *indio_dev,
0130                struct iio_chan_spec const *chan,
0131                int *val,
0132                int *val2,
0133                long m)
0134 {
0135     int ret;
0136     struct ad7476_state *st = iio_priv(indio_dev);
0137     int scale_uv;
0138
0139     switch (m) {
0140     case IIO_CHAN_INFO_RAW:
0141         ret = iio_device_claim_direct_mode(indio_dev);
0142         if (ret)
0143             return ret;
0144         ret = ad7476_scan_direct(st);
0145         iio_device_release_direct_mode(indio_dev);
0146
0147         if (ret < 0)
0148             return ret;
0149         *val = (ret >> st->chip_info->channel[0].scan_type.shift) &
0150             GENMASK(st->chip_info->channel[0].scan_type.realbits - 1, 0);
0151         return IIO_VAL_INT;
0152     case IIO_CHAN_INFO_SCALE:
0153         if (st->ref_reg) {
0154             scale_uv = regulator_get_voltage(st->ref_reg);
0155             if (scale_uv < 0)
0156                 return scale_uv;
0157         } else {
0158             scale_uv = st->chip_info->int_vref_uv;
0159         }
0160         *val = scale_uv / 1000;
0161         *val2 = chan->scan_type.realbits;
0162         return IIO_VAL_FRACTIONAL_LOG2;
0163     }
0164     return -EINVAL;
0165 }
0166
0167 #define _AD7476_CHAN(bits, _shift, _info_mask_sep)      \
0168     {                           \
0169     .type = IIO_VOLTAGE,                    \
0170     .indexed = 1,                       \
0171     .info_mask_separate = _info_mask_sep,           \
0172     .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),   \
0173     .scan_type = {                      \
0174         .sign = 'u',                    \
0175         .realbits = (bits),             \
0176         .storagebits = 16,              \
0177         .shift = (_shift),              \
0178         .endianness = IIO_BE,               \
0179     },                          \
0180 }
0181
0182 #define ADC081S_CHAN(bits) _AD7476_CHAN((bits), 12 - (bits), \
0183         BIT(IIO_CHAN_INFO_RAW))
0184 #define AD7476_CHAN(bits) _AD7476_CHAN((bits), 13 - (bits), \
0185         BIT(IIO_CHAN_INFO_RAW))
0186 #define AD7940_CHAN(bits) _AD7476_CHAN((bits), 15 - (bits), \
0187         BIT(IIO_CHAN_INFO_RAW))
0188 #define AD7091R_CHAN(bits) _AD7476_CHAN((bits), 16 - (bits), 0)
0189 #define AD7091R_CONVST_CHAN(bits) _AD7476_CHAN((bits), 16 - (bits), \
0190         BIT(IIO_CHAN_INFO_RAW))
0191 #define ADS786X_CHAN(bits) _AD7476_CHAN((bits), 12 - (bits), \
0192         BIT(IIO_CHAN_INFO_RAW))
0193
0194 static const struct ad7476_chip_info ad7476_chip_info_tbl[] = {
0195     [ID_AD7091] = {
0196         .channel[0] = AD7091R_CHAN(12),
0197         .channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
0198         .convst_channel[0] = AD7091R_CONVST_CHAN(12),
0199         .convst_channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
0200         .reset = ad7091_reset,
0201     },
0202     [ID_AD7091R] = {
0203         .channel[0] = AD7091R_CHAN(12),
0204         .channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
0205         .convst_channel[0] = AD7091R_CONVST_CHAN(12),
0206         .convst_channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
0207         .int_vref_uv = 2500000,
0208         .has_vref = true,
0209         .reset = ad7091_reset,
0210     },
0211     [ID_AD7273] = {
0212         .channel[0] = AD7940_CHAN(10),
0213         .channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
0214         .has_vref = true,
0215     },
0216     [ID_AD7274] = {
0217         .channel[0] = AD7940_CHAN(12),
0218         .channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
0219         .has_vref = true,
0220     },
0221     [ID_AD7276] = {
0222         .channel[0] = AD7940_CHAN(12),
0223         .channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
0224     },
0225     [ID_AD7277] = {
0226         .channel[0] = AD7940_CHAN(10),
0227         .channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
0228     },
0229     [ID_AD7278] = {
0230         .channel[0] = AD7940_CHAN(8),
0231         .channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
0232     },
0233     [ID_AD7466] = {
0234         .channel[0] = AD7476_CHAN(12),
0235         .channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
0236     },
0237     [ID_AD7467] = {
0238         .channel[0] = AD7476_CHAN(10),
0239         .channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
0240     },
0241     [ID_AD7468] = {
0242         .channel[0] = AD7476_CHAN(8),
0243         .channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
0244     },
0245     [ID_AD7475] = {
0246         .channel[0] = AD7476_CHAN(12),
0247         .channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
0248         .has_vref = true,
0249         .has_vdrive = true,
0250     },
0251     [ID_AD7495] = {
0252         .channel[0] = AD7476_CHAN(12),
0253         .channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
0254         .int_vref_uv = 2500000,
0255         .has_vdrive = true,
0256     },
0257     [ID_AD7940] = {
0258         .channel[0] = AD7940_CHAN(14),
0259         .channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
0260     },
0261     [ID_ADC081S] = {
0262         .channel[0] = ADC081S_CHAN(8),
0263         .channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
0264     },
0265     [ID_ADC101S] = {
0266         .channel[0] = ADC081S_CHAN(10),
0267         .channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
0268     },
0269     [ID_ADC121S] = {
0270         .channel[0] = ADC081S_CHAN(12),
0271         .channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
0272     },
0273     [ID_ADS7866] = {
0274         .channel[0] = ADS786X_CHAN(12),
0275         .channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
0276     },
0277     [ID_ADS7867] = {
0278         .channel[0] = ADS786X_CHAN(10),
0279         .channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
0280     },
0281     [ID_ADS7868] = {
0282         .channel[0] = ADS786X_CHAN(8),
0283         .channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
0284     },
0285     [ID_LTC2314_14] = {
0286         .channel[0] = AD7940_CHAN(14),
0287         .channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
0288         .has_vref = true,
0289     },
0290 };
0291
0292 static const struct iio_info ad7476_info = {
0293     .read_raw = &ad7476_read_raw,
0294 };
0295
0296 static void ad7476_reg_disable(void *data)
0297 {
0298     struct regulator *reg = data;
0299
0300     regulator_disable(reg);
0301 }
0302
0303 static int ad7476_probe(struct spi_device *spi)
0304 {
0305     struct ad7476_state *st;
0306     struct iio_dev *indio_dev;
0307     struct regulator *reg;
0308     int ret;
0309
0310     indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
0311     if (!indio_dev)
0312         return -ENOMEM;
0313
0314     st = iio_priv(indio_dev);
0315     st->chip_info =
0316         &ad7476_chip_info_tbl[spi_get_device_id(spi)->driver_data];
0317
0318     reg = devm_regulator_get(&spi->dev, "vcc");
0319     if (IS_ERR(reg))
0320         return PTR_ERR(reg);
0321
0322     ret = regulator_enable(reg);
0323     if (ret)
0324         return ret;
0325
0326     ret = devm_add_action_or_reset(&spi->dev, ad7476_reg_disable, reg);
0327     if (ret)
0328         return ret;
0329
0330     /* Either vcc or vref (below) as appropriate */
0331     if (!st->chip_info->int_vref_uv)
0332         st->ref_reg = reg;
0333
0334     if (st->chip_info->has_vref) {
0335
0336         /* If a device has an internal reference vref is optional */
0337         if (st->chip_info->int_vref_uv) {
0338             reg = devm_regulator_get_optional(&spi->dev, "vref");
0339             if (IS_ERR(reg) && (PTR_ERR(reg) != -ENODEV))
0340                 return PTR_ERR(reg);
0341         } else {
0342             reg = devm_regulator_get(&spi->dev, "vref");
0343             if (IS_ERR(reg))
0344                 return PTR_ERR(reg);
0345         }
0346
0347         if (!IS_ERR(reg)) {
0348             ret = regulator_enable(reg);
0349             if (ret)
0350                 return ret;
0351
0352             ret = devm_add_action_or_reset(&spi->dev,
0353                                ad7476_reg_disable,
0354                                reg);
0355             if (ret)
0356                 return ret;
0357             st->ref_reg = reg;
0358         } else {
0359             /*
0360              * Can only get here if device supports both internal
0361              * and external reference, but the regulator connected
0362              * to the external reference is not connected.
0363              * Set the reference regulator pointer to NULL to
0364              * indicate this.
0365              */
0366             st->ref_reg = NULL;
0367         }
0368     }
0369
0370     if (st->chip_info->has_vdrive) {
0371         reg = devm_regulator_get(&spi->dev, "vdrive");
0372         if (IS_ERR(reg))
0373             return PTR_ERR(reg);
0374
0375         ret = regulator_enable(reg);
0376         if (ret)
0377             return ret;
0378
0379         ret = devm_add_action_or_reset(&spi->dev, ad7476_reg_disable,
0380                            reg);
0381         if (ret)
0382             return ret;
0383     }
0384
0385     st->convst_gpio = devm_gpiod_get_optional(&spi->dev,
0386                           "adi,conversion-start",
0387                           GPIOD_OUT_LOW);
0388     if (IS_ERR(st->convst_gpio))
0389         return PTR_ERR(st->convst_gpio);
0390
0391     st->spi = spi;
0392
0393     indio_dev->name = spi_get_device_id(spi)->name;
0394     indio_dev->modes = INDIO_DIRECT_MODE;
0395     indio_dev->channels = st->chip_info->channel;
0396     indio_dev->num_channels = 2;
0397     indio_dev->info = &ad7476_info;
0398
0399     if (st->convst_gpio)
0400         indio_dev->channels = st->chip_info->convst_channel;
0401     /* Setup default message */
0402
0403     st->xfer.rx_buf = &st->data;
0404     st->xfer.len = st->chip_info->channel[0].scan_type.storagebits / 8;
0405
0406     spi_message_init(&st->msg);
0407     spi_message_add_tail(&st->xfer, &st->msg);
0408
0409     ret = devm_iio_triggered_buffer_setup(&spi->dev, indio_dev, NULL,
0410                           &ad7476_trigger_handler, NULL);
0411     if (ret)
0412         return ret;
0413
0414     if (st->chip_info->reset)
0415         st->chip_info->reset(st);
0416
0417     return devm_iio_device_register(&spi->dev, indio_dev);
0418 }
0419
0420 static const struct spi_device_id ad7476_id[] = {
0421     {"ad7091", ID_AD7091},
0422     {"ad7091r", ID_AD7091R},
0423     {"ad7273", ID_AD7273},
0424     {"ad7274", ID_AD7274},
0425     {"ad7276", ID_AD7276},
0426     {"ad7277", ID_AD7277},
0427     {"ad7278", ID_AD7278},
0428     {"ad7466", ID_AD7466},
0429     {"ad7467", ID_AD7467},
0430     {"ad7468", ID_AD7468},
0431     {"ad7475", ID_AD7475},
0432     {"ad7476", ID_AD7466},
0433     {"ad7476a", ID_AD7466},
0434     {"ad7477", ID_AD7467},
0435     {"ad7477a", ID_AD7467},
0436     {"ad7478", ID_AD7468},
0437     {"ad7478a", ID_AD7468},
0438     {"ad7495", ID_AD7495},
0439     {"ad7910", ID_AD7467},
0440     {"ad7920", ID_AD7466},
0441     {"ad7940", ID_AD7940},
0442     {"adc081s", ID_ADC081S},
0443     {"adc101s", ID_ADC101S},
0444     {"adc121s", ID_ADC121S},
0445     {"ads7866", ID_ADS7866},
0446     {"ads7867", ID_ADS7867},
0447     {"ads7868", ID_ADS7868},
0448     {"ltc2314-14", ID_LTC2314_14},
0449     {}
0450 };
0451 MODULE_DEVICE_TABLE(spi, ad7476_id);
0452
0453 static struct spi_driver ad7476_driver = {
0454     .driver = {
0455         .name   = "ad7476",
0456     },
0457     .probe      = ad7476_probe,
0458     .id_table   = ad7476_id,
0459 };
0460 module_spi_driver(ad7476_driver);
0461
0462 MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>");
0463 MODULE_DESCRIPTION("Analog Devices AD7476 and similar 1-channel ADCs");
0464 MODULE_LICENSE("GPL v2");