iio/adc/ad7298.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * AD7298 SPI ADC driver
0004  *
0005  * Copyright 2011 Analog Devices Inc.
0006  */
0007
0008 #include <linux/device.h>
0009 #include <linux/kernel.h>
0010 #include <linux/slab.h>
0011 #include <linux/sysfs.h>
0012 #include <linux/spi/spi.h>
0013 #include <linux/regulator/consumer.h>
0014 #include <linux/err.h>
0015 #include <linux/delay.h>
0016 #include <linux/mod_devicetable.h>
0017 #include <linux/module.h>
0018 #include <linux/interrupt.h>
0019 #include <linux/bitops.h>
0020
0021 #include <linux/iio/iio.h>
0022 #include <linux/iio/sysfs.h>
0023 #include <linux/iio/buffer.h>
0024 #include <linux/iio/trigger_consumer.h>
0025 #include <linux/iio/triggered_buffer.h>
0026
0027 #define AD7298_WRITE    BIT(15) /* write to the control register */
0028 #define AD7298_REPEAT   BIT(14) /* repeated conversion enable */
0029 #define AD7298_CH(x)    BIT(13 - (x)) /* channel select */
0030 #define AD7298_TSENSE   BIT(5) /* temperature conversion enable */
0031 #define AD7298_EXTREF   BIT(2) /* external reference enable */
0032 #define AD7298_TAVG BIT(1) /* temperature sensor averaging enable */
0033 #define AD7298_PDD  BIT(0) /* partial power down enable */
0034
0035 #define AD7298_MAX_CHAN     8
0036 #define AD7298_INTREF_mV    2500
0037
0038 #define AD7298_CH_TEMP      9
0039
0040 struct ad7298_state {
0041     struct spi_device       *spi;
0042     struct regulator        *reg;
0043     unsigned            ext_ref;
0044     struct spi_transfer     ring_xfer[10];
0045     struct spi_transfer     scan_single_xfer[3];
0046     struct spi_message      ring_msg;
0047     struct spi_message      scan_single_msg;
0048     /*
0049      * DMA (thus cache coherency maintenance) requires the
0050      * transfer buffers to live in their own cache lines.
0051      */
0052     __be16              rx_buf[12] __aligned(IIO_DMA_MINALIGN);
0053     __be16              tx_buf[2];
0054 };
0055
0056 #define AD7298_V_CHAN(index)                        \
0057     {                               \
0058         .type = IIO_VOLTAGE,                    \
0059         .indexed = 1,                       \
0060         .channel = index,                   \
0061         .info_mask_separate = BIT(IIO_CHAN_INFO_RAW),       \
0062         .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),   \
0063         .address = index,                   \
0064         .scan_index = index,                    \
0065         .scan_type = {                      \
0066             .sign = 'u',                    \
0067             .realbits = 12,                 \
0068             .storagebits = 16,              \
0069             .endianness = IIO_BE,               \
0070         },                          \
0071     }
0072
0073 static const struct iio_chan_spec ad7298_channels[] = {
0074     {
0075         .type = IIO_TEMP,
0076         .indexed = 1,
0077         .channel = 0,
0078         .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
0079             BIT(IIO_CHAN_INFO_SCALE) |
0080             BIT(IIO_CHAN_INFO_OFFSET),
0081         .address = AD7298_CH_TEMP,
0082         .scan_index = -1,
0083         .scan_type = {
0084             .sign = 's',
0085             .realbits = 32,
0086             .storagebits = 32,
0087         },
0088     },
0089     AD7298_V_CHAN(0),
0090     AD7298_V_CHAN(1),
0091     AD7298_V_CHAN(2),
0092     AD7298_V_CHAN(3),
0093     AD7298_V_CHAN(4),
0094     AD7298_V_CHAN(5),
0095     AD7298_V_CHAN(6),
0096     AD7298_V_CHAN(7),
0097     IIO_CHAN_SOFT_TIMESTAMP(8),
0098 };
0099
0100 /*
0101  * ad7298_update_scan_mode() setup the spi transfer buffer for the new scan mask
0102  */
0103 static int ad7298_update_scan_mode(struct iio_dev *indio_dev,
0104     const unsigned long *active_scan_mask)
0105 {
0106     struct ad7298_state *st = iio_priv(indio_dev);
0107     int i, m;
0108     unsigned short command;
0109     int scan_count;
0110
0111     /* Now compute overall size */
0112     scan_count = bitmap_weight(active_scan_mask, indio_dev->masklength);
0113
0114     command = AD7298_WRITE | st->ext_ref;
0115
0116     for (i = 0, m = AD7298_CH(0); i < AD7298_MAX_CHAN; i++, m >>= 1)
0117         if (test_bit(i, active_scan_mask))
0118             command |= m;
0119
0120     st->tx_buf[0] = cpu_to_be16(command);
0121
0122     /* build spi ring message */
0123     st->ring_xfer[0].tx_buf = &st->tx_buf[0];
0124     st->ring_xfer[0].len = 2;
0125     st->ring_xfer[0].cs_change = 1;
0126     st->ring_xfer[1].tx_buf = &st->tx_buf[1];
0127     st->ring_xfer[1].len = 2;
0128     st->ring_xfer[1].cs_change = 1;
0129
0130     spi_message_init(&st->ring_msg);
0131     spi_message_add_tail(&st->ring_xfer[0], &st->ring_msg);
0132     spi_message_add_tail(&st->ring_xfer[1], &st->ring_msg);
0133
0134     for (i = 0; i < scan_count; i++) {
0135         st->ring_xfer[i + 2].rx_buf = &st->rx_buf[i];
0136         st->ring_xfer[i + 2].len = 2;
0137         st->ring_xfer[i + 2].cs_change = 1;
0138         spi_message_add_tail(&st->ring_xfer[i + 2], &st->ring_msg);
0139     }
0140     /* make sure last transfer cs_change is not set */
0141     st->ring_xfer[i + 1].cs_change = 0;
0142
0143     return 0;
0144 }
0145
0146 static irqreturn_t ad7298_trigger_handler(int irq, void *p)
0147 {
0148     struct iio_poll_func *pf = p;
0149     struct iio_dev *indio_dev = pf->indio_dev;
0150     struct ad7298_state *st = iio_priv(indio_dev);
0151     int b_sent;
0152
0153     b_sent = spi_sync(st->spi, &st->ring_msg);
0154     if (b_sent)
0155         goto done;
0156
0157     iio_push_to_buffers_with_timestamp(indio_dev, st->rx_buf,
0158         iio_get_time_ns(indio_dev));
0159
0160 done:
0161     iio_trigger_notify_done(indio_dev->trig);
0162
0163     return IRQ_HANDLED;
0164 }
0165
0166 static int ad7298_scan_direct(struct ad7298_state *st, unsigned ch)
0167 {
0168     int ret;
0169     st->tx_buf[0] = cpu_to_be16(AD7298_WRITE | st->ext_ref |
0170                    (AD7298_CH(0) >> ch));
0171
0172     ret = spi_sync(st->spi, &st->scan_single_msg);
0173     if (ret)
0174         return ret;
0175
0176     return be16_to_cpu(st->rx_buf[0]);
0177 }
0178
0179 static int ad7298_scan_temp(struct ad7298_state *st, int *val)
0180 {
0181     int ret;
0182     __be16 buf;
0183
0184     buf = cpu_to_be16(AD7298_WRITE | AD7298_TSENSE |
0185               AD7298_TAVG | st->ext_ref);
0186
0187     ret = spi_write(st->spi, (u8 *)&buf, 2);
0188     if (ret)
0189         return ret;
0190
0191     buf = cpu_to_be16(0);
0192
0193     ret = spi_write(st->spi, (u8 *)&buf, 2);
0194     if (ret)
0195         return ret;
0196
0197     usleep_range(101, 1000); /* sleep > 100us */
0198
0199     ret = spi_read(st->spi, (u8 *)&buf, 2);
0200     if (ret)
0201         return ret;
0202
0203     *val = sign_extend32(be16_to_cpu(buf), 11);
0204
0205     return 0;
0206 }
0207
0208 static int ad7298_get_ref_voltage(struct ad7298_state *st)
0209 {
0210     int vref;
0211
0212     if (st->reg) {
0213         vref = regulator_get_voltage(st->reg);
0214         if (vref < 0)
0215             return vref;
0216
0217         return vref / 1000;
0218     } else {
0219         return AD7298_INTREF_mV;
0220     }
0221 }
0222
0223 static int ad7298_read_raw(struct iio_dev *indio_dev,
0224                struct iio_chan_spec const *chan,
0225                int *val,
0226                int *val2,
0227                long m)
0228 {
0229     int ret;
0230     struct ad7298_state *st = iio_priv(indio_dev);
0231
0232     switch (m) {
0233     case IIO_CHAN_INFO_RAW:
0234         ret = iio_device_claim_direct_mode(indio_dev);
0235         if (ret)
0236             return ret;
0237
0238         if (chan->address == AD7298_CH_TEMP)
0239             ret = ad7298_scan_temp(st, val);
0240         else
0241             ret = ad7298_scan_direct(st, chan->address);
0242
0243         iio_device_release_direct_mode(indio_dev);
0244
0245         if (ret < 0)
0246             return ret;
0247
0248         if (chan->address != AD7298_CH_TEMP)
0249             *val = ret & GENMASK(chan->scan_type.realbits - 1, 0);
0250
0251         return IIO_VAL_INT;
0252     case IIO_CHAN_INFO_SCALE:
0253         switch (chan->type) {
0254         case IIO_VOLTAGE:
0255             *val = ad7298_get_ref_voltage(st);
0256             *val2 = chan->scan_type.realbits;
0257             return IIO_VAL_FRACTIONAL_LOG2;
0258         case IIO_TEMP:
0259             *val = ad7298_get_ref_voltage(st);
0260             *val2 = 10;
0261             return IIO_VAL_FRACTIONAL;
0262         default:
0263             return -EINVAL;
0264         }
0265     case IIO_CHAN_INFO_OFFSET:
0266         *val = 1093 - 2732500 / ad7298_get_ref_voltage(st);
0267         return IIO_VAL_INT;
0268     }
0269     return -EINVAL;
0270 }
0271
0272 static const struct iio_info ad7298_info = {
0273     .read_raw = &ad7298_read_raw,
0274     .update_scan_mode = ad7298_update_scan_mode,
0275 };
0276
0277 static void ad7298_reg_disable(void *data)
0278 {
0279     struct regulator *reg = data;
0280
0281     regulator_disable(reg);
0282 }
0283
0284 static int ad7298_probe(struct spi_device *spi)
0285 {
0286     struct ad7298_state *st;
0287     struct iio_dev *indio_dev;
0288     int ret;
0289
0290     indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
0291     if (indio_dev == NULL)
0292         return -ENOMEM;
0293
0294     st = iio_priv(indio_dev);
0295
0296     st->reg = devm_regulator_get_optional(&spi->dev, "vref");
0297     if (!IS_ERR(st->reg)) {
0298         st->ext_ref = AD7298_EXTREF;
0299     } else {
0300         ret = PTR_ERR(st->reg);
0301         if (ret != -ENODEV)
0302             return ret;
0303
0304         st->reg = NULL;
0305     }
0306
0307     if (st->reg) {
0308         ret = regulator_enable(st->reg);
0309         if (ret)
0310             return ret;
0311
0312         ret = devm_add_action_or_reset(&spi->dev, ad7298_reg_disable,
0313                            st->reg);
0314         if (ret)
0315             return ret;
0316     }
0317
0318     st->spi = spi;
0319
0320     indio_dev->name = spi_get_device_id(spi)->name;
0321     indio_dev->modes = INDIO_DIRECT_MODE;
0322     indio_dev->channels = ad7298_channels;
0323     indio_dev->num_channels = ARRAY_SIZE(ad7298_channels);
0324     indio_dev->info = &ad7298_info;
0325
0326     /* Setup default message */
0327
0328     st->scan_single_xfer[0].tx_buf = &st->tx_buf[0];
0329     st->scan_single_xfer[0].len = 2;
0330     st->scan_single_xfer[0].cs_change = 1;
0331     st->scan_single_xfer[1].tx_buf = &st->tx_buf[1];
0332     st->scan_single_xfer[1].len = 2;
0333     st->scan_single_xfer[1].cs_change = 1;
0334     st->scan_single_xfer[2].rx_buf = &st->rx_buf[0];
0335     st->scan_single_xfer[2].len = 2;
0336
0337     spi_message_init(&st->scan_single_msg);
0338     spi_message_add_tail(&st->scan_single_xfer[0], &st->scan_single_msg);
0339     spi_message_add_tail(&st->scan_single_xfer[1], &st->scan_single_msg);
0340     spi_message_add_tail(&st->scan_single_xfer[2], &st->scan_single_msg);
0341
0342     ret = devm_iio_triggered_buffer_setup(&spi->dev, indio_dev, NULL,
0343             &ad7298_trigger_handler, NULL);
0344     if (ret)
0345         return ret;
0346
0347     return devm_iio_device_register(&spi->dev, indio_dev);
0348 }
0349
0350 static const struct acpi_device_id ad7298_acpi_ids[] = {
0351     { "INT3494", 0 },
0352     { }
0353 };
0354 MODULE_DEVICE_TABLE(acpi, ad7298_acpi_ids);
0355
0356 static const struct spi_device_id ad7298_id[] = {
0357     {"ad7298", 0},
0358     {}
0359 };
0360 MODULE_DEVICE_TABLE(spi, ad7298_id);
0361
0362 static struct spi_driver ad7298_driver = {
0363     .driver = {
0364         .name   = "ad7298",
0365         .acpi_match_table = ad7298_acpi_ids,
0366     },
0367     .probe      = ad7298_probe,
0368     .id_table   = ad7298_id,
0369 };
0370 module_spi_driver(ad7298_driver);
0371
0372 MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>");
0373 MODULE_DESCRIPTION("Analog Devices AD7298 ADC");
0374 MODULE_LICENSE("GPL v2");