iio/adc/ad7292.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Analog Devices AD7292 SPI ADC driver
0004  *
0005  * Copyright 2019 Analog Devices Inc.
0006  */
0007
0008 #include <linux/bitfield.h>
0009 #include <linux/device.h>
0010 #include <linux/module.h>
0011 #include <linux/regulator/consumer.h>
0012 #include <linux/spi/spi.h>
0013
0014 #include <linux/iio/iio.h>
0015
0016 #define ADI_VENDOR_ID 0x0018
0017
0018 /* AD7292 registers definition */
0019 #define AD7292_REG_VENDOR_ID        0x00
0020 #define AD7292_REG_CONF_BANK        0x05
0021 #define AD7292_REG_CONV_COMM        0x0E
0022 #define AD7292_REG_ADC_CH(x)        (0x10 + (x))
0023
0024 /* AD7292 configuration bank subregisters definition */
0025 #define AD7292_BANK_REG_VIN_RNG0    0x10
0026 #define AD7292_BANK_REG_VIN_RNG1    0x11
0027 #define AD7292_BANK_REG_SAMP_MODE   0x12
0028
0029 #define AD7292_RD_FLAG_MSK(x)       (BIT(7) | ((x) & 0x3F))
0030
0031 /* AD7292_REG_ADC_CONVERSION */
0032 #define AD7292_ADC_DATA_MASK        GENMASK(15, 6)
0033 #define AD7292_ADC_DATA(x)      FIELD_GET(AD7292_ADC_DATA_MASK, x)
0034
0035 /* AD7292_CHANNEL_SAMPLING_MODE */
0036 #define AD7292_CH_SAMP_MODE(reg, ch)    (((reg) >> 8) & BIT(ch))
0037
0038 /* AD7292_CHANNEL_VIN_RANGE */
0039 #define AD7292_CH_VIN_RANGE(reg, ch)    ((reg) & BIT(ch))
0040
0041 #define AD7292_VOLTAGE_CHAN(_chan)                  \
0042 {                                   \
0043     .type = IIO_VOLTAGE,                        \
0044     .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |          \
0045                   BIT(IIO_CHAN_INFO_SCALE),         \
0046     .indexed = 1,                           \
0047     .channel = _chan,                       \
0048 }
0049
0050 static const struct iio_chan_spec ad7292_channels[] = {
0051     AD7292_VOLTAGE_CHAN(0),
0052     AD7292_VOLTAGE_CHAN(1),
0053     AD7292_VOLTAGE_CHAN(2),
0054     AD7292_VOLTAGE_CHAN(3),
0055     AD7292_VOLTAGE_CHAN(4),
0056     AD7292_VOLTAGE_CHAN(5),
0057     AD7292_VOLTAGE_CHAN(6),
0058     AD7292_VOLTAGE_CHAN(7)
0059 };
0060
0061 static const struct iio_chan_spec ad7292_channels_diff[] = {
0062     {
0063         .type = IIO_VOLTAGE,
0064         .info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
0065         .indexed = 1,
0066         .differential = 1,
0067         .channel = 0,
0068         .channel2 = 1,
0069     },
0070     AD7292_VOLTAGE_CHAN(2),
0071     AD7292_VOLTAGE_CHAN(3),
0072     AD7292_VOLTAGE_CHAN(4),
0073     AD7292_VOLTAGE_CHAN(5),
0074     AD7292_VOLTAGE_CHAN(6),
0075     AD7292_VOLTAGE_CHAN(7)
0076 };
0077
0078 struct ad7292_state {
0079     struct spi_device *spi;
0080     struct regulator *reg;
0081     unsigned short vref_mv;
0082
0083     __be16 d16 __aligned(IIO_DMA_MINALIGN);
0084     u8 d8[2];
0085 };
0086
0087 static int ad7292_spi_reg_read(struct ad7292_state *st, unsigned int addr)
0088 {
0089     int ret;
0090
0091     st->d8[0] = AD7292_RD_FLAG_MSK(addr);
0092
0093     ret = spi_write_then_read(st->spi, st->d8, 1, &st->d16, 2);
0094     if (ret < 0)
0095         return ret;
0096
0097     return be16_to_cpu(st->d16);
0098 }
0099
0100 static int ad7292_spi_subreg_read(struct ad7292_state *st, unsigned int addr,
0101                   unsigned int sub_addr, unsigned int len)
0102 {
0103     unsigned int shift = 16 - (8 * len);
0104     int ret;
0105
0106     st->d8[0] = AD7292_RD_FLAG_MSK(addr);
0107     st->d8[1] = sub_addr;
0108
0109     ret = spi_write_then_read(st->spi, st->d8, 2, &st->d16, len);
0110     if (ret < 0)
0111         return ret;
0112
0113     return (be16_to_cpu(st->d16) >> shift);
0114 }
0115
0116 static int ad7292_single_conversion(struct ad7292_state *st,
0117                     unsigned int chan_addr)
0118 {
0119     int ret;
0120
0121     struct spi_transfer t[] = {
0122         {
0123             .tx_buf = &st->d8,
0124             .len = 4,
0125             .delay = {
0126                 .value = 6,
0127                 .unit = SPI_DELAY_UNIT_USECS
0128             },
0129         }, {
0130             .rx_buf = &st->d16,
0131             .len = 2,
0132         },
0133     };
0134
0135     st->d8[0] = chan_addr;
0136     st->d8[1] = AD7292_RD_FLAG_MSK(AD7292_REG_CONV_COMM);
0137
0138     ret = spi_sync_transfer(st->spi, t, ARRAY_SIZE(t));
0139
0140     if (ret < 0)
0141         return ret;
0142
0143     return be16_to_cpu(st->d16);
0144 }
0145
0146 static int ad7292_vin_range_multiplier(struct ad7292_state *st, int channel)
0147 {
0148     int samp_mode, range0, range1, factor = 1;
0149
0150     /*
0151      * Every AD7292 ADC channel may have its input range adjusted according
0152      * to the settings at the ADC sampling mode and VIN range subregisters.
0153      * For a given channel, the minimum input range is equal to Vref, and it
0154      * may be increased by a multiplier factor of 2 or 4 according to the
0155      * following rule:
0156      * If channel is being sampled with respect to AGND:
0157      *  factor = 4 if VIN range0 and VIN range1 equal 0
0158      *  factor = 2 if only one of VIN ranges equal 1
0159      *  factor = 1 if both VIN range0 and VIN range1 equal 1
0160      * If channel is being sampled with respect to AVDD:
0161      *  factor = 4 if VIN range0 and VIN range1 equal 0
0162      *  Behavior is undefined if any of VIN range doesn't equal 0
0163      */
0164
0165     samp_mode = ad7292_spi_subreg_read(st, AD7292_REG_CONF_BANK,
0166                        AD7292_BANK_REG_SAMP_MODE, 2);
0167
0168     if (samp_mode < 0)
0169         return samp_mode;
0170
0171     range0 = ad7292_spi_subreg_read(st, AD7292_REG_CONF_BANK,
0172                     AD7292_BANK_REG_VIN_RNG0, 2);
0173
0174     if (range0 < 0)
0175         return range0;
0176
0177     range1 = ad7292_spi_subreg_read(st, AD7292_REG_CONF_BANK,
0178                     AD7292_BANK_REG_VIN_RNG1, 2);
0179
0180     if (range1 < 0)
0181         return range1;
0182
0183     if (AD7292_CH_SAMP_MODE(samp_mode, channel)) {
0184         /* Sampling with respect to AGND */
0185         if (!AD7292_CH_VIN_RANGE(range0, channel))
0186             factor *= 2;
0187
0188         if (!AD7292_CH_VIN_RANGE(range1, channel))
0189             factor *= 2;
0190
0191     } else {
0192         /* Sampling with respect to AVDD */
0193         if (AD7292_CH_VIN_RANGE(range0, channel) ||
0194             AD7292_CH_VIN_RANGE(range1, channel))
0195             return -EPERM;
0196
0197         factor = 4;
0198     }
0199
0200     return factor;
0201 }
0202
0203 static int ad7292_read_raw(struct iio_dev *indio_dev,
0204                const struct iio_chan_spec *chan,
0205                int *val, int *val2, long info)
0206 {
0207     struct ad7292_state *st = iio_priv(indio_dev);
0208     unsigned int ch_addr;
0209     int ret;
0210
0211     switch (info) {
0212     case IIO_CHAN_INFO_RAW:
0213         ch_addr = AD7292_REG_ADC_CH(chan->channel);
0214         ret = ad7292_single_conversion(st, ch_addr);
0215         if (ret < 0)
0216             return ret;
0217
0218         *val = AD7292_ADC_DATA(ret);
0219
0220         return IIO_VAL_INT;
0221     case IIO_CHAN_INFO_SCALE:
0222         /*
0223          * To convert a raw value to standard units, the IIO defines
0224          * this formula: Scaled value = (raw + offset) * scale.
0225          * For the scale to be a correct multiplier for (raw + offset),
0226          * it must be calculated as the input range divided by the
0227          * number of possible distinct input values. Given the ADC data
0228          * is 10 bit long, it may assume 2^10 distinct values.
0229          * Hence, scale = range / 2^10. The IIO_VAL_FRACTIONAL_LOG2
0230          * return type indicates to the IIO API to divide *val by 2 to
0231          * the power of *val2 when returning from read_raw.
0232          */
0233
0234         ret = ad7292_vin_range_multiplier(st, chan->channel);
0235         if (ret < 0)
0236             return ret;
0237
0238         *val = st->vref_mv * ret;
0239         *val2 = 10;
0240         return IIO_VAL_FRACTIONAL_LOG2;
0241     default:
0242         break;
0243     }
0244     return -EINVAL;
0245 }
0246
0247 static const struct iio_info ad7292_info = {
0248     .read_raw = ad7292_read_raw,
0249 };
0250
0251 static void ad7292_regulator_disable(void *data)
0252 {
0253     struct ad7292_state *st = data;
0254
0255     regulator_disable(st->reg);
0256 }
0257
0258 static int ad7292_probe(struct spi_device *spi)
0259 {
0260     struct ad7292_state *st;
0261     struct iio_dev *indio_dev;
0262     struct device_node *child;
0263     bool diff_channels = false;
0264     int ret;
0265
0266     indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
0267     if (!indio_dev)
0268         return -ENOMEM;
0269
0270     st = iio_priv(indio_dev);
0271     st->spi = spi;
0272
0273     ret = ad7292_spi_reg_read(st, AD7292_REG_VENDOR_ID);
0274     if (ret != ADI_VENDOR_ID) {
0275         dev_err(&spi->dev, "Wrong vendor id 0x%x\n", ret);
0276         return -EINVAL;
0277     }
0278
0279     st->reg = devm_regulator_get_optional(&spi->dev, "vref");
0280     if (!IS_ERR(st->reg)) {
0281         ret = regulator_enable(st->reg);
0282         if (ret) {
0283             dev_err(&spi->dev,
0284                 "Failed to enable external vref supply\n");
0285             return ret;
0286         }
0287
0288         ret = devm_add_action_or_reset(&spi->dev,
0289                            ad7292_regulator_disable, st);
0290         if (ret)
0291             return ret;
0292
0293         ret = regulator_get_voltage(st->reg);
0294         if (ret < 0)
0295             return ret;
0296
0297         st->vref_mv = ret / 1000;
0298     } else {
0299         /* Use the internal voltage reference. */
0300         st->vref_mv = 1250;
0301     }
0302
0303     indio_dev->name = spi_get_device_id(spi)->name;
0304     indio_dev->modes = INDIO_DIRECT_MODE;
0305     indio_dev->info = &ad7292_info;
0306
0307     for_each_available_child_of_node(spi->dev.of_node, child) {
0308         diff_channels = of_property_read_bool(child, "diff-channels");
0309         if (diff_channels) {
0310             of_node_put(child);
0311             break;
0312         }
0313     }
0314
0315     if (diff_channels) {
0316         indio_dev->num_channels = ARRAY_SIZE(ad7292_channels_diff);
0317         indio_dev->channels = ad7292_channels_diff;
0318     } else {
0319         indio_dev->num_channels = ARRAY_SIZE(ad7292_channels);
0320         indio_dev->channels = ad7292_channels;
0321     }
0322
0323     return devm_iio_device_register(&spi->dev, indio_dev);
0324 }
0325
0326 static const struct spi_device_id ad7292_id_table[] = {
0327     { "ad7292", 0 },
0328     {}
0329 };
0330 MODULE_DEVICE_TABLE(spi, ad7292_id_table);
0331
0332 static const struct of_device_id ad7292_of_match[] = {
0333     { .compatible = "adi,ad7292" },
0334     { },
0335 };
0336 MODULE_DEVICE_TABLE(of, ad7292_of_match);
0337
0338 static struct spi_driver ad7292_driver = {
0339     .driver = {
0340         .name = "ad7292",
0341         .of_match_table = ad7292_of_match,
0342     },
0343     .probe = ad7292_probe,
0344     .id_table = ad7292_id_table,
0345 };
0346 module_spi_driver(ad7292_driver);
0347
0348 MODULE_AUTHOR("Marcelo Schmitt <marcelo.schmitt1@gmail.com>");
0349 MODULE_DESCRIPTION("Analog Devices AD7292 ADC driver");
0350 MODULE_LICENSE("GPL v2");