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0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * AD7280A Lithium Ion Battery Monitoring System
0004  *
0005  * Copyright 2011 Analog Devices Inc.
0006  */
0007 
0008 #include <linux/bitfield.h>
0009 #include <linux/bits.h>
0010 #include <linux/crc8.h>
0011 #include <linux/delay.h>
0012 #include <linux/device.h>
0013 #include <linux/err.h>
0014 #include <linux/interrupt.h>
0015 #include <linux/kernel.h>
0016 #include <linux/module.h>
0017 #include <linux/mod_devicetable.h>
0018 #include <linux/mutex.h>
0019 #include <linux/slab.h>
0020 #include <linux/sysfs.h>
0021 #include <linux/spi/spi.h>
0022 
0023 #include <linux/iio/events.h>
0024 #include <linux/iio/iio.h>
0025 
0026 /* Registers */
0027 
0028 #define AD7280A_CELL_VOLTAGE_1_REG      0x0  /* D11 to D0, Read only */
0029 #define AD7280A_CELL_VOLTAGE_2_REG      0x1  /* D11 to D0, Read only */
0030 #define AD7280A_CELL_VOLTAGE_3_REG      0x2  /* D11 to D0, Read only */
0031 #define AD7280A_CELL_VOLTAGE_4_REG      0x3  /* D11 to D0, Read only */
0032 #define AD7280A_CELL_VOLTAGE_5_REG      0x4  /* D11 to D0, Read only */
0033 #define AD7280A_CELL_VOLTAGE_6_REG      0x5  /* D11 to D0, Read only */
0034 #define AD7280A_AUX_ADC_1_REG           0x6  /* D11 to D0, Read only */
0035 #define AD7280A_AUX_ADC_2_REG           0x7  /* D11 to D0, Read only */
0036 #define AD7280A_AUX_ADC_3_REG           0x8  /* D11 to D0, Read only */
0037 #define AD7280A_AUX_ADC_4_REG           0x9  /* D11 to D0, Read only */
0038 #define AD7280A_AUX_ADC_5_REG           0xA  /* D11 to D0, Read only */
0039 #define AD7280A_AUX_ADC_6_REG           0xB  /* D11 to D0, Read only */
0040 #define AD7280A_SELF_TEST_REG           0xC  /* D11 to D0, Read only */
0041 
0042 #define AD7280A_CTRL_HB_REG         0xD  /* D15 to D8, Read/write */
0043 #define   AD7280A_CTRL_HB_CONV_INPUT_MSK        GENMASK(7, 6)
0044 #define     AD7280A_CTRL_HB_CONV_INPUT_ALL          0
0045 #define     AD7280A_CTRL_HB_CONV_INPUT_6CELL_AUX1_3_5       1
0046 #define     AD7280A_CTRL_HB_CONV_INPUT_6CELL            2
0047 #define     AD7280A_CTRL_HB_CONV_INPUT_SELF_TEST        3
0048 #define   AD7280A_CTRL_HB_CONV_RREAD_MSK        GENMASK(5, 4)
0049 #define     AD7280A_CTRL_HB_CONV_RREAD_ALL          0
0050 #define     AD7280A_CTRL_HB_CONV_RREAD_6CELL_AUX1_3_5       1
0051 #define     AD7280A_CTRL_HB_CONV_RREAD_6CELL            2
0052 #define     AD7280A_CTRL_HB_CONV_RREAD_NO               3
0053 #define   AD7280A_CTRL_HB_CONV_START_MSK        BIT(3)
0054 #define     AD7280A_CTRL_HB_CONV_START_CNVST            0
0055 #define     AD7280A_CTRL_HB_CONV_START_CS           1
0056 #define   AD7280A_CTRL_HB_CONV_AVG_MSK          GENMASK(2, 1)
0057 #define     AD7280A_CTRL_HB_CONV_AVG_DIS            0
0058 #define     AD7280A_CTRL_HB_CONV_AVG_2              1
0059 #define     AD7280A_CTRL_HB_CONV_AVG_4                  2
0060 #define     AD7280A_CTRL_HB_CONV_AVG_8                  3
0061 #define   AD7280A_CTRL_HB_PWRDN_SW          BIT(0)
0062 
0063 #define AD7280A_CTRL_LB_REG         0xE  /* D7 to D0, Read/write */
0064 #define   AD7280A_CTRL_LB_SWRST_MSK         BIT(7)
0065 #define   AD7280A_CTRL_LB_ACQ_TIME_MSK          GENMASK(6, 5)
0066 #define     AD7280A_CTRL_LB_ACQ_TIME_400ns          0
0067 #define     AD7280A_CTRL_LB_ACQ_TIME_800ns          1
0068 #define     AD7280A_CTRL_LB_ACQ_TIME_1200ns         2
0069 #define     AD7280A_CTRL_LB_ACQ_TIME_1600ns         3
0070 #define   AD7280A_CTRL_LB_MUST_SET          BIT(4)
0071 #define   AD7280A_CTRL_LB_THERMISTOR_MSK        BIT(3)
0072 #define   AD7280A_CTRL_LB_LOCK_DEV_ADDR_MSK     BIT(2)
0073 #define   AD7280A_CTRL_LB_INC_DEV_ADDR_MSK      BIT(1)
0074 #define   AD7280A_CTRL_LB_DAISY_CHAIN_RB_MSK        BIT(0)
0075 
0076 #define AD7280A_CELL_OVERVOLTAGE_REG        0xF  /* D7 to D0, Read/write */
0077 #define AD7280A_CELL_UNDERVOLTAGE_REG       0x10 /* D7 to D0, Read/write */
0078 #define AD7280A_AUX_ADC_OVERVOLTAGE_REG     0x11 /* D7 to D0, Read/write */
0079 #define AD7280A_AUX_ADC_UNDERVOLTAGE_REG    0x12 /* D7 to D0, Read/write */
0080 
0081 #define AD7280A_ALERT_REG           0x13 /* D7 to D0, Read/write */
0082 #define   AD7280A_ALERT_REMOVE_MSK          GENMASK(3, 0)
0083 #define     AD7280A_ALERT_REMOVE_AUX5           BIT(0)
0084 #define     AD7280A_ALERT_REMOVE_AUX3_AUX5      BIT(1)
0085 #define     AD7280A_ALERT_REMOVE_VIN5           BIT(2)
0086 #define     AD7280A_ALERT_REMOVE_VIN4_VIN5      BIT(3)
0087 #define   AD7280A_ALERT_GEN_STATIC_HIGH         BIT(6)
0088 #define   AD7280A_ALERT_RELAY_SIG_CHAIN_DOWN        (BIT(7) | BIT(6))
0089 
0090 #define AD7280A_CELL_BALANCE_REG        0x14 /* D7 to D0, Read/write */
0091 #define  AD7280A_CELL_BALANCE_CHAN_BITMAP_MSK       GENMASK(7, 2)
0092 #define AD7280A_CB1_TIMER_REG           0x15 /* D7 to D0, Read/write */
0093 #define  AD7280A_CB_TIMER_VAL_MSK           GENMASK(7, 3)
0094 #define AD7280A_CB2_TIMER_REG           0x16 /* D7 to D0, Read/write */
0095 #define AD7280A_CB3_TIMER_REG           0x17 /* D7 to D0, Read/write */
0096 #define AD7280A_CB4_TIMER_REG           0x18 /* D7 to D0, Read/write */
0097 #define AD7280A_CB5_TIMER_REG           0x19 /* D7 to D0, Read/write */
0098 #define AD7280A_CB6_TIMER_REG           0x1A /* D7 to D0, Read/write */
0099 #define AD7280A_PD_TIMER_REG            0x1B /* D7 to D0, Read/write */
0100 #define AD7280A_READ_REG            0x1C /* D7 to D0, Read/write */
0101 #define   AD7280A_READ_ADDR_MSK             GENMASK(7, 2)
0102 #define AD7280A_CNVST_CTRL_REG          0x1D /* D7 to D0, Read/write */
0103 
0104 /* Transfer fields */
0105 #define AD7280A_TRANS_WRITE_DEVADDR_MSK     GENMASK(31, 27)
0106 #define AD7280A_TRANS_WRITE_ADDR_MSK        GENMASK(26, 21)
0107 #define AD7280A_TRANS_WRITE_VAL_MSK     GENMASK(20, 13)
0108 #define AD7280A_TRANS_WRITE_ALL_MSK     BIT(12)
0109 #define AD7280A_TRANS_WRITE_CRC_MSK     GENMASK(10, 3)
0110 #define AD7280A_TRANS_WRITE_RES_PATTERN     0x2
0111 
0112 /* Layouts differ for channel vs other registers */
0113 #define AD7280A_TRANS_READ_DEVADDR_MSK      GENMASK(31, 27)
0114 #define AD7280A_TRANS_READ_CONV_CHANADDR_MSK    GENMASK(26, 23)
0115 #define AD7280A_TRANS_READ_CONV_DATA_MSK    GENMASK(22, 11)
0116 #define AD7280A_TRANS_READ_REG_REGADDR_MSK  GENMASK(26, 21)
0117 #define AD7280A_TRANS_READ_REG_DATA_MSK     GENMASK(20, 13)
0118 #define AD7280A_TRANS_READ_WRITE_ACK_MSK    BIT(10)
0119 #define AD7280A_TRANS_READ_CRC_MSK      GENMASK(9, 2)
0120 
0121 /* Magic value used to indicate this special case */
0122 #define AD7280A_ALL_CELLS               (0xAD << 16)
0123 
0124 #define AD7280A_MAX_SPI_CLK_HZ      700000 /* < 1MHz */
0125 #define AD7280A_MAX_CHAIN       8
0126 #define AD7280A_CELLS_PER_DEV       6
0127 #define AD7280A_BITS            12
0128 #define AD7280A_NUM_CH          (AD7280A_AUX_ADC_6_REG - \
0129                     AD7280A_CELL_VOLTAGE_1_REG + 1)
0130 
0131 #define AD7280A_CALC_VOLTAGE_CHAN_NUM(d, c) (((d) * AD7280A_CELLS_PER_DEV) + \
0132                          (c))
0133 #define AD7280A_CALC_TEMP_CHAN_NUM(d, c)    (((d) * AD7280A_CELLS_PER_DEV) + \
0134                          (c) - AD7280A_CELLS_PER_DEV)
0135 
0136 #define AD7280A_DEVADDR_MASTER      0
0137 #define AD7280A_DEVADDR_ALL     0x1F
0138 
0139 static const unsigned short ad7280a_n_avg[4] = {1, 2, 4, 8};
0140 static const unsigned short ad7280a_t_acq_ns[4] = {470, 1030, 1510, 1945};
0141 
0142 /* 5-bit device address is sent LSB first */
0143 static unsigned int ad7280a_devaddr(unsigned int addr)
0144 {
0145     return ((addr & 0x1) << 4) |
0146            ((addr & 0x2) << 2) |
0147            (addr & 0x4) |
0148            ((addr & 0x8) >> 2) |
0149            ((addr & 0x10) >> 4);
0150 }
0151 
0152 /*
0153  * During a read a valid write is mandatory.
0154  * So writing to the highest available address (Address 0x1F) and setting the
0155  * address all parts bit to 0 is recommended.
0156  * So the TXVAL is AD7280A_DEVADDR_ALL + CRC
0157  */
0158 #define AD7280A_READ_TXVAL  0xF800030A
0159 
0160 /*
0161  * AD7280 CRC
0162  *
0163  * P(x) = x^8 + x^5 + x^3 + x^2 + x^1 + x^0 = 0b100101111 => 0x2F
0164  */
0165 #define POLYNOM     0x2F
0166 
0167 struct ad7280_state {
0168     struct spi_device       *spi;
0169     struct iio_chan_spec        *channels;
0170     unsigned int            chain_last_alert_ignore;
0171     bool                thermistor_term_en;
0172     int             slave_num;
0173     int             scan_cnt;
0174     int             readback_delay_us;
0175     unsigned char           crc_tab[CRC8_TABLE_SIZE];
0176     u8              oversampling_ratio;
0177     u8              acquisition_time;
0178     unsigned char           ctrl_lb;
0179     unsigned char           cell_threshhigh;
0180     unsigned char           cell_threshlow;
0181     unsigned char           aux_threshhigh;
0182     unsigned char           aux_threshlow;
0183     unsigned char           cb_mask[AD7280A_MAX_CHAIN];
0184     struct mutex            lock; /* protect sensor state */
0185 
0186     __be32              tx __aligned(IIO_DMA_MINALIGN);
0187     __be32              rx;
0188 };
0189 
0190 static unsigned char ad7280_calc_crc8(unsigned char *crc_tab, unsigned int val)
0191 {
0192     unsigned char crc;
0193 
0194     crc = crc_tab[val >> 16 & 0xFF];
0195     crc = crc_tab[crc ^ (val >> 8 & 0xFF)];
0196 
0197     return crc ^ (val & 0xFF);
0198 }
0199 
0200 static int ad7280_check_crc(struct ad7280_state *st, unsigned int val)
0201 {
0202     unsigned char crc = ad7280_calc_crc8(st->crc_tab, val >> 10);
0203 
0204     if (crc != ((val >> 2) & 0xFF))
0205         return -EIO;
0206 
0207     return 0;
0208 }
0209 
0210 /*
0211  * After initiating a conversion sequence we need to wait until the conversion
0212  * is done. The delay is typically in the range of 15..30us however depending on
0213  * the number of devices in the daisy chain, the number of averages taken,
0214  * conversion delays and acquisition time options it may take up to 250us, in
0215  * this case we better sleep instead of busy wait.
0216  */
0217 
0218 static void ad7280_delay(struct ad7280_state *st)
0219 {
0220     if (st->readback_delay_us < 50)
0221         udelay(st->readback_delay_us);
0222     else
0223         usleep_range(250, 500);
0224 }
0225 
0226 static int __ad7280_read32(struct ad7280_state *st, unsigned int *val)
0227 {
0228     int ret;
0229     struct spi_transfer t = {
0230         .tx_buf = &st->tx,
0231         .rx_buf = &st->rx,
0232         .len = sizeof(st->tx),
0233     };
0234 
0235     st->tx = cpu_to_be32(AD7280A_READ_TXVAL);
0236 
0237     ret = spi_sync_transfer(st->spi, &t, 1);
0238     if (ret)
0239         return ret;
0240 
0241     *val = be32_to_cpu(st->rx);
0242 
0243     return 0;
0244 }
0245 
0246 static int ad7280_write(struct ad7280_state *st, unsigned int devaddr,
0247             unsigned int addr, bool all, unsigned int val)
0248 {
0249     unsigned int reg = FIELD_PREP(AD7280A_TRANS_WRITE_DEVADDR_MSK, devaddr) |
0250         FIELD_PREP(AD7280A_TRANS_WRITE_ADDR_MSK, addr) |
0251         FIELD_PREP(AD7280A_TRANS_WRITE_VAL_MSK, val) |
0252         FIELD_PREP(AD7280A_TRANS_WRITE_ALL_MSK, all);
0253 
0254     reg |= FIELD_PREP(AD7280A_TRANS_WRITE_CRC_MSK,
0255             ad7280_calc_crc8(st->crc_tab, reg >> 11));
0256     /* Reserved b010 pattern not included crc calc */
0257     reg |= AD7280A_TRANS_WRITE_RES_PATTERN;
0258 
0259     st->tx = cpu_to_be32(reg);
0260 
0261     return spi_write(st->spi, &st->tx, sizeof(st->tx));
0262 }
0263 
0264 static int ad7280_read_reg(struct ad7280_state *st, unsigned int devaddr,
0265                unsigned int addr)
0266 {
0267     int ret;
0268     unsigned int tmp;
0269 
0270     /* turns off the read operation on all parts */
0271     ret = ad7280_write(st, AD7280A_DEVADDR_MASTER, AD7280A_CTRL_HB_REG, 1,
0272                FIELD_PREP(AD7280A_CTRL_HB_CONV_INPUT_MSK,
0273                       AD7280A_CTRL_HB_CONV_INPUT_ALL) |
0274                FIELD_PREP(AD7280A_CTRL_HB_CONV_RREAD_MSK,
0275                       AD7280A_CTRL_HB_CONV_RREAD_NO) |
0276                FIELD_PREP(AD7280A_CTRL_HB_CONV_AVG_MSK,
0277                       st->oversampling_ratio));
0278     if (ret)
0279         return ret;
0280 
0281     /* turns on the read operation on the addressed part */
0282     ret = ad7280_write(st, devaddr, AD7280A_CTRL_HB_REG, 0,
0283                FIELD_PREP(AD7280A_CTRL_HB_CONV_INPUT_MSK,
0284                       AD7280A_CTRL_HB_CONV_INPUT_ALL) |
0285                FIELD_PREP(AD7280A_CTRL_HB_CONV_RREAD_MSK,
0286                       AD7280A_CTRL_HB_CONV_RREAD_ALL) |
0287                FIELD_PREP(AD7280A_CTRL_HB_CONV_AVG_MSK,
0288                       st->oversampling_ratio));
0289     if (ret)
0290         return ret;
0291 
0292     /* Set register address on the part to be read from */
0293     ret = ad7280_write(st, devaddr, AD7280A_READ_REG, 0,
0294                FIELD_PREP(AD7280A_READ_ADDR_MSK, addr));
0295     if (ret)
0296         return ret;
0297 
0298     ret = __ad7280_read32(st, &tmp);
0299     if (ret)
0300         return ret;
0301 
0302     if (ad7280_check_crc(st, tmp))
0303         return -EIO;
0304 
0305     if ((FIELD_GET(AD7280A_TRANS_READ_DEVADDR_MSK, tmp) != devaddr) ||
0306         (FIELD_GET(AD7280A_TRANS_READ_REG_REGADDR_MSK, tmp) != addr))
0307         return -EFAULT;
0308 
0309     return FIELD_GET(AD7280A_TRANS_READ_REG_DATA_MSK, tmp);
0310 }
0311 
0312 static int ad7280_read_channel(struct ad7280_state *st, unsigned int devaddr,
0313                    unsigned int addr)
0314 {
0315     int ret;
0316     unsigned int tmp;
0317 
0318     ret = ad7280_write(st, devaddr, AD7280A_READ_REG, 0,
0319                FIELD_PREP(AD7280A_READ_ADDR_MSK, addr));
0320     if (ret)
0321         return ret;
0322 
0323     ret = ad7280_write(st, AD7280A_DEVADDR_MASTER, AD7280A_CTRL_HB_REG, 1,
0324                FIELD_PREP(AD7280A_CTRL_HB_CONV_INPUT_MSK,
0325                       AD7280A_CTRL_HB_CONV_INPUT_ALL) |
0326                FIELD_PREP(AD7280A_CTRL_HB_CONV_RREAD_MSK,
0327                       AD7280A_CTRL_HB_CONV_RREAD_NO) |
0328                FIELD_PREP(AD7280A_CTRL_HB_CONV_AVG_MSK,
0329                       st->oversampling_ratio));
0330     if (ret)
0331         return ret;
0332 
0333     ret = ad7280_write(st, devaddr, AD7280A_CTRL_HB_REG, 0,
0334                FIELD_PREP(AD7280A_CTRL_HB_CONV_INPUT_MSK,
0335                       AD7280A_CTRL_HB_CONV_INPUT_ALL) |
0336                FIELD_PREP(AD7280A_CTRL_HB_CONV_RREAD_MSK,
0337                       AD7280A_CTRL_HB_CONV_RREAD_ALL) |
0338                FIELD_PREP(AD7280A_CTRL_HB_CONV_START_MSK,
0339                       AD7280A_CTRL_HB_CONV_START_CS) |
0340                FIELD_PREP(AD7280A_CTRL_HB_CONV_AVG_MSK,
0341                       st->oversampling_ratio));
0342     if (ret)
0343         return ret;
0344 
0345     ad7280_delay(st);
0346 
0347     ret = __ad7280_read32(st, &tmp);
0348     if (ret)
0349         return ret;
0350 
0351     if (ad7280_check_crc(st, tmp))
0352         return -EIO;
0353 
0354     if ((FIELD_GET(AD7280A_TRANS_READ_DEVADDR_MSK, tmp) != devaddr) ||
0355         (FIELD_GET(AD7280A_TRANS_READ_CONV_CHANADDR_MSK, tmp) != addr))
0356         return -EFAULT;
0357 
0358     return FIELD_GET(AD7280A_TRANS_READ_CONV_DATA_MSK, tmp);
0359 }
0360 
0361 static int ad7280_read_all_channels(struct ad7280_state *st, unsigned int cnt,
0362                     unsigned int *array)
0363 {
0364     int i, ret;
0365     unsigned int tmp, sum = 0;
0366 
0367     ret = ad7280_write(st, AD7280A_DEVADDR_MASTER, AD7280A_READ_REG, 1,
0368                AD7280A_CELL_VOLTAGE_1_REG << 2);
0369     if (ret)
0370         return ret;
0371 
0372     ret = ad7280_write(st, AD7280A_DEVADDR_MASTER, AD7280A_CTRL_HB_REG, 1,
0373                FIELD_PREP(AD7280A_CTRL_HB_CONV_INPUT_MSK,
0374                       AD7280A_CTRL_HB_CONV_INPUT_ALL) |
0375                FIELD_PREP(AD7280A_CTRL_HB_CONV_RREAD_MSK,
0376                       AD7280A_CTRL_HB_CONV_RREAD_ALL) |
0377                FIELD_PREP(AD7280A_CTRL_HB_CONV_START_MSK,
0378                       AD7280A_CTRL_HB_CONV_START_CS) |
0379                FIELD_PREP(AD7280A_CTRL_HB_CONV_AVG_MSK,
0380                       st->oversampling_ratio));
0381     if (ret)
0382         return ret;
0383 
0384     ad7280_delay(st);
0385 
0386     for (i = 0; i < cnt; i++) {
0387         ret = __ad7280_read32(st, &tmp);
0388         if (ret)
0389             return ret;
0390 
0391         if (ad7280_check_crc(st, tmp))
0392             return -EIO;
0393 
0394         if (array)
0395             array[i] = tmp;
0396         /* only sum cell voltages */
0397         if (FIELD_GET(AD7280A_TRANS_READ_CONV_CHANADDR_MSK, tmp) <=
0398             AD7280A_CELL_VOLTAGE_6_REG)
0399             sum += FIELD_GET(AD7280A_TRANS_READ_CONV_DATA_MSK, tmp);
0400     }
0401 
0402     return sum;
0403 }
0404 
0405 static void ad7280_sw_power_down(void *data)
0406 {
0407     struct ad7280_state *st = data;
0408 
0409     ad7280_write(st, AD7280A_DEVADDR_MASTER, AD7280A_CTRL_HB_REG, 1,
0410              AD7280A_CTRL_HB_PWRDN_SW |
0411              FIELD_PREP(AD7280A_CTRL_HB_CONV_AVG_MSK, st->oversampling_ratio));
0412 }
0413 
0414 static int ad7280_chain_setup(struct ad7280_state *st)
0415 {
0416     unsigned int val, n;
0417     int ret;
0418 
0419     ret = ad7280_write(st, AD7280A_DEVADDR_MASTER, AD7280A_CTRL_LB_REG, 1,
0420                FIELD_PREP(AD7280A_CTRL_LB_DAISY_CHAIN_RB_MSK, 1) |
0421                FIELD_PREP(AD7280A_CTRL_LB_LOCK_DEV_ADDR_MSK, 1) |
0422                AD7280A_CTRL_LB_MUST_SET |
0423                FIELD_PREP(AD7280A_CTRL_LB_SWRST_MSK, 1) |
0424                st->ctrl_lb);
0425     if (ret)
0426         return ret;
0427 
0428     ret = ad7280_write(st, AD7280A_DEVADDR_MASTER, AD7280A_CTRL_LB_REG, 1,
0429                FIELD_PREP(AD7280A_CTRL_LB_DAISY_CHAIN_RB_MSK, 1) |
0430                FIELD_PREP(AD7280A_CTRL_LB_LOCK_DEV_ADDR_MSK, 1) |
0431                AD7280A_CTRL_LB_MUST_SET |
0432                FIELD_PREP(AD7280A_CTRL_LB_SWRST_MSK, 0) |
0433                st->ctrl_lb);
0434     if (ret)
0435         goto error_power_down;
0436 
0437     ret = ad7280_write(st, AD7280A_DEVADDR_MASTER, AD7280A_READ_REG, 1,
0438                FIELD_PREP(AD7280A_READ_ADDR_MSK, AD7280A_CTRL_LB_REG));
0439     if (ret)
0440         goto error_power_down;
0441 
0442     for (n = 0; n <= AD7280A_MAX_CHAIN; n++) {
0443         ret = __ad7280_read32(st, &val);
0444         if (ret)
0445             goto error_power_down;
0446 
0447         if (val == 0)
0448             return n - 1;
0449 
0450         if (ad7280_check_crc(st, val)) {
0451             ret = -EIO;
0452             goto error_power_down;
0453         }
0454 
0455         if (n != ad7280a_devaddr(FIELD_GET(AD7280A_TRANS_READ_DEVADDR_MSK, val))) {
0456             ret = -EIO;
0457             goto error_power_down;
0458         }
0459     }
0460     ret = -EFAULT;
0461 
0462 error_power_down:
0463     ad7280_write(st, AD7280A_DEVADDR_MASTER, AD7280A_CTRL_HB_REG, 1,
0464              AD7280A_CTRL_HB_PWRDN_SW |
0465              FIELD_PREP(AD7280A_CTRL_HB_CONV_AVG_MSK, st->oversampling_ratio));
0466 
0467     return ret;
0468 }
0469 
0470 static ssize_t ad7280_show_balance_sw(struct iio_dev *indio_dev,
0471                       uintptr_t private,
0472                       const struct iio_chan_spec *chan, char *buf)
0473 {
0474     struct ad7280_state *st = iio_priv(indio_dev);
0475 
0476     return sysfs_emit(buf, "%d\n",
0477               !!(st->cb_mask[chan->address >> 8] &
0478                  BIT(chan->address & 0xFF)));
0479 }
0480 
0481 static ssize_t ad7280_store_balance_sw(struct iio_dev *indio_dev,
0482                        uintptr_t private,
0483                        const struct iio_chan_spec *chan,
0484                        const char *buf, size_t len)
0485 {
0486     struct ad7280_state *st = iio_priv(indio_dev);
0487     unsigned int devaddr, ch;
0488     bool readin;
0489     int ret;
0490 
0491     ret = kstrtobool(buf, &readin);
0492     if (ret)
0493         return ret;
0494 
0495     devaddr = chan->address >> 8;
0496     ch = chan->address & 0xFF;
0497 
0498     mutex_lock(&st->lock);
0499     if (readin)
0500         st->cb_mask[devaddr] |= BIT(ch);
0501     else
0502         st->cb_mask[devaddr] &= ~BIT(ch);
0503 
0504     ret = ad7280_write(st, devaddr, AD7280A_CELL_BALANCE_REG, 0,
0505                FIELD_PREP(AD7280A_CELL_BALANCE_CHAN_BITMAP_MSK,
0506                       st->cb_mask[devaddr]));
0507     mutex_unlock(&st->lock);
0508 
0509     return ret ? ret : len;
0510 }
0511 
0512 static ssize_t ad7280_show_balance_timer(struct iio_dev *indio_dev,
0513                      uintptr_t private,
0514                      const struct iio_chan_spec *chan,
0515                      char *buf)
0516 {
0517     struct ad7280_state *st = iio_priv(indio_dev);
0518     unsigned int msecs;
0519     int ret;
0520 
0521     mutex_lock(&st->lock);
0522     ret = ad7280_read_reg(st, chan->address >> 8,
0523                   (chan->address & 0xFF) + AD7280A_CB1_TIMER_REG);
0524     mutex_unlock(&st->lock);
0525 
0526     if (ret < 0)
0527         return ret;
0528 
0529     msecs = FIELD_GET(AD7280A_CB_TIMER_VAL_MSK, ret) * 71500;
0530 
0531     return sysfs_emit(buf, "%u.%u\n", msecs / 1000, msecs % 1000);
0532 }
0533 
0534 static ssize_t ad7280_store_balance_timer(struct iio_dev *indio_dev,
0535                       uintptr_t private,
0536                       const struct iio_chan_spec *chan,
0537                       const char *buf, size_t len)
0538 {
0539     struct ad7280_state *st = iio_priv(indio_dev);
0540     int val, val2;
0541     int ret;
0542 
0543     ret = iio_str_to_fixpoint(buf, 1000, &val, &val2);
0544     if (ret)
0545         return ret;
0546 
0547     val = val * 1000 + val2;
0548     val /= 71500;
0549 
0550     if (val > 31)
0551         return -EINVAL;
0552 
0553     mutex_lock(&st->lock);
0554     ret = ad7280_write(st, chan->address >> 8,
0555                (chan->address & 0xFF) + AD7280A_CB1_TIMER_REG, 0,
0556                FIELD_PREP(AD7280A_CB_TIMER_VAL_MSK, val));
0557     mutex_unlock(&st->lock);
0558 
0559     return ret ? ret : len;
0560 }
0561 
0562 static const struct iio_chan_spec_ext_info ad7280_cell_ext_info[] = {
0563     {
0564         .name = "balance_switch_en",
0565         .read = ad7280_show_balance_sw,
0566         .write = ad7280_store_balance_sw,
0567         .shared = IIO_SEPARATE,
0568     }, {
0569         .name = "balance_switch_timer",
0570         .read = ad7280_show_balance_timer,
0571         .write = ad7280_store_balance_timer,
0572         .shared = IIO_SEPARATE,
0573     },
0574     {}
0575 };
0576 
0577 static const struct iio_event_spec ad7280_events[] = {
0578     {
0579         .type = IIO_EV_TYPE_THRESH,
0580         .dir = IIO_EV_DIR_RISING,
0581         .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE),
0582     }, {
0583         .type = IIO_EV_TYPE_THRESH,
0584         .dir = IIO_EV_DIR_FALLING,
0585         .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE),
0586     },
0587 };
0588 
0589 static void ad7280_voltage_channel_init(struct iio_chan_spec *chan, int i,
0590                     bool irq_present)
0591 {
0592     chan->type = IIO_VOLTAGE;
0593     chan->differential = 1;
0594     chan->channel = i;
0595     chan->channel2 = chan->channel + 1;
0596     if (irq_present) {
0597         chan->event_spec = ad7280_events;
0598         chan->num_event_specs = ARRAY_SIZE(ad7280_events);
0599     }
0600     chan->ext_info = ad7280_cell_ext_info;
0601 }
0602 
0603 static void ad7280_temp_channel_init(struct iio_chan_spec *chan, int i,
0604                      bool irq_present)
0605 {
0606     chan->type = IIO_TEMP;
0607     chan->channel = i;
0608     if (irq_present) {
0609         chan->event_spec = ad7280_events;
0610         chan->num_event_specs = ARRAY_SIZE(ad7280_events);
0611     }
0612 }
0613 
0614 static void ad7280_common_fields_init(struct iio_chan_spec *chan, int addr,
0615                       int cnt)
0616 {
0617     chan->indexed = 1;
0618     chan->info_mask_separate = BIT(IIO_CHAN_INFO_RAW);
0619     chan->info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE);
0620     chan->info_mask_shared_by_all = BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO);
0621     chan->address = addr;
0622     chan->scan_index = cnt;
0623     chan->scan_type.sign = 'u';
0624     chan->scan_type.realbits = 12;
0625     chan->scan_type.storagebits = 32;
0626 }
0627 
0628 static void ad7280_total_voltage_channel_init(struct iio_chan_spec *chan,
0629                           int cnt, int dev)
0630 {
0631     chan->type = IIO_VOLTAGE;
0632     chan->differential = 1;
0633     chan->channel = 0;
0634     chan->channel2 = dev * AD7280A_CELLS_PER_DEV;
0635     chan->address = AD7280A_ALL_CELLS;
0636     chan->indexed = 1;
0637     chan->info_mask_separate = BIT(IIO_CHAN_INFO_RAW);
0638     chan->info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE);
0639     chan->scan_index = cnt;
0640     chan->scan_type.sign = 'u';
0641     chan->scan_type.realbits = 32;
0642     chan->scan_type.storagebits = 32;
0643 }
0644 
0645 static void ad7280_init_dev_channels(struct ad7280_state *st, int dev, int *cnt,
0646                      bool irq_present)
0647 {
0648     int addr, ch, i;
0649     struct iio_chan_spec *chan;
0650 
0651     for (ch = AD7280A_CELL_VOLTAGE_1_REG; ch <= AD7280A_AUX_ADC_6_REG; ch++) {
0652         chan = &st->channels[*cnt];
0653 
0654         if (ch < AD7280A_AUX_ADC_1_REG) {
0655             i = AD7280A_CALC_VOLTAGE_CHAN_NUM(dev, ch);
0656             ad7280_voltage_channel_init(chan, i, irq_present);
0657         } else {
0658             i = AD7280A_CALC_TEMP_CHAN_NUM(dev, ch);
0659             ad7280_temp_channel_init(chan, i, irq_present);
0660         }
0661 
0662         addr = ad7280a_devaddr(dev) << 8 | ch;
0663         ad7280_common_fields_init(chan, addr, *cnt);
0664 
0665         (*cnt)++;
0666     }
0667 }
0668 
0669 static int ad7280_channel_init(struct ad7280_state *st, bool irq_present)
0670 {
0671     int dev, cnt = 0;
0672 
0673     st->channels = devm_kcalloc(&st->spi->dev, (st->slave_num + 1) * 12 + 1,
0674                     sizeof(*st->channels), GFP_KERNEL);
0675     if (!st->channels)
0676         return -ENOMEM;
0677 
0678     for (dev = 0; dev <= st->slave_num; dev++)
0679         ad7280_init_dev_channels(st, dev, &cnt, irq_present);
0680 
0681     ad7280_total_voltage_channel_init(&st->channels[cnt], cnt, dev);
0682 
0683     return cnt + 1;
0684 }
0685 
0686 static int ad7280a_read_thresh(struct iio_dev *indio_dev,
0687                    const struct iio_chan_spec *chan,
0688                    enum iio_event_type type,
0689                    enum iio_event_direction dir,
0690                    enum iio_event_info info, int *val, int *val2)
0691 {
0692     struct ad7280_state *st = iio_priv(indio_dev);
0693 
0694     switch (chan->type) {
0695     case IIO_VOLTAGE:
0696         switch (dir) {
0697         case IIO_EV_DIR_RISING:
0698             *val = 1000 + (st->cell_threshhigh * 1568L) / 100;
0699             return IIO_VAL_INT;
0700         case IIO_EV_DIR_FALLING:
0701             *val = 1000 + (st->cell_threshlow * 1568L) / 100;
0702             return IIO_VAL_INT;
0703         default:
0704             return -EINVAL;
0705         }
0706         break;
0707     case IIO_TEMP:
0708         switch (dir) {
0709         case IIO_EV_DIR_RISING:
0710             *val = ((st->aux_threshhigh) * 196L) / 10;
0711             return IIO_VAL_INT;
0712         case IIO_EV_DIR_FALLING:
0713             *val = (st->aux_threshlow * 196L) / 10;
0714             return IIO_VAL_INT;
0715         default:
0716             return -EINVAL;
0717         }
0718         break;
0719     default:
0720         return -EINVAL;
0721     }
0722 }
0723 
0724 static int ad7280a_write_thresh(struct iio_dev *indio_dev,
0725                 const struct iio_chan_spec *chan,
0726                 enum iio_event_type type,
0727                 enum iio_event_direction dir,
0728                 enum iio_event_info info,
0729                 int val, int val2)
0730 {
0731     struct ad7280_state *st = iio_priv(indio_dev);
0732     unsigned int addr;
0733     long value;
0734     int ret;
0735 
0736     if (val2 != 0)
0737         return -EINVAL;
0738 
0739     mutex_lock(&st->lock);
0740     switch (chan->type) {
0741     case IIO_VOLTAGE:
0742         value = ((val - 1000) * 100) / 1568; /* LSB 15.68mV */
0743         value = clamp(value, 0L, 0xFFL);
0744         switch (dir) {
0745         case IIO_EV_DIR_RISING:
0746             addr = AD7280A_CELL_OVERVOLTAGE_REG;
0747             ret = ad7280_write(st, AD7280A_DEVADDR_MASTER, addr,
0748                        1, value);
0749             if (ret)
0750                 break;
0751             st->cell_threshhigh = value;
0752             break;
0753         case IIO_EV_DIR_FALLING:
0754             addr = AD7280A_CELL_UNDERVOLTAGE_REG;
0755             ret = ad7280_write(st, AD7280A_DEVADDR_MASTER, addr,
0756                        1, value);
0757             if (ret)
0758                 break;
0759             st->cell_threshlow = value;
0760             break;
0761         default:
0762             ret = -EINVAL;
0763             goto err_unlock;
0764         }
0765         break;
0766     case IIO_TEMP:
0767         value = (val * 10) / 196; /* LSB 19.6mV */
0768         value = clamp(value, 0L, 0xFFL);
0769         switch (dir) {
0770         case IIO_EV_DIR_RISING:
0771             addr = AD7280A_AUX_ADC_OVERVOLTAGE_REG;
0772             ret = ad7280_write(st, AD7280A_DEVADDR_MASTER, addr,
0773                        1, value);
0774             if (ret)
0775                 break;
0776             st->aux_threshhigh = value;
0777             break;
0778         case IIO_EV_DIR_FALLING:
0779             addr = AD7280A_AUX_ADC_UNDERVOLTAGE_REG;
0780             ret = ad7280_write(st, AD7280A_DEVADDR_MASTER, addr,
0781                        1, value);
0782             if (ret)
0783                 break;
0784             st->aux_threshlow = value;
0785             break;
0786         default:
0787             ret = -EINVAL;
0788             goto err_unlock;
0789         }
0790         break;
0791     default:
0792         ret = -EINVAL;
0793         goto err_unlock;
0794     }
0795 
0796 err_unlock:
0797     mutex_unlock(&st->lock);
0798 
0799     return ret;
0800 }
0801 
0802 static irqreturn_t ad7280_event_handler(int irq, void *private)
0803 {
0804     struct iio_dev *indio_dev = private;
0805     struct ad7280_state *st = iio_priv(indio_dev);
0806     unsigned int *channels;
0807     int i, ret;
0808 
0809     channels = kcalloc(st->scan_cnt, sizeof(*channels), GFP_KERNEL);
0810     if (!channels)
0811         return IRQ_HANDLED;
0812 
0813     ret = ad7280_read_all_channels(st, st->scan_cnt, channels);
0814     if (ret < 0)
0815         goto out;
0816 
0817     for (i = 0; i < st->scan_cnt; i++) {
0818         unsigned int val;
0819 
0820         val = FIELD_GET(AD7280A_TRANS_READ_CONV_DATA_MSK, channels[i]);
0821         if (FIELD_GET(AD7280A_TRANS_READ_CONV_CHANADDR_MSK, channels[i]) <=
0822             AD7280A_CELL_VOLTAGE_6_REG) {
0823             if (val >= st->cell_threshhigh) {
0824                 u64 tmp = IIO_EVENT_CODE(IIO_VOLTAGE, 1, 0,
0825                              IIO_EV_DIR_RISING,
0826                              IIO_EV_TYPE_THRESH,
0827                              0, 0, 0);
0828                 iio_push_event(indio_dev, tmp,
0829                            iio_get_time_ns(indio_dev));
0830             } else if (val <= st->cell_threshlow) {
0831                 u64 tmp = IIO_EVENT_CODE(IIO_VOLTAGE, 1, 0,
0832                              IIO_EV_DIR_FALLING,
0833                              IIO_EV_TYPE_THRESH,
0834                              0, 0, 0);
0835                 iio_push_event(indio_dev, tmp,
0836                            iio_get_time_ns(indio_dev));
0837             }
0838         } else {
0839             if (val >= st->aux_threshhigh) {
0840                 u64 tmp = IIO_UNMOD_EVENT_CODE(IIO_TEMP, 0,
0841                             IIO_EV_TYPE_THRESH,
0842                             IIO_EV_DIR_RISING);
0843                 iio_push_event(indio_dev, tmp,
0844                            iio_get_time_ns(indio_dev));
0845             } else if (val <= st->aux_threshlow) {
0846                 u64 tmp = IIO_UNMOD_EVENT_CODE(IIO_TEMP, 0,
0847                             IIO_EV_TYPE_THRESH,
0848                             IIO_EV_DIR_FALLING);
0849                 iio_push_event(indio_dev, tmp,
0850                            iio_get_time_ns(indio_dev));
0851             }
0852         }
0853     }
0854 
0855 out:
0856     kfree(channels);
0857 
0858     return IRQ_HANDLED;
0859 }
0860 
0861 static void ad7280_update_delay(struct ad7280_state *st)
0862 {
0863     /*
0864      * Total Conversion Time = ((tACQ + tCONV) *
0865      *             (Number of Conversions per Part)) −
0866      *             tACQ + ((N - 1) * tDELAY)
0867      *
0868      * Readback Delay = Total Conversion Time + tWAIT
0869      */
0870 
0871     st->readback_delay_us =
0872         ((ad7280a_t_acq_ns[st->acquisition_time & 0x3] + 720) *
0873             (AD7280A_NUM_CH * ad7280a_n_avg[st->oversampling_ratio & 0x3])) -
0874         ad7280a_t_acq_ns[st->acquisition_time & 0x3] + st->slave_num * 250;
0875 
0876     /* Convert to usecs */
0877     st->readback_delay_us = DIV_ROUND_UP(st->readback_delay_us, 1000);
0878     st->readback_delay_us += 5; /* Add tWAIT */
0879 }
0880 
0881 static int ad7280_read_raw(struct iio_dev *indio_dev,
0882                struct iio_chan_spec const *chan,
0883                int *val,
0884                int *val2,
0885                long m)
0886 {
0887     struct ad7280_state *st = iio_priv(indio_dev);
0888     int ret;
0889 
0890     switch (m) {
0891     case IIO_CHAN_INFO_RAW:
0892         mutex_lock(&st->lock);
0893         if (chan->address == AD7280A_ALL_CELLS)
0894             ret = ad7280_read_all_channels(st, st->scan_cnt, NULL);
0895         else
0896             ret = ad7280_read_channel(st, chan->address >> 8,
0897                           chan->address & 0xFF);
0898         mutex_unlock(&st->lock);
0899 
0900         if (ret < 0)
0901             return ret;
0902 
0903         *val = ret;
0904 
0905         return IIO_VAL_INT;
0906     case IIO_CHAN_INFO_SCALE:
0907         if ((chan->address & 0xFF) <= AD7280A_CELL_VOLTAGE_6_REG)
0908             *val = 4000;
0909         else
0910             *val = 5000;
0911 
0912         *val2 = AD7280A_BITS;
0913         return IIO_VAL_FRACTIONAL_LOG2;
0914     case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
0915         *val = ad7280a_n_avg[st->oversampling_ratio];
0916         return IIO_VAL_INT;
0917     }
0918     return -EINVAL;
0919 }
0920 
0921 static int ad7280_write_raw(struct iio_dev *indio_dev,
0922                 struct iio_chan_spec const *chan,
0923                 int val, int val2, long mask)
0924 {
0925     struct ad7280_state *st = iio_priv(indio_dev);
0926     int i;
0927 
0928     switch (mask) {
0929     case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
0930         if (val2 != 0)
0931             return -EINVAL;
0932         for (i = 0; i < ARRAY_SIZE(ad7280a_n_avg); i++) {
0933             if (val == ad7280a_n_avg[i]) {
0934                 st->oversampling_ratio = i;
0935                 ad7280_update_delay(st);
0936                 return 0;
0937             }
0938         }
0939         return -EINVAL;
0940     default:
0941         return -EINVAL;
0942     }
0943 }
0944 
0945 static const struct iio_info ad7280_info = {
0946     .read_raw = ad7280_read_raw,
0947     .write_raw = ad7280_write_raw,
0948     .read_event_value = &ad7280a_read_thresh,
0949     .write_event_value = &ad7280a_write_thresh,
0950 };
0951 
0952 static const struct iio_info ad7280_info_no_irq = {
0953     .read_raw = ad7280_read_raw,
0954     .write_raw = ad7280_write_raw,
0955 };
0956 
0957 static int ad7280_probe(struct spi_device *spi)
0958 {
0959     struct device *dev = &spi->dev;
0960     struct ad7280_state *st;
0961     int ret;
0962     struct iio_dev *indio_dev;
0963 
0964     indio_dev = devm_iio_device_alloc(dev, sizeof(*st));
0965     if (!indio_dev)
0966         return -ENOMEM;
0967 
0968     st = iio_priv(indio_dev);
0969     spi_set_drvdata(spi, indio_dev);
0970     st->spi = spi;
0971     mutex_init(&st->lock);
0972 
0973     st->thermistor_term_en =
0974         device_property_read_bool(dev, "adi,thermistor-termination");
0975 
0976     if (device_property_present(dev, "adi,acquisition-time-ns")) {
0977         u32 val;
0978 
0979         ret = device_property_read_u32(dev, "adi,acquisition-time-ns", &val);
0980         if (ret)
0981             return ret;
0982 
0983         switch (val) {
0984         case 400:
0985             st->acquisition_time = AD7280A_CTRL_LB_ACQ_TIME_400ns;
0986             break;
0987         case 800:
0988             st->acquisition_time = AD7280A_CTRL_LB_ACQ_TIME_800ns;
0989             break;
0990         case 1200:
0991             st->acquisition_time = AD7280A_CTRL_LB_ACQ_TIME_1200ns;
0992             break;
0993         case 1600:
0994             st->acquisition_time = AD7280A_CTRL_LB_ACQ_TIME_1600ns;
0995             break;
0996         default:
0997             dev_err(dev, "Firmware provided acquisition time is invalid\n");
0998             return -EINVAL;
0999         }
1000     } else {
1001         st->acquisition_time = AD7280A_CTRL_LB_ACQ_TIME_400ns;
1002     }
1003 
1004     /* Alert masks are intended for when particular inputs are not wired up */
1005     if (device_property_present(dev, "adi,voltage-alert-last-chan")) {
1006         u32 val;
1007 
1008         ret = device_property_read_u32(dev, "adi,voltage-alert-last-chan", &val);
1009         if (ret)
1010             return ret;
1011 
1012         switch (val) {
1013         case 3:
1014             st->chain_last_alert_ignore |= AD7280A_ALERT_REMOVE_VIN4_VIN5;
1015             break;
1016         case 4:
1017             st->chain_last_alert_ignore |= AD7280A_ALERT_REMOVE_VIN5;
1018             break;
1019         case 5:
1020             break;
1021         default:
1022             dev_err(dev,
1023                 "Firmware provided last voltage alert channel invalid\n");
1024             break;
1025         }
1026     }
1027     crc8_populate_msb(st->crc_tab, POLYNOM);
1028 
1029     st->spi->max_speed_hz = AD7280A_MAX_SPI_CLK_HZ;
1030     st->spi->mode = SPI_MODE_1;
1031     spi_setup(st->spi);
1032 
1033     st->ctrl_lb = FIELD_PREP(AD7280A_CTRL_LB_ACQ_TIME_MSK, st->acquisition_time) |
1034         FIELD_PREP(AD7280A_CTRL_LB_THERMISTOR_MSK, st->thermistor_term_en);
1035     st->oversampling_ratio = 0; /* No oversampling */
1036 
1037     ret = ad7280_chain_setup(st);
1038     if (ret < 0)
1039         return ret;
1040 
1041     st->slave_num = ret;
1042     st->scan_cnt = (st->slave_num + 1) * AD7280A_NUM_CH;
1043     st->cell_threshhigh = 0xFF;
1044     st->aux_threshhigh = 0xFF;
1045 
1046     ret = devm_add_action_or_reset(dev, ad7280_sw_power_down, st);
1047     if (ret)
1048         return ret;
1049 
1050     ad7280_update_delay(st);
1051 
1052     indio_dev->name = spi_get_device_id(spi)->name;
1053     indio_dev->modes = INDIO_DIRECT_MODE;
1054 
1055     ret = ad7280_channel_init(st, spi->irq > 0);
1056     if (ret < 0)
1057         return ret;
1058 
1059     indio_dev->num_channels = ret;
1060     indio_dev->channels = st->channels;
1061     if (spi->irq > 0) {
1062         ret = ad7280_write(st, AD7280A_DEVADDR_MASTER,
1063                    AD7280A_ALERT_REG, 1,
1064                    AD7280A_ALERT_RELAY_SIG_CHAIN_DOWN);
1065         if (ret)
1066             return ret;
1067 
1068         ret = ad7280_write(st, ad7280a_devaddr(st->slave_num),
1069                    AD7280A_ALERT_REG, 0,
1070                    AD7280A_ALERT_GEN_STATIC_HIGH |
1071                    FIELD_PREP(AD7280A_ALERT_REMOVE_MSK,
1072                           st->chain_last_alert_ignore));
1073         if (ret)
1074             return ret;
1075 
1076         ret = devm_request_threaded_irq(dev, spi->irq,
1077                         NULL,
1078                         ad7280_event_handler,
1079                         IRQF_TRIGGER_FALLING |
1080                         IRQF_ONESHOT,
1081                         indio_dev->name,
1082                         indio_dev);
1083         if (ret)
1084             return ret;
1085 
1086         indio_dev->info = &ad7280_info;
1087     } else {
1088         indio_dev->info = &ad7280_info_no_irq;
1089     }
1090 
1091     return devm_iio_device_register(dev, indio_dev);
1092 }
1093 
1094 static const struct spi_device_id ad7280_id[] = {
1095     {"ad7280a", 0},
1096     {}
1097 };
1098 MODULE_DEVICE_TABLE(spi, ad7280_id);
1099 
1100 static struct spi_driver ad7280_driver = {
1101     .driver = {
1102         .name   = "ad7280",
1103     },
1104     .probe      = ad7280_probe,
1105     .id_table   = ad7280_id,
1106 };
1107 module_spi_driver(ad7280_driver);
1108 
1109 MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>");
1110 MODULE_DESCRIPTION("Analog Devices AD7280A");
1111 MODULE_LICENSE("GPL v2");
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