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0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * AD7190 AD7192 AD7193 AD7195 SPI ADC driver
0004  *
0005  * Copyright 2011-2015 Analog Devices Inc.
0006  */
0007 
0008 #include <linux/interrupt.h>
0009 #include <linux/clk.h>
0010 #include <linux/device.h>
0011 #include <linux/kernel.h>
0012 #include <linux/slab.h>
0013 #include <linux/sysfs.h>
0014 #include <linux/spi/spi.h>
0015 #include <linux/regulator/consumer.h>
0016 #include <linux/err.h>
0017 #include <linux/sched.h>
0018 #include <linux/delay.h>
0019 #include <linux/of_device.h>
0020 
0021 #include <linux/iio/iio.h>
0022 #include <linux/iio/sysfs.h>
0023 #include <linux/iio/buffer.h>
0024 #include <linux/iio/trigger.h>
0025 #include <linux/iio/trigger_consumer.h>
0026 #include <linux/iio/triggered_buffer.h>
0027 #include <linux/iio/adc/ad_sigma_delta.h>
0028 
0029 /* Registers */
0030 #define AD7192_REG_COMM     0 /* Communications Register (WO, 8-bit) */
0031 #define AD7192_REG_STAT     0 /* Status Register         (RO, 8-bit) */
0032 #define AD7192_REG_MODE     1 /* Mode Register       (RW, 24-bit */
0033 #define AD7192_REG_CONF     2 /* Configuration Register  (RW, 24-bit) */
0034 #define AD7192_REG_DATA     3 /* Data Register       (RO, 24/32-bit) */
0035 #define AD7192_REG_ID       4 /* ID Register         (RO, 8-bit) */
0036 #define AD7192_REG_GPOCON   5 /* GPOCON Register         (RO, 8-bit) */
0037 #define AD7192_REG_OFFSET   6 /* Offset Register         (RW, 16-bit */
0038                   /* (AD7792)/24-bit (AD7192)) */
0039 #define AD7192_REG_FULLSALE 7 /* Full-Scale Register */
0040                   /* (RW, 16-bit (AD7792)/24-bit (AD7192)) */
0041 
0042 /* Communications Register Bit Designations (AD7192_REG_COMM) */
0043 #define AD7192_COMM_WEN     BIT(7) /* Write Enable */
0044 #define AD7192_COMM_WRITE   0 /* Write Operation */
0045 #define AD7192_COMM_READ    BIT(6) /* Read Operation */
0046 #define AD7192_COMM_ADDR(x) (((x) & 0x7) << 3) /* Register Address */
0047 #define AD7192_COMM_CREAD   BIT(2) /* Continuous Read of Data Register */
0048 
0049 /* Status Register Bit Designations (AD7192_REG_STAT) */
0050 #define AD7192_STAT_RDY     BIT(7) /* Ready */
0051 #define AD7192_STAT_ERR     BIT(6) /* Error (Overrange, Underrange) */
0052 #define AD7192_STAT_NOREF   BIT(5) /* Error no external reference */
0053 #define AD7192_STAT_PARITY  BIT(4) /* Parity */
0054 #define AD7192_STAT_CH3     BIT(2) /* Channel 3 */
0055 #define AD7192_STAT_CH2     BIT(1) /* Channel 2 */
0056 #define AD7192_STAT_CH1     BIT(0) /* Channel 1 */
0057 
0058 /* Mode Register Bit Designations (AD7192_REG_MODE) */
0059 #define AD7192_MODE_SEL(x)  (((x) & 0x7) << 21) /* Operation Mode Select */
0060 #define AD7192_MODE_SEL_MASK    (0x7 << 21) /* Operation Mode Select Mask */
0061 #define AD7192_MODE_STA(x)  (((x) & 0x1) << 20) /* Status Register transmission */
0062 #define AD7192_MODE_STA_MASK    BIT(20) /* Status Register transmission Mask */
0063 #define AD7192_MODE_CLKSRC(x)   (((x) & 0x3) << 18) /* Clock Source Select */
0064 #define AD7192_MODE_SINC3   BIT(15) /* SINC3 Filter Select */
0065 #define AD7192_MODE_ACX     BIT(14) /* AC excitation enable(AD7195 only)*/
0066 #define AD7192_MODE_ENPAR   BIT(13) /* Parity Enable */
0067 #define AD7192_MODE_CLKDIV  BIT(12) /* Clock divide by 2 (AD7190/2 only)*/
0068 #define AD7192_MODE_SCYCLE  BIT(11) /* Single cycle conversion */
0069 #define AD7192_MODE_REJ60   BIT(10) /* 50/60Hz notch filter */
0070 #define AD7192_MODE_RATE(x) ((x) & 0x3FF) /* Filter Update Rate Select */
0071 
0072 /* Mode Register: AD7192_MODE_SEL options */
0073 #define AD7192_MODE_CONT        0 /* Continuous Conversion Mode */
0074 #define AD7192_MODE_SINGLE      1 /* Single Conversion Mode */
0075 #define AD7192_MODE_IDLE        2 /* Idle Mode */
0076 #define AD7192_MODE_PWRDN       3 /* Power-Down Mode */
0077 #define AD7192_MODE_CAL_INT_ZERO    4 /* Internal Zero-Scale Calibration */
0078 #define AD7192_MODE_CAL_INT_FULL    5 /* Internal Full-Scale Calibration */
0079 #define AD7192_MODE_CAL_SYS_ZERO    6 /* System Zero-Scale Calibration */
0080 #define AD7192_MODE_CAL_SYS_FULL    7 /* System Full-Scale Calibration */
0081 
0082 /* Mode Register: AD7192_MODE_CLKSRC options */
0083 #define AD7192_CLK_EXT_MCLK1_2      0 /* External 4.92 MHz Clock connected*/
0084                       /* from MCLK1 to MCLK2 */
0085 #define AD7192_CLK_EXT_MCLK2        1 /* External Clock applied to MCLK2 */
0086 #define AD7192_CLK_INT          2 /* Internal 4.92 MHz Clock not */
0087                       /* available at the MCLK2 pin */
0088 #define AD7192_CLK_INT_CO       3 /* Internal 4.92 MHz Clock available*/
0089                       /* at the MCLK2 pin */
0090 
0091 /* Configuration Register Bit Designations (AD7192_REG_CONF) */
0092 
0093 #define AD7192_CONF_CHOP    BIT(23) /* CHOP enable */
0094 #define AD7192_CONF_REFSEL  BIT(20) /* REFIN1/REFIN2 Reference Select */
0095 #define AD7192_CONF_CHAN(x) ((x) << 8) /* Channel select */
0096 #define AD7192_CONF_CHAN_MASK   (0x7FF << 8) /* Channel select mask */
0097 #define AD7192_CONF_BURN    BIT(7) /* Burnout current enable */
0098 #define AD7192_CONF_REFDET  BIT(6) /* Reference detect enable */
0099 #define AD7192_CONF_BUF     BIT(4) /* Buffered Mode Enable */
0100 #define AD7192_CONF_UNIPOLAR    BIT(3) /* Unipolar/Bipolar Enable */
0101 #define AD7192_CONF_GAIN(x) ((x) & 0x7) /* Gain Select */
0102 
0103 #define AD7192_CH_AIN1P_AIN2M   BIT(0) /* AIN1(+) - AIN2(-) */
0104 #define AD7192_CH_AIN3P_AIN4M   BIT(1) /* AIN3(+) - AIN4(-) */
0105 #define AD7192_CH_TEMP      BIT(2) /* Temp Sensor */
0106 #define AD7192_CH_AIN2P_AIN2M   BIT(3) /* AIN2(+) - AIN2(-) */
0107 #define AD7192_CH_AIN1      BIT(4) /* AIN1 - AINCOM */
0108 #define AD7192_CH_AIN2      BIT(5) /* AIN2 - AINCOM */
0109 #define AD7192_CH_AIN3      BIT(6) /* AIN3 - AINCOM */
0110 #define AD7192_CH_AIN4      BIT(7) /* AIN4 - AINCOM */
0111 
0112 #define AD7193_CH_AIN1P_AIN2M   0x001  /* AIN1(+) - AIN2(-) */
0113 #define AD7193_CH_AIN3P_AIN4M   0x002  /* AIN3(+) - AIN4(-) */
0114 #define AD7193_CH_AIN5P_AIN6M   0x004  /* AIN5(+) - AIN6(-) */
0115 #define AD7193_CH_AIN7P_AIN8M   0x008  /* AIN7(+) - AIN8(-) */
0116 #define AD7193_CH_TEMP      0x100 /* Temp senseor */
0117 #define AD7193_CH_AIN2P_AIN2M   0x200 /* AIN2(+) - AIN2(-) */
0118 #define AD7193_CH_AIN1      0x401 /* AIN1 - AINCOM */
0119 #define AD7193_CH_AIN2      0x402 /* AIN2 - AINCOM */
0120 #define AD7193_CH_AIN3      0x404 /* AIN3 - AINCOM */
0121 #define AD7193_CH_AIN4      0x408 /* AIN4 - AINCOM */
0122 #define AD7193_CH_AIN5      0x410 /* AIN5 - AINCOM */
0123 #define AD7193_CH_AIN6      0x420 /* AIN6 - AINCOM */
0124 #define AD7193_CH_AIN7      0x440 /* AIN7 - AINCOM */
0125 #define AD7193_CH_AIN8      0x480 /* AIN7 - AINCOM */
0126 #define AD7193_CH_AINCOM    0x600 /* AINCOM - AINCOM */
0127 
0128 /* ID Register Bit Designations (AD7192_REG_ID) */
0129 #define CHIPID_AD7190       0x4
0130 #define CHIPID_AD7192       0x0
0131 #define CHIPID_AD7193       0x2
0132 #define CHIPID_AD7195       0x6
0133 #define AD7192_ID_MASK      0x0F
0134 
0135 /* GPOCON Register Bit Designations (AD7192_REG_GPOCON) */
0136 #define AD7192_GPOCON_BPDSW BIT(6) /* Bridge power-down switch enable */
0137 #define AD7192_GPOCON_GP32EN    BIT(5) /* Digital Output P3 and P2 enable */
0138 #define AD7192_GPOCON_GP10EN    BIT(4) /* Digital Output P1 and P0 enable */
0139 #define AD7192_GPOCON_P3DAT BIT(3) /* P3 state */
0140 #define AD7192_GPOCON_P2DAT BIT(2) /* P2 state */
0141 #define AD7192_GPOCON_P1DAT BIT(1) /* P1 state */
0142 #define AD7192_GPOCON_P0DAT BIT(0) /* P0 state */
0143 
0144 #define AD7192_EXT_FREQ_MHZ_MIN 2457600
0145 #define AD7192_EXT_FREQ_MHZ_MAX 5120000
0146 #define AD7192_INT_FREQ_MHZ 4915200
0147 
0148 #define AD7192_NO_SYNC_FILTER   1
0149 #define AD7192_SYNC3_FILTER 3
0150 #define AD7192_SYNC4_FILTER 4
0151 
0152 /* NOTE:
0153  * The AD7190/2/5 features a dual use data out ready DOUT/RDY output.
0154  * In order to avoid contentions on the SPI bus, it's therefore necessary
0155  * to use spi bus locking.
0156  *
0157  * The DOUT/RDY output must also be wired to an interrupt capable GPIO.
0158  */
0159 
0160 enum {
0161     AD7192_SYSCALIB_ZERO_SCALE,
0162     AD7192_SYSCALIB_FULL_SCALE,
0163 };
0164 
0165 enum {
0166     ID_AD7190,
0167     ID_AD7192,
0168     ID_AD7193,
0169     ID_AD7195,
0170 };
0171 
0172 struct ad7192_chip_info {
0173     unsigned int            chip_id;
0174     const char          *name;
0175 };
0176 
0177 struct ad7192_state {
0178     const struct ad7192_chip_info   *chip_info;
0179     struct regulator        *avdd;
0180     struct regulator        *dvdd;
0181     struct clk          *mclk;
0182     u16             int_vref_mv;
0183     u32             fclk;
0184     u32             f_order;
0185     u32             mode;
0186     u32             conf;
0187     u32             scale_avail[8][2];
0188     u8              gpocon;
0189     u8              clock_sel;
0190     struct mutex            lock;   /* protect sensor state */
0191     u8              syscalib_mode[8];
0192 
0193     struct ad_sigma_delta       sd;
0194 };
0195 
0196 static const char * const ad7192_syscalib_modes[] = {
0197     [AD7192_SYSCALIB_ZERO_SCALE] = "zero_scale",
0198     [AD7192_SYSCALIB_FULL_SCALE] = "full_scale",
0199 };
0200 
0201 static int ad7192_set_syscalib_mode(struct iio_dev *indio_dev,
0202                     const struct iio_chan_spec *chan,
0203                     unsigned int mode)
0204 {
0205     struct ad7192_state *st = iio_priv(indio_dev);
0206 
0207     st->syscalib_mode[chan->channel] = mode;
0208 
0209     return 0;
0210 }
0211 
0212 static int ad7192_get_syscalib_mode(struct iio_dev *indio_dev,
0213                     const struct iio_chan_spec *chan)
0214 {
0215     struct ad7192_state *st = iio_priv(indio_dev);
0216 
0217     return st->syscalib_mode[chan->channel];
0218 }
0219 
0220 static ssize_t ad7192_write_syscalib(struct iio_dev *indio_dev,
0221                      uintptr_t private,
0222                      const struct iio_chan_spec *chan,
0223                      const char *buf, size_t len)
0224 {
0225     struct ad7192_state *st = iio_priv(indio_dev);
0226     bool sys_calib;
0227     int ret, temp;
0228 
0229     ret = kstrtobool(buf, &sys_calib);
0230     if (ret)
0231         return ret;
0232 
0233     temp = st->syscalib_mode[chan->channel];
0234     if (sys_calib) {
0235         if (temp == AD7192_SYSCALIB_ZERO_SCALE)
0236             ret = ad_sd_calibrate(&st->sd, AD7192_MODE_CAL_SYS_ZERO,
0237                           chan->address);
0238         else
0239             ret = ad_sd_calibrate(&st->sd, AD7192_MODE_CAL_SYS_FULL,
0240                           chan->address);
0241     }
0242 
0243     return ret ? ret : len;
0244 }
0245 
0246 static const struct iio_enum ad7192_syscalib_mode_enum = {
0247     .items = ad7192_syscalib_modes,
0248     .num_items = ARRAY_SIZE(ad7192_syscalib_modes),
0249     .set = ad7192_set_syscalib_mode,
0250     .get = ad7192_get_syscalib_mode
0251 };
0252 
0253 static const struct iio_chan_spec_ext_info ad7192_calibsys_ext_info[] = {
0254     {
0255         .name = "sys_calibration",
0256         .write = ad7192_write_syscalib,
0257         .shared = IIO_SEPARATE,
0258     },
0259     IIO_ENUM("sys_calibration_mode", IIO_SEPARATE,
0260          &ad7192_syscalib_mode_enum),
0261     IIO_ENUM_AVAILABLE("sys_calibration_mode", IIO_SHARED_BY_TYPE,
0262                &ad7192_syscalib_mode_enum),
0263     {}
0264 };
0265 
0266 static struct ad7192_state *ad_sigma_delta_to_ad7192(struct ad_sigma_delta *sd)
0267 {
0268     return container_of(sd, struct ad7192_state, sd);
0269 }
0270 
0271 static int ad7192_set_channel(struct ad_sigma_delta *sd, unsigned int channel)
0272 {
0273     struct ad7192_state *st = ad_sigma_delta_to_ad7192(sd);
0274 
0275     st->conf &= ~AD7192_CONF_CHAN_MASK;
0276     st->conf |= AD7192_CONF_CHAN(channel);
0277 
0278     return ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, st->conf);
0279 }
0280 
0281 static int ad7192_set_mode(struct ad_sigma_delta *sd,
0282                enum ad_sigma_delta_mode mode)
0283 {
0284     struct ad7192_state *st = ad_sigma_delta_to_ad7192(sd);
0285 
0286     st->mode &= ~AD7192_MODE_SEL_MASK;
0287     st->mode |= AD7192_MODE_SEL(mode);
0288 
0289     return ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode);
0290 }
0291 
0292 static int ad7192_append_status(struct ad_sigma_delta *sd, bool append)
0293 {
0294     struct ad7192_state *st = ad_sigma_delta_to_ad7192(sd);
0295     unsigned int mode = st->mode;
0296     int ret;
0297 
0298     mode &= ~AD7192_MODE_STA_MASK;
0299     mode |= AD7192_MODE_STA(append);
0300 
0301     ret = ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, mode);
0302     if (ret < 0)
0303         return ret;
0304 
0305     st->mode = mode;
0306 
0307     return 0;
0308 }
0309 
0310 static int ad7192_disable_all(struct ad_sigma_delta *sd)
0311 {
0312     struct ad7192_state *st = ad_sigma_delta_to_ad7192(sd);
0313     u32 conf = st->conf;
0314     int ret;
0315 
0316     conf &= ~AD7192_CONF_CHAN_MASK;
0317 
0318     ret = ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, conf);
0319     if (ret < 0)
0320         return ret;
0321 
0322     st->conf = conf;
0323 
0324     return 0;
0325 }
0326 
0327 static const struct ad_sigma_delta_info ad7192_sigma_delta_info = {
0328     .set_channel = ad7192_set_channel,
0329     .append_status = ad7192_append_status,
0330     .disable_all = ad7192_disable_all,
0331     .set_mode = ad7192_set_mode,
0332     .has_registers = true,
0333     .addr_shift = 3,
0334     .read_mask = BIT(6),
0335     .status_ch_mask = GENMASK(3, 0),
0336     .num_slots = 4,
0337     .irq_flags = IRQF_TRIGGER_FALLING,
0338 };
0339 
0340 static const struct ad_sd_calib_data ad7192_calib_arr[8] = {
0341     {AD7192_MODE_CAL_INT_ZERO, AD7192_CH_AIN1},
0342     {AD7192_MODE_CAL_INT_FULL, AD7192_CH_AIN1},
0343     {AD7192_MODE_CAL_INT_ZERO, AD7192_CH_AIN2},
0344     {AD7192_MODE_CAL_INT_FULL, AD7192_CH_AIN2},
0345     {AD7192_MODE_CAL_INT_ZERO, AD7192_CH_AIN3},
0346     {AD7192_MODE_CAL_INT_FULL, AD7192_CH_AIN3},
0347     {AD7192_MODE_CAL_INT_ZERO, AD7192_CH_AIN4},
0348     {AD7192_MODE_CAL_INT_FULL, AD7192_CH_AIN4}
0349 };
0350 
0351 static int ad7192_calibrate_all(struct ad7192_state *st)
0352 {
0353     return ad_sd_calibrate_all(&st->sd, ad7192_calib_arr,
0354                    ARRAY_SIZE(ad7192_calib_arr));
0355 }
0356 
0357 static inline bool ad7192_valid_external_frequency(u32 freq)
0358 {
0359     return (freq >= AD7192_EXT_FREQ_MHZ_MIN &&
0360         freq <= AD7192_EXT_FREQ_MHZ_MAX);
0361 }
0362 
0363 static int ad7192_of_clock_select(struct ad7192_state *st)
0364 {
0365     struct device_node *np = st->sd.spi->dev.of_node;
0366     unsigned int clock_sel;
0367 
0368     clock_sel = AD7192_CLK_INT;
0369 
0370     /* use internal clock */
0371     if (st->mclk) {
0372         if (of_property_read_bool(np, "adi,int-clock-output-enable"))
0373             clock_sel = AD7192_CLK_INT_CO;
0374     } else {
0375         if (of_property_read_bool(np, "adi,clock-xtal"))
0376             clock_sel = AD7192_CLK_EXT_MCLK1_2;
0377         else
0378             clock_sel = AD7192_CLK_EXT_MCLK2;
0379     }
0380 
0381     return clock_sel;
0382 }
0383 
0384 static int ad7192_setup(struct ad7192_state *st, struct device_node *np)
0385 {
0386     struct iio_dev *indio_dev = spi_get_drvdata(st->sd.spi);
0387     bool rej60_en, refin2_en;
0388     bool buf_en, bipolar, burnout_curr_en;
0389     unsigned long long scale_uv;
0390     int i, ret, id;
0391 
0392     /* reset the serial interface */
0393     ret = ad_sd_reset(&st->sd, 48);
0394     if (ret < 0)
0395         return ret;
0396     usleep_range(500, 1000); /* Wait for at least 500us */
0397 
0398     /* write/read test for device presence */
0399     ret = ad_sd_read_reg(&st->sd, AD7192_REG_ID, 1, &id);
0400     if (ret)
0401         return ret;
0402 
0403     id &= AD7192_ID_MASK;
0404 
0405     if (id != st->chip_info->chip_id)
0406         dev_warn(&st->sd.spi->dev, "device ID query failed (0x%X)\n",
0407              id);
0408 
0409     st->mode = AD7192_MODE_SEL(AD7192_MODE_IDLE) |
0410         AD7192_MODE_CLKSRC(st->clock_sel) |
0411         AD7192_MODE_RATE(480);
0412 
0413     st->conf = AD7192_CONF_GAIN(0);
0414 
0415     rej60_en = of_property_read_bool(np, "adi,rejection-60-Hz-enable");
0416     if (rej60_en)
0417         st->mode |= AD7192_MODE_REJ60;
0418 
0419     refin2_en = of_property_read_bool(np, "adi,refin2-pins-enable");
0420     if (refin2_en && st->chip_info->chip_id != CHIPID_AD7195)
0421         st->conf |= AD7192_CONF_REFSEL;
0422 
0423     st->conf &= ~AD7192_CONF_CHOP;
0424     st->f_order = AD7192_NO_SYNC_FILTER;
0425 
0426     buf_en = of_property_read_bool(np, "adi,buffer-enable");
0427     if (buf_en)
0428         st->conf |= AD7192_CONF_BUF;
0429 
0430     bipolar = of_property_read_bool(np, "bipolar");
0431     if (!bipolar)
0432         st->conf |= AD7192_CONF_UNIPOLAR;
0433 
0434     burnout_curr_en = of_property_read_bool(np,
0435                         "adi,burnout-currents-enable");
0436     if (burnout_curr_en && buf_en) {
0437         st->conf |= AD7192_CONF_BURN;
0438     } else if (burnout_curr_en) {
0439         dev_warn(&st->sd.spi->dev,
0440              "Can't enable burnout currents: see CHOP or buffer\n");
0441     }
0442 
0443     ret = ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode);
0444     if (ret)
0445         return ret;
0446 
0447     ret = ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, st->conf);
0448     if (ret)
0449         return ret;
0450 
0451     ret = ad7192_calibrate_all(st);
0452     if (ret)
0453         return ret;
0454 
0455     /* Populate available ADC input ranges */
0456     for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++) {
0457         scale_uv = ((u64)st->int_vref_mv * 100000000)
0458             >> (indio_dev->channels[0].scan_type.realbits -
0459             ((st->conf & AD7192_CONF_UNIPOLAR) ? 0 : 1));
0460         scale_uv >>= i;
0461 
0462         st->scale_avail[i][1] = do_div(scale_uv, 100000000) * 10;
0463         st->scale_avail[i][0] = scale_uv;
0464     }
0465 
0466     return 0;
0467 }
0468 
0469 static ssize_t ad7192_show_ac_excitation(struct device *dev,
0470                      struct device_attribute *attr,
0471                      char *buf)
0472 {
0473     struct iio_dev *indio_dev = dev_to_iio_dev(dev);
0474     struct ad7192_state *st = iio_priv(indio_dev);
0475 
0476     return sysfs_emit(buf, "%d\n", !!(st->mode & AD7192_MODE_ACX));
0477 }
0478 
0479 static ssize_t ad7192_show_bridge_switch(struct device *dev,
0480                      struct device_attribute *attr,
0481                      char *buf)
0482 {
0483     struct iio_dev *indio_dev = dev_to_iio_dev(dev);
0484     struct ad7192_state *st = iio_priv(indio_dev);
0485 
0486     return sysfs_emit(buf, "%d\n", !!(st->gpocon & AD7192_GPOCON_BPDSW));
0487 }
0488 
0489 static ssize_t ad7192_set(struct device *dev,
0490               struct device_attribute *attr,
0491               const char *buf,
0492               size_t len)
0493 {
0494     struct iio_dev *indio_dev = dev_to_iio_dev(dev);
0495     struct ad7192_state *st = iio_priv(indio_dev);
0496     struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
0497     int ret;
0498     bool val;
0499 
0500     ret = kstrtobool(buf, &val);
0501     if (ret < 0)
0502         return ret;
0503 
0504     ret = iio_device_claim_direct_mode(indio_dev);
0505     if (ret)
0506         return ret;
0507 
0508     switch ((u32)this_attr->address) {
0509     case AD7192_REG_GPOCON:
0510         if (val)
0511             st->gpocon |= AD7192_GPOCON_BPDSW;
0512         else
0513             st->gpocon &= ~AD7192_GPOCON_BPDSW;
0514 
0515         ad_sd_write_reg(&st->sd, AD7192_REG_GPOCON, 1, st->gpocon);
0516         break;
0517     case AD7192_REG_MODE:
0518         if (val)
0519             st->mode |= AD7192_MODE_ACX;
0520         else
0521             st->mode &= ~AD7192_MODE_ACX;
0522 
0523         ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode);
0524         break;
0525     default:
0526         ret = -EINVAL;
0527     }
0528 
0529     iio_device_release_direct_mode(indio_dev);
0530 
0531     return ret ? ret : len;
0532 }
0533 
0534 static void ad7192_get_available_filter_freq(struct ad7192_state *st,
0535                             int *freq)
0536 {
0537     unsigned int fadc;
0538 
0539     /* Formulas for filter at page 25 of the datasheet */
0540     fadc = DIV_ROUND_CLOSEST(st->fclk,
0541                  AD7192_SYNC4_FILTER * AD7192_MODE_RATE(st->mode));
0542     freq[0] = DIV_ROUND_CLOSEST(fadc * 240, 1024);
0543 
0544     fadc = DIV_ROUND_CLOSEST(st->fclk,
0545                  AD7192_SYNC3_FILTER * AD7192_MODE_RATE(st->mode));
0546     freq[1] = DIV_ROUND_CLOSEST(fadc * 240, 1024);
0547 
0548     fadc = DIV_ROUND_CLOSEST(st->fclk, AD7192_MODE_RATE(st->mode));
0549     freq[2] = DIV_ROUND_CLOSEST(fadc * 230, 1024);
0550     freq[3] = DIV_ROUND_CLOSEST(fadc * 272, 1024);
0551 }
0552 
0553 static ssize_t ad7192_show_filter_avail(struct device *dev,
0554                     struct device_attribute *attr,
0555                     char *buf)
0556 {
0557     struct iio_dev *indio_dev = dev_to_iio_dev(dev);
0558     struct ad7192_state *st = iio_priv(indio_dev);
0559     unsigned int freq_avail[4], i;
0560     size_t len = 0;
0561 
0562     ad7192_get_available_filter_freq(st, freq_avail);
0563 
0564     for (i = 0; i < ARRAY_SIZE(freq_avail); i++)
0565         len += scnprintf(buf + len, PAGE_SIZE - len,
0566                  "%d.%d ", freq_avail[i] / 1000,
0567                  freq_avail[i] % 1000);
0568 
0569     buf[len - 1] = '\n';
0570 
0571     return len;
0572 }
0573 
0574 static IIO_DEVICE_ATTR(filter_low_pass_3db_frequency_available,
0575                0444, ad7192_show_filter_avail, NULL, 0);
0576 
0577 static IIO_DEVICE_ATTR(bridge_switch_en, 0644,
0578                ad7192_show_bridge_switch, ad7192_set,
0579                AD7192_REG_GPOCON);
0580 
0581 static IIO_DEVICE_ATTR(ac_excitation_en, 0644,
0582                ad7192_show_ac_excitation, ad7192_set,
0583                AD7192_REG_MODE);
0584 
0585 static struct attribute *ad7192_attributes[] = {
0586     &iio_dev_attr_filter_low_pass_3db_frequency_available.dev_attr.attr,
0587     &iio_dev_attr_bridge_switch_en.dev_attr.attr,
0588     &iio_dev_attr_ac_excitation_en.dev_attr.attr,
0589     NULL
0590 };
0591 
0592 static const struct attribute_group ad7192_attribute_group = {
0593     .attrs = ad7192_attributes,
0594 };
0595 
0596 static struct attribute *ad7195_attributes[] = {
0597     &iio_dev_attr_filter_low_pass_3db_frequency_available.dev_attr.attr,
0598     &iio_dev_attr_bridge_switch_en.dev_attr.attr,
0599     NULL
0600 };
0601 
0602 static const struct attribute_group ad7195_attribute_group = {
0603     .attrs = ad7195_attributes,
0604 };
0605 
0606 static unsigned int ad7192_get_temp_scale(bool unipolar)
0607 {
0608     return unipolar ? 2815 * 2 : 2815;
0609 }
0610 
0611 static int ad7192_set_3db_filter_freq(struct ad7192_state *st,
0612                       int val, int val2)
0613 {
0614     int freq_avail[4], i, ret, freq;
0615     unsigned int diff_new, diff_old;
0616     int idx = 0;
0617 
0618     diff_old = U32_MAX;
0619     freq = val * 1000 + val2;
0620 
0621     ad7192_get_available_filter_freq(st, freq_avail);
0622 
0623     for (i = 0; i < ARRAY_SIZE(freq_avail); i++) {
0624         diff_new = abs(freq - freq_avail[i]);
0625         if (diff_new < diff_old) {
0626             diff_old = diff_new;
0627             idx = i;
0628         }
0629     }
0630 
0631     switch (idx) {
0632     case 0:
0633         st->f_order = AD7192_SYNC4_FILTER;
0634         st->mode &= ~AD7192_MODE_SINC3;
0635 
0636         st->conf |= AD7192_CONF_CHOP;
0637         break;
0638     case 1:
0639         st->f_order = AD7192_SYNC3_FILTER;
0640         st->mode |= AD7192_MODE_SINC3;
0641 
0642         st->conf |= AD7192_CONF_CHOP;
0643         break;
0644     case 2:
0645         st->f_order = AD7192_NO_SYNC_FILTER;
0646         st->mode &= ~AD7192_MODE_SINC3;
0647 
0648         st->conf &= ~AD7192_CONF_CHOP;
0649         break;
0650     case 3:
0651         st->f_order = AD7192_NO_SYNC_FILTER;
0652         st->mode |= AD7192_MODE_SINC3;
0653 
0654         st->conf &= ~AD7192_CONF_CHOP;
0655         break;
0656     }
0657 
0658     ret = ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode);
0659     if (ret < 0)
0660         return ret;
0661 
0662     return ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, st->conf);
0663 }
0664 
0665 static int ad7192_get_3db_filter_freq(struct ad7192_state *st)
0666 {
0667     unsigned int fadc;
0668 
0669     fadc = DIV_ROUND_CLOSEST(st->fclk,
0670                  st->f_order * AD7192_MODE_RATE(st->mode));
0671 
0672     if (st->conf & AD7192_CONF_CHOP)
0673         return DIV_ROUND_CLOSEST(fadc * 240, 1024);
0674     if (st->mode & AD7192_MODE_SINC3)
0675         return DIV_ROUND_CLOSEST(fadc * 272, 1024);
0676     else
0677         return DIV_ROUND_CLOSEST(fadc * 230, 1024);
0678 }
0679 
0680 static int ad7192_read_raw(struct iio_dev *indio_dev,
0681                struct iio_chan_spec const *chan,
0682                int *val,
0683                int *val2,
0684                long m)
0685 {
0686     struct ad7192_state *st = iio_priv(indio_dev);
0687     bool unipolar = !!(st->conf & AD7192_CONF_UNIPOLAR);
0688 
0689     switch (m) {
0690     case IIO_CHAN_INFO_RAW:
0691         return ad_sigma_delta_single_conversion(indio_dev, chan, val);
0692     case IIO_CHAN_INFO_SCALE:
0693         switch (chan->type) {
0694         case IIO_VOLTAGE:
0695             mutex_lock(&st->lock);
0696             *val = st->scale_avail[AD7192_CONF_GAIN(st->conf)][0];
0697             *val2 = st->scale_avail[AD7192_CONF_GAIN(st->conf)][1];
0698             mutex_unlock(&st->lock);
0699             return IIO_VAL_INT_PLUS_NANO;
0700         case IIO_TEMP:
0701             *val = 0;
0702             *val2 = 1000000000 / ad7192_get_temp_scale(unipolar);
0703             return IIO_VAL_INT_PLUS_NANO;
0704         default:
0705             return -EINVAL;
0706         }
0707     case IIO_CHAN_INFO_OFFSET:
0708         if (!unipolar)
0709             *val = -(1 << (chan->scan_type.realbits - 1));
0710         else
0711             *val = 0;
0712         /* Kelvin to Celsius */
0713         if (chan->type == IIO_TEMP)
0714             *val -= 273 * ad7192_get_temp_scale(unipolar);
0715         return IIO_VAL_INT;
0716     case IIO_CHAN_INFO_SAMP_FREQ:
0717         *val = st->fclk /
0718             (st->f_order * 1024 * AD7192_MODE_RATE(st->mode));
0719         return IIO_VAL_INT;
0720     case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
0721         *val = ad7192_get_3db_filter_freq(st);
0722         *val2 = 1000;
0723         return IIO_VAL_FRACTIONAL;
0724     }
0725 
0726     return -EINVAL;
0727 }
0728 
0729 static int ad7192_write_raw(struct iio_dev *indio_dev,
0730                 struct iio_chan_spec const *chan,
0731                 int val,
0732                 int val2,
0733                 long mask)
0734 {
0735     struct ad7192_state *st = iio_priv(indio_dev);
0736     int ret, i, div;
0737     unsigned int tmp;
0738 
0739     ret = iio_device_claim_direct_mode(indio_dev);
0740     if (ret)
0741         return ret;
0742 
0743     switch (mask) {
0744     case IIO_CHAN_INFO_SCALE:
0745         ret = -EINVAL;
0746         mutex_lock(&st->lock);
0747         for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++)
0748             if (val2 == st->scale_avail[i][1]) {
0749                 ret = 0;
0750                 tmp = st->conf;
0751                 st->conf &= ~AD7192_CONF_GAIN(-1);
0752                 st->conf |= AD7192_CONF_GAIN(i);
0753                 if (tmp == st->conf)
0754                     break;
0755                 ad_sd_write_reg(&st->sd, AD7192_REG_CONF,
0756                         3, st->conf);
0757                 ad7192_calibrate_all(st);
0758                 break;
0759             }
0760         mutex_unlock(&st->lock);
0761         break;
0762     case IIO_CHAN_INFO_SAMP_FREQ:
0763         if (!val) {
0764             ret = -EINVAL;
0765             break;
0766         }
0767 
0768         div = st->fclk / (val * st->f_order * 1024);
0769         if (div < 1 || div > 1023) {
0770             ret = -EINVAL;
0771             break;
0772         }
0773 
0774         st->mode &= ~AD7192_MODE_RATE(-1);
0775         st->mode |= AD7192_MODE_RATE(div);
0776         ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode);
0777         break;
0778     case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
0779         ret = ad7192_set_3db_filter_freq(st, val, val2 / 1000);
0780         break;
0781     default:
0782         ret = -EINVAL;
0783     }
0784 
0785     iio_device_release_direct_mode(indio_dev);
0786 
0787     return ret;
0788 }
0789 
0790 static int ad7192_write_raw_get_fmt(struct iio_dev *indio_dev,
0791                     struct iio_chan_spec const *chan,
0792                     long mask)
0793 {
0794     switch (mask) {
0795     case IIO_CHAN_INFO_SCALE:
0796         return IIO_VAL_INT_PLUS_NANO;
0797     case IIO_CHAN_INFO_SAMP_FREQ:
0798         return IIO_VAL_INT;
0799     case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
0800         return IIO_VAL_INT_PLUS_MICRO;
0801     default:
0802         return -EINVAL;
0803     }
0804 }
0805 
0806 static int ad7192_read_avail(struct iio_dev *indio_dev,
0807                  struct iio_chan_spec const *chan,
0808                  const int **vals, int *type, int *length,
0809                  long mask)
0810 {
0811     struct ad7192_state *st = iio_priv(indio_dev);
0812 
0813     switch (mask) {
0814     case IIO_CHAN_INFO_SCALE:
0815         *vals = (int *)st->scale_avail;
0816         *type = IIO_VAL_INT_PLUS_NANO;
0817         /* Values are stored in a 2D matrix  */
0818         *length = ARRAY_SIZE(st->scale_avail) * 2;
0819 
0820         return IIO_AVAIL_LIST;
0821     }
0822 
0823     return -EINVAL;
0824 }
0825 
0826 static int ad7192_update_scan_mode(struct iio_dev *indio_dev, const unsigned long *scan_mask)
0827 {
0828     struct ad7192_state *st = iio_priv(indio_dev);
0829     u32 conf = st->conf;
0830     int ret;
0831     int i;
0832 
0833     conf &= ~AD7192_CONF_CHAN_MASK;
0834     for_each_set_bit(i, scan_mask, 8)
0835         conf |= AD7192_CONF_CHAN(i);
0836 
0837     ret = ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, conf);
0838     if (ret < 0)
0839         return ret;
0840 
0841     st->conf = conf;
0842 
0843     return 0;
0844 }
0845 
0846 static const struct iio_info ad7192_info = {
0847     .read_raw = ad7192_read_raw,
0848     .write_raw = ad7192_write_raw,
0849     .write_raw_get_fmt = ad7192_write_raw_get_fmt,
0850     .read_avail = ad7192_read_avail,
0851     .attrs = &ad7192_attribute_group,
0852     .validate_trigger = ad_sd_validate_trigger,
0853     .update_scan_mode = ad7192_update_scan_mode,
0854 };
0855 
0856 static const struct iio_info ad7195_info = {
0857     .read_raw = ad7192_read_raw,
0858     .write_raw = ad7192_write_raw,
0859     .write_raw_get_fmt = ad7192_write_raw_get_fmt,
0860     .read_avail = ad7192_read_avail,
0861     .attrs = &ad7195_attribute_group,
0862     .validate_trigger = ad_sd_validate_trigger,
0863     .update_scan_mode = ad7192_update_scan_mode,
0864 };
0865 
0866 #define __AD719x_CHANNEL(_si, _channel1, _channel2, _address, _extend_name, \
0867     _type, _mask_type_av, _ext_info) \
0868     { \
0869         .type = (_type), \
0870         .differential = ((_channel2) == -1 ? 0 : 1), \
0871         .indexed = 1, \
0872         .channel = (_channel1), \
0873         .channel2 = (_channel2), \
0874         .address = (_address), \
0875         .extend_name = (_extend_name), \
0876         .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
0877             BIT(IIO_CHAN_INFO_OFFSET), \
0878         .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
0879         .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \
0880             BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY), \
0881         .info_mask_shared_by_type_available = (_mask_type_av), \
0882         .ext_info = (_ext_info), \
0883         .scan_index = (_si), \
0884         .scan_type = { \
0885             .sign = 'u', \
0886             .realbits = 24, \
0887             .storagebits = 32, \
0888             .endianness = IIO_BE, \
0889         }, \
0890     }
0891 
0892 #define AD719x_DIFF_CHANNEL(_si, _channel1, _channel2, _address) \
0893     __AD719x_CHANNEL(_si, _channel1, _channel2, _address, NULL, \
0894         IIO_VOLTAGE, BIT(IIO_CHAN_INFO_SCALE), \
0895         ad7192_calibsys_ext_info)
0896 
0897 #define AD719x_CHANNEL(_si, _channel1, _address) \
0898     __AD719x_CHANNEL(_si, _channel1, -1, _address, NULL, IIO_VOLTAGE, \
0899         BIT(IIO_CHAN_INFO_SCALE), ad7192_calibsys_ext_info)
0900 
0901 #define AD719x_SHORTED_CHANNEL(_si, _channel1, _address) \
0902     __AD719x_CHANNEL(_si, _channel1, -1, _address, "shorted", IIO_VOLTAGE, \
0903         BIT(IIO_CHAN_INFO_SCALE), ad7192_calibsys_ext_info)
0904 
0905 #define AD719x_TEMP_CHANNEL(_si, _address) \
0906     __AD719x_CHANNEL(_si, 0, -1, _address, NULL, IIO_TEMP, 0, NULL)
0907 
0908 static const struct iio_chan_spec ad7192_channels[] = {
0909     AD719x_DIFF_CHANNEL(0, 1, 2, AD7192_CH_AIN1P_AIN2M),
0910     AD719x_DIFF_CHANNEL(1, 3, 4, AD7192_CH_AIN3P_AIN4M),
0911     AD719x_TEMP_CHANNEL(2, AD7192_CH_TEMP),
0912     AD719x_SHORTED_CHANNEL(3, 2, AD7192_CH_AIN2P_AIN2M),
0913     AD719x_CHANNEL(4, 1, AD7192_CH_AIN1),
0914     AD719x_CHANNEL(5, 2, AD7192_CH_AIN2),
0915     AD719x_CHANNEL(6, 3, AD7192_CH_AIN3),
0916     AD719x_CHANNEL(7, 4, AD7192_CH_AIN4),
0917     IIO_CHAN_SOFT_TIMESTAMP(8),
0918 };
0919 
0920 static const struct iio_chan_spec ad7193_channels[] = {
0921     AD719x_DIFF_CHANNEL(0, 1, 2, AD7193_CH_AIN1P_AIN2M),
0922     AD719x_DIFF_CHANNEL(1, 3, 4, AD7193_CH_AIN3P_AIN4M),
0923     AD719x_DIFF_CHANNEL(2, 5, 6, AD7193_CH_AIN5P_AIN6M),
0924     AD719x_DIFF_CHANNEL(3, 7, 8, AD7193_CH_AIN7P_AIN8M),
0925     AD719x_TEMP_CHANNEL(4, AD7193_CH_TEMP),
0926     AD719x_SHORTED_CHANNEL(5, 2, AD7193_CH_AIN2P_AIN2M),
0927     AD719x_CHANNEL(6, 1, AD7193_CH_AIN1),
0928     AD719x_CHANNEL(7, 2, AD7193_CH_AIN2),
0929     AD719x_CHANNEL(8, 3, AD7193_CH_AIN3),
0930     AD719x_CHANNEL(9, 4, AD7193_CH_AIN4),
0931     AD719x_CHANNEL(10, 5, AD7193_CH_AIN5),
0932     AD719x_CHANNEL(11, 6, AD7193_CH_AIN6),
0933     AD719x_CHANNEL(12, 7, AD7193_CH_AIN7),
0934     AD719x_CHANNEL(13, 8, AD7193_CH_AIN8),
0935     IIO_CHAN_SOFT_TIMESTAMP(14),
0936 };
0937 
0938 static const struct ad7192_chip_info ad7192_chip_info_tbl[] = {
0939     [ID_AD7190] = {
0940         .chip_id = CHIPID_AD7190,
0941         .name = "ad7190",
0942     },
0943     [ID_AD7192] = {
0944         .chip_id = CHIPID_AD7192,
0945         .name = "ad7192",
0946     },
0947     [ID_AD7193] = {
0948         .chip_id = CHIPID_AD7193,
0949         .name = "ad7193",
0950     },
0951     [ID_AD7195] = {
0952         .chip_id = CHIPID_AD7195,
0953         .name = "ad7195",
0954     },
0955 };
0956 
0957 static int ad7192_channels_config(struct iio_dev *indio_dev)
0958 {
0959     struct ad7192_state *st = iio_priv(indio_dev);
0960 
0961     switch (st->chip_info->chip_id) {
0962     case CHIPID_AD7193:
0963         indio_dev->channels = ad7193_channels;
0964         indio_dev->num_channels = ARRAY_SIZE(ad7193_channels);
0965         break;
0966     default:
0967         indio_dev->channels = ad7192_channels;
0968         indio_dev->num_channels = ARRAY_SIZE(ad7192_channels);
0969         break;
0970     }
0971 
0972     return 0;
0973 }
0974 
0975 static void ad7192_reg_disable(void *reg)
0976 {
0977     regulator_disable(reg);
0978 }
0979 
0980 static void ad7192_clk_disable(void *clk)
0981 {
0982     clk_disable_unprepare(clk);
0983 }
0984 
0985 static int ad7192_probe(struct spi_device *spi)
0986 {
0987     struct ad7192_state *st;
0988     struct iio_dev *indio_dev;
0989     int ret;
0990 
0991     if (!spi->irq) {
0992         dev_err(&spi->dev, "no IRQ?\n");
0993         return -ENODEV;
0994     }
0995 
0996     indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
0997     if (!indio_dev)
0998         return -ENOMEM;
0999 
1000     st = iio_priv(indio_dev);
1001 
1002     mutex_init(&st->lock);
1003 
1004     st->avdd = devm_regulator_get(&spi->dev, "avdd");
1005     if (IS_ERR(st->avdd))
1006         return PTR_ERR(st->avdd);
1007 
1008     ret = regulator_enable(st->avdd);
1009     if (ret) {
1010         dev_err(&spi->dev, "Failed to enable specified AVdd supply\n");
1011         return ret;
1012     }
1013 
1014     ret = devm_add_action_or_reset(&spi->dev, ad7192_reg_disable, st->avdd);
1015     if (ret)
1016         return ret;
1017 
1018     st->dvdd = devm_regulator_get(&spi->dev, "dvdd");
1019     if (IS_ERR(st->dvdd))
1020         return PTR_ERR(st->dvdd);
1021 
1022     ret = regulator_enable(st->dvdd);
1023     if (ret) {
1024         dev_err(&spi->dev, "Failed to enable specified DVdd supply\n");
1025         return ret;
1026     }
1027 
1028     ret = devm_add_action_or_reset(&spi->dev, ad7192_reg_disable, st->dvdd);
1029     if (ret)
1030         return ret;
1031 
1032     ret = regulator_get_voltage(st->avdd);
1033     if (ret < 0) {
1034         dev_err(&spi->dev, "Device tree error, reference voltage undefined\n");
1035         return ret;
1036     }
1037     st->int_vref_mv = ret / 1000;
1038 
1039     st->chip_info = of_device_get_match_data(&spi->dev);
1040     indio_dev->name = st->chip_info->name;
1041     indio_dev->modes = INDIO_DIRECT_MODE;
1042 
1043     ret = ad7192_channels_config(indio_dev);
1044     if (ret < 0)
1045         return ret;
1046 
1047     if (st->chip_info->chip_id == CHIPID_AD7195)
1048         indio_dev->info = &ad7195_info;
1049     else
1050         indio_dev->info = &ad7192_info;
1051 
1052     ad_sd_init(&st->sd, indio_dev, spi, &ad7192_sigma_delta_info);
1053 
1054     ret = devm_ad_sd_setup_buffer_and_trigger(&spi->dev, indio_dev);
1055     if (ret)
1056         return ret;
1057 
1058     st->fclk = AD7192_INT_FREQ_MHZ;
1059 
1060     st->mclk = devm_clk_get_optional(&spi->dev, "mclk");
1061     if (IS_ERR(st->mclk))
1062         return PTR_ERR(st->mclk);
1063 
1064     st->clock_sel = ad7192_of_clock_select(st);
1065 
1066     if (st->clock_sel == AD7192_CLK_EXT_MCLK1_2 ||
1067         st->clock_sel == AD7192_CLK_EXT_MCLK2) {
1068         ret = clk_prepare_enable(st->mclk);
1069         if (ret < 0)
1070             return ret;
1071 
1072         ret = devm_add_action_or_reset(&spi->dev, ad7192_clk_disable,
1073                            st->mclk);
1074         if (ret)
1075             return ret;
1076 
1077         st->fclk = clk_get_rate(st->mclk);
1078         if (!ad7192_valid_external_frequency(st->fclk)) {
1079             dev_err(&spi->dev,
1080                 "External clock frequency out of bounds\n");
1081             return -EINVAL;
1082         }
1083     }
1084 
1085     ret = ad7192_setup(st, spi->dev.of_node);
1086     if (ret)
1087         return ret;
1088 
1089     return devm_iio_device_register(&spi->dev, indio_dev);
1090 }
1091 
1092 static const struct of_device_id ad7192_of_match[] = {
1093     { .compatible = "adi,ad7190", .data = &ad7192_chip_info_tbl[ID_AD7190] },
1094     { .compatible = "adi,ad7192", .data = &ad7192_chip_info_tbl[ID_AD7192] },
1095     { .compatible = "adi,ad7193", .data = &ad7192_chip_info_tbl[ID_AD7193] },
1096     { .compatible = "adi,ad7195", .data = &ad7192_chip_info_tbl[ID_AD7195] },
1097     {}
1098 };
1099 MODULE_DEVICE_TABLE(of, ad7192_of_match);
1100 
1101 static struct spi_driver ad7192_driver = {
1102     .driver = {
1103         .name   = "ad7192",
1104         .of_match_table = ad7192_of_match,
1105     },
1106     .probe      = ad7192_probe,
1107 };
1108 module_spi_driver(ad7192_driver);
1109 
1110 MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>");
1111 MODULE_DESCRIPTION("Analog Devices AD7190, AD7192, AD7193, AD7195 ADC");
1112 MODULE_LICENSE("GPL v2");
1113 MODULE_IMPORT_NS(IIO_AD_SIGMA_DELTA);
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