Back to home page

OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0+
0002 /*
0003  * AD7124 SPI ADC driver
0004  *
0005  * Copyright 2018 Analog Devices Inc.
0006  */
0007 #include <linux/bitfield.h>
0008 #include <linux/bitops.h>
0009 #include <linux/clk.h>
0010 #include <linux/delay.h>
0011 #include <linux/device.h>
0012 #include <linux/err.h>
0013 #include <linux/interrupt.h>
0014 #include <linux/kernel.h>
0015 #include <linux/kfifo.h>
0016 #include <linux/module.h>
0017 #include <linux/of_device.h>
0018 #include <linux/regulator/consumer.h>
0019 #include <linux/spi/spi.h>
0020 
0021 #include <linux/iio/iio.h>
0022 #include <linux/iio/adc/ad_sigma_delta.h>
0023 #include <linux/iio/sysfs.h>
0024 
0025 /* AD7124 registers */
0026 #define AD7124_COMMS            0x00
0027 #define AD7124_STATUS           0x00
0028 #define AD7124_ADC_CONTROL      0x01
0029 #define AD7124_DATA         0x02
0030 #define AD7124_IO_CONTROL_1     0x03
0031 #define AD7124_IO_CONTROL_2     0x04
0032 #define AD7124_ID           0x05
0033 #define AD7124_ERROR            0x06
0034 #define AD7124_ERROR_EN     0x07
0035 #define AD7124_MCLK_COUNT       0x08
0036 #define AD7124_CHANNEL(x)       (0x09 + (x))
0037 #define AD7124_CONFIG(x)        (0x19 + (x))
0038 #define AD7124_FILTER(x)        (0x21 + (x))
0039 #define AD7124_OFFSET(x)        (0x29 + (x))
0040 #define AD7124_GAIN(x)          (0x31 + (x))
0041 
0042 /* AD7124_STATUS */
0043 #define AD7124_STATUS_POR_FLAG_MSK  BIT(4)
0044 
0045 /* AD7124_ADC_CONTROL */
0046 #define AD7124_ADC_STATUS_EN_MSK    BIT(10)
0047 #define AD7124_ADC_STATUS_EN(x)     FIELD_PREP(AD7124_ADC_STATUS_EN_MSK, x)
0048 #define AD7124_ADC_CTRL_REF_EN_MSK  BIT(8)
0049 #define AD7124_ADC_CTRL_REF_EN(x)   FIELD_PREP(AD7124_ADC_CTRL_REF_EN_MSK, x)
0050 #define AD7124_ADC_CTRL_PWR_MSK GENMASK(7, 6)
0051 #define AD7124_ADC_CTRL_PWR(x)      FIELD_PREP(AD7124_ADC_CTRL_PWR_MSK, x)
0052 #define AD7124_ADC_CTRL_MODE_MSK    GENMASK(5, 2)
0053 #define AD7124_ADC_CTRL_MODE(x) FIELD_PREP(AD7124_ADC_CTRL_MODE_MSK, x)
0054 
0055 /* AD7124 ID */
0056 #define AD7124_DEVICE_ID_MSK        GENMASK(7, 4)
0057 #define AD7124_DEVICE_ID_GET(x)     FIELD_GET(AD7124_DEVICE_ID_MSK, x)
0058 #define AD7124_SILICON_REV_MSK      GENMASK(3, 0)
0059 #define AD7124_SILICON_REV_GET(x)   FIELD_GET(AD7124_SILICON_REV_MSK, x)
0060 
0061 #define CHIPID_AD7124_4         0x0
0062 #define CHIPID_AD7124_8         0x1
0063 
0064 /* AD7124_CHANNEL_X */
0065 #define AD7124_CHANNEL_EN_MSK       BIT(15)
0066 #define AD7124_CHANNEL_EN(x)        FIELD_PREP(AD7124_CHANNEL_EN_MSK, x)
0067 #define AD7124_CHANNEL_SETUP_MSK    GENMASK(14, 12)
0068 #define AD7124_CHANNEL_SETUP(x) FIELD_PREP(AD7124_CHANNEL_SETUP_MSK, x)
0069 #define AD7124_CHANNEL_AINP_MSK GENMASK(9, 5)
0070 #define AD7124_CHANNEL_AINP(x)      FIELD_PREP(AD7124_CHANNEL_AINP_MSK, x)
0071 #define AD7124_CHANNEL_AINM_MSK GENMASK(4, 0)
0072 #define AD7124_CHANNEL_AINM(x)      FIELD_PREP(AD7124_CHANNEL_AINM_MSK, x)
0073 
0074 /* AD7124_CONFIG_X */
0075 #define AD7124_CONFIG_BIPOLAR_MSK   BIT(11)
0076 #define AD7124_CONFIG_BIPOLAR(x)    FIELD_PREP(AD7124_CONFIG_BIPOLAR_MSK, x)
0077 #define AD7124_CONFIG_REF_SEL_MSK   GENMASK(4, 3)
0078 #define AD7124_CONFIG_REF_SEL(x)    FIELD_PREP(AD7124_CONFIG_REF_SEL_MSK, x)
0079 #define AD7124_CONFIG_PGA_MSK       GENMASK(2, 0)
0080 #define AD7124_CONFIG_PGA(x)        FIELD_PREP(AD7124_CONFIG_PGA_MSK, x)
0081 #define AD7124_CONFIG_IN_BUFF_MSK   GENMASK(6, 5)
0082 #define AD7124_CONFIG_IN_BUFF(x)    FIELD_PREP(AD7124_CONFIG_IN_BUFF_MSK, x)
0083 
0084 /* AD7124_FILTER_X */
0085 #define AD7124_FILTER_FS_MSK        GENMASK(10, 0)
0086 #define AD7124_FILTER_FS(x)     FIELD_PREP(AD7124_FILTER_FS_MSK, x)
0087 #define AD7124_FILTER_TYPE_MSK      GENMASK(23, 21)
0088 #define AD7124_FILTER_TYPE_SEL(x)   FIELD_PREP(AD7124_FILTER_TYPE_MSK, x)
0089 
0090 #define AD7124_SINC3_FILTER 2
0091 #define AD7124_SINC4_FILTER 0
0092 
0093 #define AD7124_CONF_ADDR_OFFSET 20
0094 #define AD7124_MAX_CONFIGS  8
0095 #define AD7124_MAX_CHANNELS 16
0096 
0097 enum ad7124_ids {
0098     ID_AD7124_4,
0099     ID_AD7124_8,
0100 };
0101 
0102 enum ad7124_ref_sel {
0103     AD7124_REFIN1,
0104     AD7124_REFIN2,
0105     AD7124_INT_REF,
0106     AD7124_AVDD_REF,
0107 };
0108 
0109 enum ad7124_power_mode {
0110     AD7124_LOW_POWER,
0111     AD7124_MID_POWER,
0112     AD7124_FULL_POWER,
0113 };
0114 
0115 static const unsigned int ad7124_gain[8] = {
0116     1, 2, 4, 8, 16, 32, 64, 128
0117 };
0118 
0119 static const unsigned int ad7124_reg_size[] = {
0120     1, 2, 3, 3, 2, 1, 3, 3, 1, 2, 2, 2, 2,
0121     2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
0122     2, 2, 2, 2, 2, 2, 2, 3, 3, 3, 3, 3, 3,
0123     3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
0124     3, 3, 3, 3, 3
0125 };
0126 
0127 static const int ad7124_master_clk_freq_hz[3] = {
0128     [AD7124_LOW_POWER] = 76800,
0129     [AD7124_MID_POWER] = 153600,
0130     [AD7124_FULL_POWER] = 614400,
0131 };
0132 
0133 static const char * const ad7124_ref_names[] = {
0134     [AD7124_REFIN1] = "refin1",
0135     [AD7124_REFIN2] = "refin2",
0136     [AD7124_INT_REF] = "int",
0137     [AD7124_AVDD_REF] = "avdd",
0138 };
0139 
0140 struct ad7124_chip_info {
0141     const char *name;
0142     unsigned int chip_id;
0143     unsigned int num_inputs;
0144 };
0145 
0146 struct ad7124_channel_config {
0147     bool live;
0148     unsigned int cfg_slot;
0149     enum ad7124_ref_sel refsel;
0150     bool bipolar;
0151     bool buf_positive;
0152     bool buf_negative;
0153     unsigned int vref_mv;
0154     unsigned int pga_bits;
0155     unsigned int odr;
0156     unsigned int odr_sel_bits;
0157     unsigned int filter_type;
0158 };
0159 
0160 struct ad7124_channel {
0161     unsigned int nr;
0162     struct ad7124_channel_config cfg;
0163     unsigned int ain;
0164     unsigned int slot;
0165 };
0166 
0167 struct ad7124_state {
0168     const struct ad7124_chip_info *chip_info;
0169     struct ad_sigma_delta sd;
0170     struct ad7124_channel *channels;
0171     struct regulator *vref[4];
0172     struct clk *mclk;
0173     unsigned int adc_control;
0174     unsigned int num_channels;
0175     struct mutex cfgs_lock; /* lock for configs access */
0176     unsigned long cfg_slots_status; /* bitmap with slot status (1 means it is used) */
0177     DECLARE_KFIFO(live_cfgs_fifo, struct ad7124_channel_config *, AD7124_MAX_CONFIGS);
0178 };
0179 
0180 static const struct iio_chan_spec ad7124_channel_template = {
0181     .type = IIO_VOLTAGE,
0182     .indexed = 1,
0183     .differential = 1,
0184     .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
0185         BIT(IIO_CHAN_INFO_SCALE) |
0186         BIT(IIO_CHAN_INFO_OFFSET) |
0187         BIT(IIO_CHAN_INFO_SAMP_FREQ) |
0188         BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY),
0189     .scan_type = {
0190         .sign = 'u',
0191         .realbits = 24,
0192         .storagebits = 32,
0193         .endianness = IIO_BE,
0194     },
0195 };
0196 
0197 static struct ad7124_chip_info ad7124_chip_info_tbl[] = {
0198     [ID_AD7124_4] = {
0199         .name = "ad7124-4",
0200         .chip_id = CHIPID_AD7124_4,
0201         .num_inputs = 8,
0202     },
0203     [ID_AD7124_8] = {
0204         .name = "ad7124-8",
0205         .chip_id = CHIPID_AD7124_8,
0206         .num_inputs = 16,
0207     },
0208 };
0209 
0210 static int ad7124_find_closest_match(const int *array,
0211                      unsigned int size, int val)
0212 {
0213     int i, idx;
0214     unsigned int diff_new, diff_old;
0215 
0216     diff_old = U32_MAX;
0217     idx = 0;
0218 
0219     for (i = 0; i < size; i++) {
0220         diff_new = abs(val - array[i]);
0221         if (diff_new < diff_old) {
0222             diff_old = diff_new;
0223             idx = i;
0224         }
0225     }
0226 
0227     return idx;
0228 }
0229 
0230 static int ad7124_spi_write_mask(struct ad7124_state *st,
0231                  unsigned int addr,
0232                  unsigned long mask,
0233                  unsigned int val,
0234                  unsigned int bytes)
0235 {
0236     unsigned int readval;
0237     int ret;
0238 
0239     ret = ad_sd_read_reg(&st->sd, addr, bytes, &readval);
0240     if (ret < 0)
0241         return ret;
0242 
0243     readval &= ~mask;
0244     readval |= val;
0245 
0246     return ad_sd_write_reg(&st->sd, addr, bytes, readval);
0247 }
0248 
0249 static int ad7124_set_mode(struct ad_sigma_delta *sd,
0250                enum ad_sigma_delta_mode mode)
0251 {
0252     struct ad7124_state *st = container_of(sd, struct ad7124_state, sd);
0253 
0254     st->adc_control &= ~AD7124_ADC_CTRL_MODE_MSK;
0255     st->adc_control |= AD7124_ADC_CTRL_MODE(mode);
0256 
0257     return ad_sd_write_reg(&st->sd, AD7124_ADC_CONTROL, 2, st->adc_control);
0258 }
0259 
0260 static void ad7124_set_channel_odr(struct ad7124_state *st, unsigned int channel, unsigned int odr)
0261 {
0262     unsigned int fclk, odr_sel_bits;
0263 
0264     fclk = clk_get_rate(st->mclk);
0265     /*
0266      * FS[10:0] = fCLK / (fADC x 32) where:
0267      * fADC is the output data rate
0268      * fCLK is the master clock frequency
0269      * FS[10:0] are the bits in the filter register
0270      * FS[10:0] can have a value from 1 to 2047
0271      */
0272     odr_sel_bits = DIV_ROUND_CLOSEST(fclk, odr * 32);
0273     if (odr_sel_bits < 1)
0274         odr_sel_bits = 1;
0275     else if (odr_sel_bits > 2047)
0276         odr_sel_bits = 2047;
0277 
0278     if (odr_sel_bits != st->channels[channel].cfg.odr_sel_bits)
0279         st->channels[channel].cfg.live = false;
0280 
0281     /* fADC = fCLK / (FS[10:0] x 32) */
0282     st->channels[channel].cfg.odr = DIV_ROUND_CLOSEST(fclk, odr_sel_bits * 32);
0283     st->channels[channel].cfg.odr_sel_bits = odr_sel_bits;
0284 }
0285 
0286 static int ad7124_get_3db_filter_freq(struct ad7124_state *st,
0287                       unsigned int channel)
0288 {
0289     unsigned int fadc;
0290 
0291     fadc = st->channels[channel].cfg.odr;
0292 
0293     switch (st->channels[channel].cfg.filter_type) {
0294     case AD7124_SINC3_FILTER:
0295         return DIV_ROUND_CLOSEST(fadc * 230, 1000);
0296     case AD7124_SINC4_FILTER:
0297         return DIV_ROUND_CLOSEST(fadc * 262, 1000);
0298     default:
0299         return -EINVAL;
0300     }
0301 }
0302 
0303 static void ad7124_set_3db_filter_freq(struct ad7124_state *st, unsigned int channel,
0304                        unsigned int freq)
0305 {
0306     unsigned int sinc4_3db_odr;
0307     unsigned int sinc3_3db_odr;
0308     unsigned int new_filter;
0309     unsigned int new_odr;
0310 
0311     sinc4_3db_odr = DIV_ROUND_CLOSEST(freq * 1000, 230);
0312     sinc3_3db_odr = DIV_ROUND_CLOSEST(freq * 1000, 262);
0313 
0314     if (sinc4_3db_odr > sinc3_3db_odr) {
0315         new_filter = AD7124_SINC3_FILTER;
0316         new_odr = sinc4_3db_odr;
0317     } else {
0318         new_filter = AD7124_SINC4_FILTER;
0319         new_odr = sinc3_3db_odr;
0320     }
0321 
0322     if (new_odr != st->channels[channel].cfg.odr)
0323         st->channels[channel].cfg.live = false;
0324 
0325     st->channels[channel].cfg.filter_type = new_filter;
0326     st->channels[channel].cfg.odr = new_odr;
0327 }
0328 
0329 static struct ad7124_channel_config *ad7124_find_similar_live_cfg(struct ad7124_state *st,
0330                                   struct ad7124_channel_config *cfg)
0331 {
0332     struct ad7124_channel_config *cfg_aux;
0333     ptrdiff_t cmp_size;
0334     int i;
0335 
0336     cmp_size = (u8 *)&cfg->live - (u8 *)cfg;
0337     for (i = 0; i < st->num_channels; i++) {
0338         cfg_aux = &st->channels[i].cfg;
0339 
0340         if (cfg_aux->live && !memcmp(cfg, cfg_aux, cmp_size))
0341             return cfg_aux;
0342     }
0343 
0344     return NULL;
0345 }
0346 
0347 static int ad7124_find_free_config_slot(struct ad7124_state *st)
0348 {
0349     unsigned int free_cfg_slot;
0350 
0351     free_cfg_slot = find_first_zero_bit(&st->cfg_slots_status, AD7124_MAX_CONFIGS);
0352     if (free_cfg_slot == AD7124_MAX_CONFIGS)
0353         return -1;
0354 
0355     return free_cfg_slot;
0356 }
0357 
0358 static int ad7124_init_config_vref(struct ad7124_state *st, struct ad7124_channel_config *cfg)
0359 {
0360     unsigned int refsel = cfg->refsel;
0361 
0362     switch (refsel) {
0363     case AD7124_REFIN1:
0364     case AD7124_REFIN2:
0365     case AD7124_AVDD_REF:
0366         if (IS_ERR(st->vref[refsel])) {
0367             dev_err(&st->sd.spi->dev,
0368                 "Error, trying to use external voltage reference without a %s regulator.\n",
0369                 ad7124_ref_names[refsel]);
0370             return PTR_ERR(st->vref[refsel]);
0371         }
0372         cfg->vref_mv = regulator_get_voltage(st->vref[refsel]);
0373         /* Conversion from uV to mV */
0374         cfg->vref_mv /= 1000;
0375         return 0;
0376     case AD7124_INT_REF:
0377         cfg->vref_mv = 2500;
0378         st->adc_control &= ~AD7124_ADC_CTRL_REF_EN_MSK;
0379         st->adc_control |= AD7124_ADC_CTRL_REF_EN(1);
0380         return ad_sd_write_reg(&st->sd, AD7124_ADC_CONTROL,
0381                       2, st->adc_control);
0382     default:
0383         dev_err(&st->sd.spi->dev, "Invalid reference %d\n", refsel);
0384         return -EINVAL;
0385     }
0386 }
0387 
0388 static int ad7124_write_config(struct ad7124_state *st, struct ad7124_channel_config *cfg,
0389                    unsigned int cfg_slot)
0390 {
0391     unsigned int tmp;
0392     unsigned int val;
0393     int ret;
0394 
0395     cfg->cfg_slot = cfg_slot;
0396 
0397     tmp = (cfg->buf_positive << 1) + cfg->buf_negative;
0398     val = AD7124_CONFIG_BIPOLAR(cfg->bipolar) | AD7124_CONFIG_REF_SEL(cfg->refsel) |
0399           AD7124_CONFIG_IN_BUFF(tmp);
0400     ret = ad_sd_write_reg(&st->sd, AD7124_CONFIG(cfg->cfg_slot), 2, val);
0401     if (ret < 0)
0402         return ret;
0403 
0404     tmp = AD7124_FILTER_TYPE_SEL(cfg->filter_type);
0405     ret = ad7124_spi_write_mask(st, AD7124_FILTER(cfg->cfg_slot), AD7124_FILTER_TYPE_MSK,
0406                     tmp, 3);
0407     if (ret < 0)
0408         return ret;
0409 
0410     ret = ad7124_spi_write_mask(st, AD7124_FILTER(cfg->cfg_slot), AD7124_FILTER_FS_MSK,
0411                     AD7124_FILTER_FS(cfg->odr_sel_bits), 3);
0412     if (ret < 0)
0413         return ret;
0414 
0415     return ad7124_spi_write_mask(st, AD7124_CONFIG(cfg->cfg_slot), AD7124_CONFIG_PGA_MSK,
0416                      AD7124_CONFIG_PGA(cfg->pga_bits), 2);
0417 }
0418 
0419 static struct ad7124_channel_config *ad7124_pop_config(struct ad7124_state *st)
0420 {
0421     struct ad7124_channel_config *lru_cfg;
0422     struct ad7124_channel_config *cfg;
0423     int ret;
0424     int i;
0425 
0426     /*
0427      * Pop least recently used config from the fifo
0428      * in order to make room for the new one
0429      */
0430     ret = kfifo_get(&st->live_cfgs_fifo, &lru_cfg);
0431     if (ret <= 0)
0432         return NULL;
0433 
0434     lru_cfg->live = false;
0435 
0436     /* mark slot as free */
0437     assign_bit(lru_cfg->cfg_slot, &st->cfg_slots_status, 0);
0438 
0439     /* invalidate all other configs that pointed to this one */
0440     for (i = 0; i < st->num_channels; i++) {
0441         cfg = &st->channels[i].cfg;
0442 
0443         if (cfg->cfg_slot == lru_cfg->cfg_slot)
0444             cfg->live = false;
0445     }
0446 
0447     return lru_cfg;
0448 }
0449 
0450 static int ad7124_push_config(struct ad7124_state *st, struct ad7124_channel_config *cfg)
0451 {
0452     struct ad7124_channel_config *lru_cfg;
0453     int free_cfg_slot;
0454 
0455     free_cfg_slot = ad7124_find_free_config_slot(st);
0456     if (free_cfg_slot >= 0) {
0457         /* push the new config in configs queue */
0458         kfifo_put(&st->live_cfgs_fifo, cfg);
0459     } else {
0460         /* pop one config to make room for the new one */
0461         lru_cfg = ad7124_pop_config(st);
0462         if (!lru_cfg)
0463             return -EINVAL;
0464 
0465         /* push the new config in configs queue */
0466         free_cfg_slot = lru_cfg->cfg_slot;
0467         kfifo_put(&st->live_cfgs_fifo, cfg);
0468     }
0469 
0470     /* mark slot as used */
0471     assign_bit(free_cfg_slot, &st->cfg_slots_status, 1);
0472 
0473     return ad7124_write_config(st, cfg, free_cfg_slot);
0474 }
0475 
0476 static int ad7124_enable_channel(struct ad7124_state *st, struct ad7124_channel *ch)
0477 {
0478     ch->cfg.live = true;
0479     return ad_sd_write_reg(&st->sd, AD7124_CHANNEL(ch->nr), 2, ch->ain |
0480                   AD7124_CHANNEL_SETUP(ch->cfg.cfg_slot) | AD7124_CHANNEL_EN(1));
0481 }
0482 
0483 static int ad7124_prepare_read(struct ad7124_state *st, int address)
0484 {
0485     struct ad7124_channel_config *cfg = &st->channels[address].cfg;
0486     struct ad7124_channel_config *live_cfg;
0487 
0488     /*
0489      * Before doing any reads assign the channel a configuration.
0490      * Check if channel's config is on the device
0491      */
0492     if (!cfg->live) {
0493         /* check if config matches another one */
0494         live_cfg = ad7124_find_similar_live_cfg(st, cfg);
0495         if (!live_cfg)
0496             ad7124_push_config(st, cfg);
0497         else
0498             cfg->cfg_slot = live_cfg->cfg_slot;
0499     }
0500 
0501     /* point channel to the config slot and enable */
0502     return ad7124_enable_channel(st, &st->channels[address]);
0503 }
0504 
0505 static int __ad7124_set_channel(struct ad_sigma_delta *sd, unsigned int channel)
0506 {
0507     struct ad7124_state *st = container_of(sd, struct ad7124_state, sd);
0508 
0509     return ad7124_prepare_read(st, channel);
0510 }
0511 
0512 static int ad7124_set_channel(struct ad_sigma_delta *sd, unsigned int channel)
0513 {
0514     struct ad7124_state *st = container_of(sd, struct ad7124_state, sd);
0515     int ret;
0516 
0517     mutex_lock(&st->cfgs_lock);
0518     ret = __ad7124_set_channel(sd, channel);
0519     mutex_unlock(&st->cfgs_lock);
0520 
0521     return ret;
0522 }
0523 
0524 static int ad7124_append_status(struct ad_sigma_delta *sd, bool append)
0525 {
0526     struct ad7124_state *st = container_of(sd, struct ad7124_state, sd);
0527     unsigned int adc_control = st->adc_control;
0528     int ret;
0529 
0530     adc_control &= ~AD7124_ADC_STATUS_EN_MSK;
0531     adc_control |= AD7124_ADC_STATUS_EN(append);
0532 
0533     ret = ad_sd_write_reg(&st->sd, AD7124_ADC_CONTROL, 2, adc_control);
0534     if (ret < 0)
0535         return ret;
0536 
0537     st->adc_control = adc_control;
0538 
0539     return 0;
0540 }
0541 
0542 static int ad7124_disable_all(struct ad_sigma_delta *sd)
0543 {
0544     struct ad7124_state *st = container_of(sd, struct ad7124_state, sd);
0545     int ret;
0546     int i;
0547 
0548     for (i = 0; i < st->num_channels; i++) {
0549         ret = ad7124_spi_write_mask(st, AD7124_CHANNEL(i), AD7124_CHANNEL_EN_MSK, 0, 2);
0550         if (ret < 0)
0551             return ret;
0552     }
0553 
0554     return 0;
0555 }
0556 
0557 static const struct ad_sigma_delta_info ad7124_sigma_delta_info = {
0558     .set_channel = ad7124_set_channel,
0559     .append_status = ad7124_append_status,
0560     .disable_all = ad7124_disable_all,
0561     .set_mode = ad7124_set_mode,
0562     .has_registers = true,
0563     .addr_shift = 0,
0564     .read_mask = BIT(6),
0565     .status_ch_mask = GENMASK(3, 0),
0566     .data_reg = AD7124_DATA,
0567     .num_slots = 8,
0568     .irq_flags = IRQF_TRIGGER_FALLING,
0569 };
0570 
0571 static int ad7124_read_raw(struct iio_dev *indio_dev,
0572                struct iio_chan_spec const *chan,
0573                int *val, int *val2, long info)
0574 {
0575     struct ad7124_state *st = iio_priv(indio_dev);
0576     int idx, ret;
0577 
0578     switch (info) {
0579     case IIO_CHAN_INFO_RAW:
0580         ret = ad_sigma_delta_single_conversion(indio_dev, chan, val);
0581         if (ret < 0)
0582             return ret;
0583 
0584         /* After the conversion is performed, disable the channel */
0585         ret = ad_sd_write_reg(&st->sd, AD7124_CHANNEL(chan->address), 2,
0586                       st->channels[chan->address].ain | AD7124_CHANNEL_EN(0));
0587         if (ret < 0)
0588             return ret;
0589 
0590         return IIO_VAL_INT;
0591     case IIO_CHAN_INFO_SCALE:
0592         mutex_lock(&st->cfgs_lock);
0593 
0594         idx = st->channels[chan->address].cfg.pga_bits;
0595         *val = st->channels[chan->address].cfg.vref_mv;
0596         if (st->channels[chan->address].cfg.bipolar)
0597             *val2 = chan->scan_type.realbits - 1 + idx;
0598         else
0599             *val2 = chan->scan_type.realbits + idx;
0600 
0601         mutex_unlock(&st->cfgs_lock);
0602         return IIO_VAL_FRACTIONAL_LOG2;
0603     case IIO_CHAN_INFO_OFFSET:
0604         mutex_lock(&st->cfgs_lock);
0605         if (st->channels[chan->address].cfg.bipolar)
0606             *val = -(1 << (chan->scan_type.realbits - 1));
0607         else
0608             *val = 0;
0609 
0610         mutex_unlock(&st->cfgs_lock);
0611         return IIO_VAL_INT;
0612     case IIO_CHAN_INFO_SAMP_FREQ:
0613         mutex_lock(&st->cfgs_lock);
0614         *val = st->channels[chan->address].cfg.odr;
0615         mutex_unlock(&st->cfgs_lock);
0616 
0617         return IIO_VAL_INT;
0618     case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
0619         mutex_lock(&st->cfgs_lock);
0620         *val = ad7124_get_3db_filter_freq(st, chan->scan_index);
0621         mutex_unlock(&st->cfgs_lock);
0622 
0623         return IIO_VAL_INT;
0624     default:
0625         return -EINVAL;
0626     }
0627 }
0628 
0629 static int ad7124_write_raw(struct iio_dev *indio_dev,
0630                 struct iio_chan_spec const *chan,
0631                 int val, int val2, long info)
0632 {
0633     struct ad7124_state *st = iio_priv(indio_dev);
0634     unsigned int res, gain, full_scale, vref;
0635     int ret = 0;
0636 
0637     mutex_lock(&st->cfgs_lock);
0638 
0639     switch (info) {
0640     case IIO_CHAN_INFO_SAMP_FREQ:
0641         if (val2 != 0) {
0642             ret = -EINVAL;
0643             break;
0644         }
0645 
0646         ad7124_set_channel_odr(st, chan->address, val);
0647         break;
0648     case IIO_CHAN_INFO_SCALE:
0649         if (val != 0) {
0650             ret = -EINVAL;
0651             break;
0652         }
0653 
0654         if (st->channels[chan->address].cfg.bipolar)
0655             full_scale = 1 << (chan->scan_type.realbits - 1);
0656         else
0657             full_scale = 1 << chan->scan_type.realbits;
0658 
0659         vref = st->channels[chan->address].cfg.vref_mv * 1000000LL;
0660         res = DIV_ROUND_CLOSEST(vref, full_scale);
0661         gain = DIV_ROUND_CLOSEST(res, val2);
0662         res = ad7124_find_closest_match(ad7124_gain, ARRAY_SIZE(ad7124_gain), gain);
0663 
0664         if (st->channels[chan->address].cfg.pga_bits != res)
0665             st->channels[chan->address].cfg.live = false;
0666 
0667         st->channels[chan->address].cfg.pga_bits = res;
0668         break;
0669     case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
0670         if (val2 != 0) {
0671             ret = -EINVAL;
0672             break;
0673         }
0674 
0675         ad7124_set_3db_filter_freq(st, chan->address, val);
0676         break;
0677     default:
0678         ret =  -EINVAL;
0679     }
0680 
0681     mutex_unlock(&st->cfgs_lock);
0682     return ret;
0683 }
0684 
0685 static int ad7124_reg_access(struct iio_dev *indio_dev,
0686                  unsigned int reg,
0687                  unsigned int writeval,
0688                  unsigned int *readval)
0689 {
0690     struct ad7124_state *st = iio_priv(indio_dev);
0691     int ret;
0692 
0693     if (reg >= ARRAY_SIZE(ad7124_reg_size))
0694         return -EINVAL;
0695 
0696     if (readval)
0697         ret = ad_sd_read_reg(&st->sd, reg, ad7124_reg_size[reg],
0698                      readval);
0699     else
0700         ret = ad_sd_write_reg(&st->sd, reg, ad7124_reg_size[reg],
0701                       writeval);
0702 
0703     return ret;
0704 }
0705 
0706 static IIO_CONST_ATTR(in_voltage_scale_available,
0707     "0.000001164 0.000002328 0.000004656 0.000009313 0.000018626 0.000037252 0.000074505 0.000149011 0.000298023");
0708 
0709 static struct attribute *ad7124_attributes[] = {
0710     &iio_const_attr_in_voltage_scale_available.dev_attr.attr,
0711     NULL,
0712 };
0713 
0714 static const struct attribute_group ad7124_attrs_group = {
0715     .attrs = ad7124_attributes,
0716 };
0717 
0718 static int ad7124_update_scan_mode(struct iio_dev *indio_dev,
0719                    const unsigned long *scan_mask)
0720 {
0721     struct ad7124_state *st = iio_priv(indio_dev);
0722     bool bit_set;
0723     int ret;
0724     int i;
0725 
0726     mutex_lock(&st->cfgs_lock);
0727     for (i = 0; i < st->num_channels; i++) {
0728         bit_set = test_bit(i, scan_mask);
0729         if (bit_set)
0730             ret = __ad7124_set_channel(&st->sd, i);
0731         else
0732             ret = ad7124_spi_write_mask(st, AD7124_CHANNEL(i), AD7124_CHANNEL_EN_MSK,
0733                             0, 2);
0734         if (ret < 0) {
0735             mutex_unlock(&st->cfgs_lock);
0736 
0737             return ret;
0738         }
0739     }
0740 
0741     mutex_unlock(&st->cfgs_lock);
0742 
0743     return 0;
0744 }
0745 
0746 static const struct iio_info ad7124_info = {
0747     .read_raw = ad7124_read_raw,
0748     .write_raw = ad7124_write_raw,
0749     .debugfs_reg_access = &ad7124_reg_access,
0750     .validate_trigger = ad_sd_validate_trigger,
0751     .update_scan_mode = ad7124_update_scan_mode,
0752     .attrs = &ad7124_attrs_group,
0753 };
0754 
0755 static int ad7124_soft_reset(struct ad7124_state *st)
0756 {
0757     unsigned int readval, timeout;
0758     int ret;
0759 
0760     ret = ad_sd_reset(&st->sd, 64);
0761     if (ret < 0)
0762         return ret;
0763 
0764     timeout = 100;
0765     do {
0766         ret = ad_sd_read_reg(&st->sd, AD7124_STATUS, 1, &readval);
0767         if (ret < 0)
0768             return ret;
0769 
0770         if (!(readval & AD7124_STATUS_POR_FLAG_MSK))
0771             return 0;
0772 
0773         /* The AD7124 requires typically 2ms to power up and settle */
0774         usleep_range(100, 2000);
0775     } while (--timeout);
0776 
0777     dev_err(&st->sd.spi->dev, "Soft reset failed\n");
0778 
0779     return -EIO;
0780 }
0781 
0782 static int ad7124_check_chip_id(struct ad7124_state *st)
0783 {
0784     unsigned int readval, chip_id, silicon_rev;
0785     int ret;
0786 
0787     ret = ad_sd_read_reg(&st->sd, AD7124_ID, 1, &readval);
0788     if (ret < 0)
0789         return ret;
0790 
0791     chip_id = AD7124_DEVICE_ID_GET(readval);
0792     silicon_rev = AD7124_SILICON_REV_GET(readval);
0793 
0794     if (chip_id != st->chip_info->chip_id) {
0795         dev_err(&st->sd.spi->dev,
0796             "Chip ID mismatch: expected %u, got %u\n",
0797             st->chip_info->chip_id, chip_id);
0798         return -ENODEV;
0799     }
0800 
0801     if (silicon_rev == 0) {
0802         dev_err(&st->sd.spi->dev,
0803             "Silicon revision empty. Chip may not be present\n");
0804         return -ENODEV;
0805     }
0806 
0807     return 0;
0808 }
0809 
0810 static int ad7124_of_parse_channel_config(struct iio_dev *indio_dev,
0811                       struct device_node *np)
0812 {
0813     struct ad7124_state *st = iio_priv(indio_dev);
0814     struct ad7124_channel_config *cfg;
0815     struct ad7124_channel *channels;
0816     struct device_node *child;
0817     struct iio_chan_spec *chan;
0818     unsigned int ain[2], channel = 0, tmp;
0819     int ret;
0820 
0821     st->num_channels = of_get_available_child_count(np);
0822     if (!st->num_channels) {
0823         dev_err(indio_dev->dev.parent, "no channel children\n");
0824         return -ENODEV;
0825     }
0826 
0827     chan = devm_kcalloc(indio_dev->dev.parent, st->num_channels,
0828                 sizeof(*chan), GFP_KERNEL);
0829     if (!chan)
0830         return -ENOMEM;
0831 
0832     channels = devm_kcalloc(indio_dev->dev.parent, st->num_channels, sizeof(*channels),
0833                 GFP_KERNEL);
0834     if (!channels)
0835         return -ENOMEM;
0836 
0837     indio_dev->channels = chan;
0838     indio_dev->num_channels = st->num_channels;
0839     st->channels = channels;
0840 
0841     for_each_available_child_of_node(np, child) {
0842         cfg = &st->channels[channel].cfg;
0843 
0844         ret = of_property_read_u32(child, "reg", &channel);
0845         if (ret)
0846             goto err;
0847 
0848         if (channel >= indio_dev->num_channels) {
0849             dev_err(indio_dev->dev.parent,
0850                 "Channel index >= number of channels\n");
0851             ret = -EINVAL;
0852             goto err;
0853         }
0854 
0855         ret = of_property_read_u32_array(child, "diff-channels",
0856                          ain, 2);
0857         if (ret)
0858             goto err;
0859 
0860         st->channels[channel].nr = channel;
0861         st->channels[channel].ain = AD7124_CHANNEL_AINP(ain[0]) |
0862                           AD7124_CHANNEL_AINM(ain[1]);
0863 
0864         cfg->bipolar = of_property_read_bool(child, "bipolar");
0865 
0866         ret = of_property_read_u32(child, "adi,reference-select", &tmp);
0867         if (ret)
0868             cfg->refsel = AD7124_INT_REF;
0869         else
0870             cfg->refsel = tmp;
0871 
0872         cfg->buf_positive = of_property_read_bool(child, "adi,buffered-positive");
0873         cfg->buf_negative = of_property_read_bool(child, "adi,buffered-negative");
0874 
0875         chan[channel] = ad7124_channel_template;
0876         chan[channel].address = channel;
0877         chan[channel].scan_index = channel;
0878         chan[channel].channel = ain[0];
0879         chan[channel].channel2 = ain[1];
0880     }
0881 
0882     return 0;
0883 err:
0884     of_node_put(child);
0885 
0886     return ret;
0887 }
0888 
0889 static int ad7124_setup(struct ad7124_state *st)
0890 {
0891     unsigned int fclk, power_mode;
0892     int i, ret;
0893 
0894     fclk = clk_get_rate(st->mclk);
0895     if (!fclk)
0896         return -EINVAL;
0897 
0898     /* The power mode changes the master clock frequency */
0899     power_mode = ad7124_find_closest_match(ad7124_master_clk_freq_hz,
0900                     ARRAY_SIZE(ad7124_master_clk_freq_hz),
0901                     fclk);
0902     if (fclk != ad7124_master_clk_freq_hz[power_mode]) {
0903         ret = clk_set_rate(st->mclk, fclk);
0904         if (ret)
0905             return ret;
0906     }
0907 
0908     /* Set the power mode */
0909     st->adc_control &= ~AD7124_ADC_CTRL_PWR_MSK;
0910     st->adc_control |= AD7124_ADC_CTRL_PWR(power_mode);
0911     ret = ad_sd_write_reg(&st->sd, AD7124_ADC_CONTROL, 2, st->adc_control);
0912     if (ret < 0)
0913         return ret;
0914 
0915     mutex_init(&st->cfgs_lock);
0916     INIT_KFIFO(st->live_cfgs_fifo);
0917     for (i = 0; i < st->num_channels; i++) {
0918 
0919         ret = ad7124_init_config_vref(st, &st->channels[i].cfg);
0920         if (ret < 0)
0921             return ret;
0922 
0923         /*
0924          * 9.38 SPS is the minimum output data rate supported
0925          * regardless of the selected power mode. Round it up to 10 and
0926          * set all channels to this default value.
0927          */
0928         ad7124_set_channel_odr(st, i, 10);
0929     }
0930 
0931     return ret;
0932 }
0933 
0934 static void ad7124_reg_disable(void *r)
0935 {
0936     regulator_disable(r);
0937 }
0938 
0939 static void ad7124_clk_disable(void *c)
0940 {
0941     clk_disable_unprepare(c);
0942 }
0943 
0944 static int ad7124_probe(struct spi_device *spi)
0945 {
0946     const struct ad7124_chip_info *info;
0947     struct ad7124_state *st;
0948     struct iio_dev *indio_dev;
0949     int i, ret;
0950 
0951     info = of_device_get_match_data(&spi->dev);
0952     if (!info)
0953         return -ENODEV;
0954 
0955     indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
0956     if (!indio_dev)
0957         return -ENOMEM;
0958 
0959     st = iio_priv(indio_dev);
0960 
0961     st->chip_info = info;
0962 
0963     indio_dev->name = st->chip_info->name;
0964     indio_dev->modes = INDIO_DIRECT_MODE;
0965     indio_dev->info = &ad7124_info;
0966 
0967     ret = ad_sd_init(&st->sd, indio_dev, spi, &ad7124_sigma_delta_info);
0968     if (ret < 0)
0969         return ret;
0970 
0971     ret = ad7124_of_parse_channel_config(indio_dev, spi->dev.of_node);
0972     if (ret < 0)
0973         return ret;
0974 
0975     for (i = 0; i < ARRAY_SIZE(st->vref); i++) {
0976         if (i == AD7124_INT_REF)
0977             continue;
0978 
0979         st->vref[i] = devm_regulator_get_optional(&spi->dev,
0980                         ad7124_ref_names[i]);
0981         if (PTR_ERR(st->vref[i]) == -ENODEV)
0982             continue;
0983         else if (IS_ERR(st->vref[i]))
0984             return PTR_ERR(st->vref[i]);
0985 
0986         ret = regulator_enable(st->vref[i]);
0987         if (ret)
0988             return ret;
0989 
0990         ret = devm_add_action_or_reset(&spi->dev, ad7124_reg_disable,
0991                            st->vref[i]);
0992         if (ret)
0993             return ret;
0994     }
0995 
0996     st->mclk = devm_clk_get(&spi->dev, "mclk");
0997     if (IS_ERR(st->mclk))
0998         return PTR_ERR(st->mclk);
0999 
1000     ret = clk_prepare_enable(st->mclk);
1001     if (ret < 0)
1002         return ret;
1003 
1004     ret = devm_add_action_or_reset(&spi->dev, ad7124_clk_disable, st->mclk);
1005     if (ret)
1006         return ret;
1007 
1008     ret = ad7124_soft_reset(st);
1009     if (ret < 0)
1010         return ret;
1011 
1012     ret = ad7124_check_chip_id(st);
1013     if (ret)
1014         return ret;
1015 
1016     ret = ad7124_setup(st);
1017     if (ret < 0)
1018         return ret;
1019 
1020     ret = devm_ad_sd_setup_buffer_and_trigger(&spi->dev, indio_dev);
1021     if (ret < 0)
1022         return ret;
1023 
1024     return devm_iio_device_register(&spi->dev, indio_dev);
1025 
1026 }
1027 
1028 static const struct of_device_id ad7124_of_match[] = {
1029     { .compatible = "adi,ad7124-4",
1030         .data = &ad7124_chip_info_tbl[ID_AD7124_4], },
1031     { .compatible = "adi,ad7124-8",
1032         .data = &ad7124_chip_info_tbl[ID_AD7124_8], },
1033     { },
1034 };
1035 MODULE_DEVICE_TABLE(of, ad7124_of_match);
1036 
1037 static struct spi_driver ad71124_driver = {
1038     .driver = {
1039         .name = "ad7124",
1040         .of_match_table = ad7124_of_match,
1041     },
1042     .probe = ad7124_probe,
1043 };
1044 module_spi_driver(ad71124_driver);
1045 
1046 MODULE_AUTHOR("Stefan Popa <stefan.popa@analog.com>");
1047 MODULE_DESCRIPTION("Analog Devices AD7124 SPI driver");
1048 MODULE_LICENSE("GPL");
1049 MODULE_IMPORT_NS(IIO_AD_SIGMA_DELTA);
[ Source navigation ] [ Diff markup ] [ Identifier search ] [ general search ]

This page was automatically generated by the 2.1.0 LXR engine.

The LXR team
Valid CSS 2.1! Valid HTML 4.01!