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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (C) ST-Ericsson SA 2010
0004  *
0005  * Author: Arun R Murthy <arun.murthy@stericsson.com>
0006  * Author: Daniel Willerud <daniel.willerud@stericsson.com>
0007  * Author: Johan Palsson <johan.palsson@stericsson.com>
0008  * Author: M'boumba Cedric Madianga
0009  * Author: Linus Walleij <linus.walleij@linaro.org>
0010  *
0011  * AB8500 General Purpose ADC driver. The AB8500 uses reference voltages:
0012  * VinVADC, and VADC relative to GND to do its job. It monitors main and backup
0013  * battery voltages, AC (mains) voltage, USB cable voltage, as well as voltages
0014  * representing the temperature of the chip die and battery, accessory
0015  * detection by resistance measurements using relative voltages and GSM burst
0016  * information.
0017  *
0018  * Some of the voltages are measured on external pins on the IC, such as
0019  * battery temperature or "ADC aux" 1 and 2. Other voltages are internal rails
0020  * from other parts of the ASIC such as main charger voltage, main and battery
0021  * backup voltage or USB VBUS voltage. For this reason drivers for other
0022  * parts of the system are required to obtain handles to the ADC to do work
0023  * for them and the IIO driver provides arbitration among these consumers.
0024  */
0025 #include <linux/init.h>
0026 #include <linux/bits.h>
0027 #include <linux/iio/iio.h>
0028 #include <linux/iio/sysfs.h>
0029 #include <linux/device.h>
0030 #include <linux/interrupt.h>
0031 #include <linux/spinlock.h>
0032 #include <linux/delay.h>
0033 #include <linux/pm_runtime.h>
0034 #include <linux/platform_device.h>
0035 #include <linux/completion.h>
0036 #include <linux/regulator/consumer.h>
0037 #include <linux/random.h>
0038 #include <linux/err.h>
0039 #include <linux/slab.h>
0040 #include <linux/mfd/abx500.h>
0041 #include <linux/mfd/abx500/ab8500.h>
0042 
0043 /* GPADC register offsets and bit definitions */
0044 
0045 #define AB8500_GPADC_CTRL1_REG      0x00
0046 /* GPADC control register 1 bits */
0047 #define AB8500_GPADC_CTRL1_DISABLE      0x00
0048 #define AB8500_GPADC_CTRL1_ENABLE       BIT(0)
0049 #define AB8500_GPADC_CTRL1_TRIG_ENA     BIT(1)
0050 #define AB8500_GPADC_CTRL1_START_SW_CONV    BIT(2)
0051 #define AB8500_GPADC_CTRL1_BTEMP_PULL_UP    BIT(3)
0052 /* 0 = use rising edge, 1 = use falling edge */
0053 #define AB8500_GPADC_CTRL1_TRIG_EDGE        BIT(4)
0054 /* 0 = use VTVOUT, 1 = use VRTC as pull-up supply for battery temp NTC */
0055 #define AB8500_GPADC_CTRL1_PUPSUPSEL        BIT(5)
0056 #define AB8500_GPADC_CTRL1_BUF_ENA      BIT(6)
0057 #define AB8500_GPADC_CTRL1_ICHAR_ENA        BIT(7)
0058 
0059 #define AB8500_GPADC_CTRL2_REG      0x01
0060 #define AB8500_GPADC_CTRL3_REG      0x02
0061 /*
0062  * GPADC control register 2 and 3 bits
0063  * the bit layout is the same for SW and HW conversion set-up
0064  */
0065 #define AB8500_GPADC_CTRL2_AVG_1        0x00
0066 #define AB8500_GPADC_CTRL2_AVG_4        BIT(5)
0067 #define AB8500_GPADC_CTRL2_AVG_8        BIT(6)
0068 #define AB8500_GPADC_CTRL2_AVG_16       (BIT(5) | BIT(6))
0069 
0070 enum ab8500_gpadc_channel {
0071     AB8500_GPADC_CHAN_UNUSED = 0x00,
0072     AB8500_GPADC_CHAN_BAT_CTRL = 0x01,
0073     AB8500_GPADC_CHAN_BAT_TEMP = 0x02,
0074     /* This is not used on AB8505 */
0075     AB8500_GPADC_CHAN_MAIN_CHARGER = 0x03,
0076     AB8500_GPADC_CHAN_ACC_DET_1 = 0x04,
0077     AB8500_GPADC_CHAN_ACC_DET_2 = 0x05,
0078     AB8500_GPADC_CHAN_ADC_AUX_1 = 0x06,
0079     AB8500_GPADC_CHAN_ADC_AUX_2 = 0x07,
0080     AB8500_GPADC_CHAN_VBAT_A = 0x08,
0081     AB8500_GPADC_CHAN_VBUS = 0x09,
0082     AB8500_GPADC_CHAN_MAIN_CHARGER_CURRENT = 0x0a,
0083     AB8500_GPADC_CHAN_USB_CHARGER_CURRENT = 0x0b,
0084     AB8500_GPADC_CHAN_BACKUP_BAT = 0x0c,
0085     /* Only on AB8505 */
0086     AB8505_GPADC_CHAN_DIE_TEMP = 0x0d,
0087     AB8500_GPADC_CHAN_ID = 0x0e,
0088     AB8500_GPADC_CHAN_INTERNAL_TEST_1 = 0x0f,
0089     AB8500_GPADC_CHAN_INTERNAL_TEST_2 = 0x10,
0090     AB8500_GPADC_CHAN_INTERNAL_TEST_3 = 0x11,
0091     /* FIXME: Applicable to all ASIC variants? */
0092     AB8500_GPADC_CHAN_XTAL_TEMP = 0x12,
0093     AB8500_GPADC_CHAN_VBAT_TRUE_MEAS = 0x13,
0094     /* FIXME: Doesn't seem to work with pure AB8500 */
0095     AB8500_GPADC_CHAN_BAT_CTRL_AND_IBAT = 0x1c,
0096     AB8500_GPADC_CHAN_VBAT_MEAS_AND_IBAT = 0x1d,
0097     AB8500_GPADC_CHAN_VBAT_TRUE_MEAS_AND_IBAT = 0x1e,
0098     AB8500_GPADC_CHAN_BAT_TEMP_AND_IBAT = 0x1f,
0099     /*
0100      * Virtual channel used only for ibat conversion to ampere.
0101      * Battery current conversion (ibat) cannot be requested as a
0102      * single conversion but it is always requested in combination
0103      * with other input requests.
0104      */
0105     AB8500_GPADC_CHAN_IBAT_VIRTUAL = 0xFF,
0106 };
0107 
0108 #define AB8500_GPADC_AUTO_TIMER_REG 0x03
0109 
0110 #define AB8500_GPADC_STAT_REG       0x04
0111 #define AB8500_GPADC_STAT_BUSY      BIT(0)
0112 
0113 #define AB8500_GPADC_MANDATAL_REG   0x05
0114 #define AB8500_GPADC_MANDATAH_REG   0x06
0115 #define AB8500_GPADC_AUTODATAL_REG  0x07
0116 #define AB8500_GPADC_AUTODATAH_REG  0x08
0117 #define AB8500_GPADC_MUX_CTRL_REG   0x09
0118 #define AB8540_GPADC_MANDATA2L_REG  0x09
0119 #define AB8540_GPADC_MANDATA2H_REG  0x0A
0120 #define AB8540_GPADC_APEAAX_REG     0x10
0121 #define AB8540_GPADC_APEAAT_REG     0x11
0122 #define AB8540_GPADC_APEAAM_REG     0x12
0123 #define AB8540_GPADC_APEAAH_REG     0x13
0124 #define AB8540_GPADC_APEAAL_REG     0x14
0125 
0126 /*
0127  * OTP register offsets
0128  * Bank : 0x15
0129  */
0130 #define AB8500_GPADC_CAL_1  0x0F
0131 #define AB8500_GPADC_CAL_2  0x10
0132 #define AB8500_GPADC_CAL_3  0x11
0133 #define AB8500_GPADC_CAL_4  0x12
0134 #define AB8500_GPADC_CAL_5  0x13
0135 #define AB8500_GPADC_CAL_6  0x14
0136 #define AB8500_GPADC_CAL_7  0x15
0137 /* New calibration for 8540 */
0138 #define AB8540_GPADC_OTP4_REG_7 0x38
0139 #define AB8540_GPADC_OTP4_REG_6 0x39
0140 #define AB8540_GPADC_OTP4_REG_5 0x3A
0141 
0142 #define AB8540_GPADC_DIS_ZERO   0x00
0143 #define AB8540_GPADC_EN_VBIAS_XTAL_TEMP 0x02
0144 
0145 /* GPADC constants from AB8500 spec, UM0836 */
0146 #define AB8500_ADC_RESOLUTION       1024
0147 #define AB8500_ADC_CH_BTEMP_MIN     0
0148 #define AB8500_ADC_CH_BTEMP_MAX     1350
0149 #define AB8500_ADC_CH_DIETEMP_MIN   0
0150 #define AB8500_ADC_CH_DIETEMP_MAX   1350
0151 #define AB8500_ADC_CH_CHG_V_MIN     0
0152 #define AB8500_ADC_CH_CHG_V_MAX     20030
0153 #define AB8500_ADC_CH_ACCDET2_MIN   0
0154 #define AB8500_ADC_CH_ACCDET2_MAX   2500
0155 #define AB8500_ADC_CH_VBAT_MIN      2300
0156 #define AB8500_ADC_CH_VBAT_MAX      4800
0157 #define AB8500_ADC_CH_CHG_I_MIN     0
0158 #define AB8500_ADC_CH_CHG_I_MAX     1500
0159 #define AB8500_ADC_CH_BKBAT_MIN     0
0160 #define AB8500_ADC_CH_BKBAT_MAX     3200
0161 
0162 /* GPADC constants from AB8540 spec */
0163 #define AB8500_ADC_CH_IBAT_MIN      (-6000) /* mA range measured by ADC for ibat */
0164 #define AB8500_ADC_CH_IBAT_MAX      6000
0165 #define AB8500_ADC_CH_IBAT_MIN_V    (-60)   /* mV range measured by ADC for ibat */
0166 #define AB8500_ADC_CH_IBAT_MAX_V    60
0167 #define AB8500_GPADC_IBAT_VDROP_L   (-56)  /* mV */
0168 #define AB8500_GPADC_IBAT_VDROP_H   56
0169 
0170 /* This is used to not lose precision when dividing to get gain and offset */
0171 #define AB8500_GPADC_CALIB_SCALE    1000
0172 /*
0173  * Number of bits shift used to not lose precision
0174  * when dividing to get ibat gain.
0175  */
0176 #define AB8500_GPADC_CALIB_SHIFT_IBAT   20
0177 
0178 /* Time in ms before disabling regulator */
0179 #define AB8500_GPADC_AUTOSUSPEND_DELAY  1
0180 
0181 #define AB8500_GPADC_CONVERSION_TIME    500 /* ms */
0182 
0183 enum ab8500_cal_channels {
0184     AB8500_CAL_VMAIN = 0,
0185     AB8500_CAL_BTEMP,
0186     AB8500_CAL_VBAT,
0187     AB8500_CAL_IBAT,
0188     AB8500_CAL_NR,
0189 };
0190 
0191 /**
0192  * struct ab8500_adc_cal_data - Table for storing gain and offset for the
0193  * calibrated ADC channels
0194  * @gain: Gain of the ADC channel
0195  * @offset: Offset of the ADC channel
0196  * @otp_calib_hi: Calibration from OTP
0197  * @otp_calib_lo: Calibration from OTP
0198  */
0199 struct ab8500_adc_cal_data {
0200     s64 gain;
0201     s64 offset;
0202     u16 otp_calib_hi;
0203     u16 otp_calib_lo;
0204 };
0205 
0206 /**
0207  * struct ab8500_gpadc_chan_info - per-channel GPADC info
0208  * @name: name of the channel
0209  * @id: the internal AB8500 ID number for the channel
0210  * @hardware_control: indicate that we want to use hardware ADC control
0211  * on this channel, the default is software ADC control. Hardware control
0212  * is normally only used to test the battery voltage during GSM bursts
0213  * and needs a hardware trigger on the GPADCTrig pin of the ASIC.
0214  * @falling_edge: indicate that we want to trigger on falling edge
0215  * rather than rising edge, rising edge is the default
0216  * @avg_sample: how many samples to average: must be 1, 4, 8 or 16.
0217  * @trig_timer: how long to wait for the trigger, in 32kHz periods:
0218  * 0 .. 255 periods
0219  */
0220 struct ab8500_gpadc_chan_info {
0221     const char *name;
0222     u8 id;
0223     bool hardware_control;
0224     bool falling_edge;
0225     u8 avg_sample;
0226     u8 trig_timer;
0227 };
0228 
0229 /**
0230  * struct ab8500_gpadc - AB8500 GPADC device information
0231  * @dev: pointer to the containing device
0232  * @ab8500: pointer to the parent AB8500 device
0233  * @chans: internal per-channel information container
0234  * @nchans: number of channels
0235  * @complete: pointer to the completion that indicates
0236  * the completion of an gpadc conversion cycle
0237  * @vddadc: pointer to the regulator supplying VDDADC
0238  * @irq_sw: interrupt number that is used by gpadc for software ADC conversion
0239  * @irq_hw: interrupt number that is used by gpadc for hardware ADC conversion
0240  * @cal_data: array of ADC calibration data structs
0241  */
0242 struct ab8500_gpadc {
0243     struct device *dev;
0244     struct ab8500 *ab8500;
0245     struct ab8500_gpadc_chan_info *chans;
0246     unsigned int nchans;
0247     struct completion complete;
0248     struct regulator *vddadc;
0249     int irq_sw;
0250     int irq_hw;
0251     struct ab8500_adc_cal_data cal_data[AB8500_CAL_NR];
0252 };
0253 
0254 static struct ab8500_gpadc_chan_info *
0255 ab8500_gpadc_get_channel(struct ab8500_gpadc *gpadc, u8 chan)
0256 {
0257     struct ab8500_gpadc_chan_info *ch;
0258     int i;
0259 
0260     for (i = 0; i < gpadc->nchans; i++) {
0261         ch = &gpadc->chans[i];
0262         if (ch->id == chan)
0263             break;
0264     }
0265     if (i == gpadc->nchans)
0266         return NULL;
0267 
0268     return ch;
0269 }
0270 
0271 /**
0272  * ab8500_gpadc_ad_to_voltage() - Convert a raw ADC value to a voltage
0273  * @gpadc: GPADC instance
0274  * @ch: the sampled channel this raw value is coming from
0275  * @ad_value: the raw value
0276  */
0277 static int ab8500_gpadc_ad_to_voltage(struct ab8500_gpadc *gpadc,
0278                       enum ab8500_gpadc_channel ch,
0279                       int ad_value)
0280 {
0281     int res;
0282 
0283     switch (ch) {
0284     case AB8500_GPADC_CHAN_MAIN_CHARGER:
0285         /* No calibration data available: just interpolate */
0286         if (!gpadc->cal_data[AB8500_CAL_VMAIN].gain) {
0287             res = AB8500_ADC_CH_CHG_V_MIN + (AB8500_ADC_CH_CHG_V_MAX -
0288                 AB8500_ADC_CH_CHG_V_MIN) * ad_value /
0289                 AB8500_ADC_RESOLUTION;
0290             break;
0291         }
0292         /* Here we can use calibration */
0293         res = (int) (ad_value * gpadc->cal_data[AB8500_CAL_VMAIN].gain +
0294             gpadc->cal_data[AB8500_CAL_VMAIN].offset) / AB8500_GPADC_CALIB_SCALE;
0295         break;
0296 
0297     case AB8500_GPADC_CHAN_BAT_CTRL:
0298     case AB8500_GPADC_CHAN_BAT_TEMP:
0299     case AB8500_GPADC_CHAN_ACC_DET_1:
0300     case AB8500_GPADC_CHAN_ADC_AUX_1:
0301     case AB8500_GPADC_CHAN_ADC_AUX_2:
0302     case AB8500_GPADC_CHAN_XTAL_TEMP:
0303         /* No calibration data available: just interpolate */
0304         if (!gpadc->cal_data[AB8500_CAL_BTEMP].gain) {
0305             res = AB8500_ADC_CH_BTEMP_MIN + (AB8500_ADC_CH_BTEMP_MAX -
0306                 AB8500_ADC_CH_BTEMP_MIN) * ad_value /
0307                 AB8500_ADC_RESOLUTION;
0308             break;
0309         }
0310         /* Here we can use calibration */
0311         res = (int) (ad_value * gpadc->cal_data[AB8500_CAL_BTEMP].gain +
0312             gpadc->cal_data[AB8500_CAL_BTEMP].offset) / AB8500_GPADC_CALIB_SCALE;
0313         break;
0314 
0315     case AB8500_GPADC_CHAN_VBAT_A:
0316     case AB8500_GPADC_CHAN_VBAT_TRUE_MEAS:
0317         /* No calibration data available: just interpolate */
0318         if (!gpadc->cal_data[AB8500_CAL_VBAT].gain) {
0319             res = AB8500_ADC_CH_VBAT_MIN + (AB8500_ADC_CH_VBAT_MAX -
0320                 AB8500_ADC_CH_VBAT_MIN) * ad_value /
0321                 AB8500_ADC_RESOLUTION;
0322             break;
0323         }
0324         /* Here we can use calibration */
0325         res = (int) (ad_value * gpadc->cal_data[AB8500_CAL_VBAT].gain +
0326             gpadc->cal_data[AB8500_CAL_VBAT].offset) / AB8500_GPADC_CALIB_SCALE;
0327         break;
0328 
0329     case AB8505_GPADC_CHAN_DIE_TEMP:
0330         res = AB8500_ADC_CH_DIETEMP_MIN +
0331             (AB8500_ADC_CH_DIETEMP_MAX - AB8500_ADC_CH_DIETEMP_MIN) * ad_value /
0332             AB8500_ADC_RESOLUTION;
0333         break;
0334 
0335     case AB8500_GPADC_CHAN_ACC_DET_2:
0336         res = AB8500_ADC_CH_ACCDET2_MIN +
0337             (AB8500_ADC_CH_ACCDET2_MAX - AB8500_ADC_CH_ACCDET2_MIN) * ad_value /
0338             AB8500_ADC_RESOLUTION;
0339         break;
0340 
0341     case AB8500_GPADC_CHAN_VBUS:
0342         res = AB8500_ADC_CH_CHG_V_MIN +
0343             (AB8500_ADC_CH_CHG_V_MAX - AB8500_ADC_CH_CHG_V_MIN) * ad_value /
0344             AB8500_ADC_RESOLUTION;
0345         break;
0346 
0347     case AB8500_GPADC_CHAN_MAIN_CHARGER_CURRENT:
0348     case AB8500_GPADC_CHAN_USB_CHARGER_CURRENT:
0349         res = AB8500_ADC_CH_CHG_I_MIN +
0350             (AB8500_ADC_CH_CHG_I_MAX - AB8500_ADC_CH_CHG_I_MIN) * ad_value /
0351             AB8500_ADC_RESOLUTION;
0352         break;
0353 
0354     case AB8500_GPADC_CHAN_BACKUP_BAT:
0355         res = AB8500_ADC_CH_BKBAT_MIN +
0356             (AB8500_ADC_CH_BKBAT_MAX - AB8500_ADC_CH_BKBAT_MIN) * ad_value /
0357             AB8500_ADC_RESOLUTION;
0358         break;
0359 
0360     case AB8500_GPADC_CHAN_IBAT_VIRTUAL:
0361         /* No calibration data available: just interpolate */
0362         if (!gpadc->cal_data[AB8500_CAL_IBAT].gain) {
0363             res = AB8500_ADC_CH_IBAT_MIN + (AB8500_ADC_CH_IBAT_MAX -
0364                 AB8500_ADC_CH_IBAT_MIN) * ad_value /
0365                 AB8500_ADC_RESOLUTION;
0366             break;
0367         }
0368         /* Here we can use calibration */
0369         res = (int) (ad_value * gpadc->cal_data[AB8500_CAL_IBAT].gain +
0370                 gpadc->cal_data[AB8500_CAL_IBAT].offset)
0371                 >> AB8500_GPADC_CALIB_SHIFT_IBAT;
0372         break;
0373 
0374     default:
0375         dev_err(gpadc->dev,
0376             "unknown channel ID: %d, not possible to convert\n",
0377             ch);
0378         res = -EINVAL;
0379         break;
0380 
0381     }
0382 
0383     return res;
0384 }
0385 
0386 static int ab8500_gpadc_read(struct ab8500_gpadc *gpadc,
0387                  const struct ab8500_gpadc_chan_info *ch,
0388                  int *ibat)
0389 {
0390     int ret;
0391     int looplimit = 0;
0392     unsigned long completion_timeout;
0393     u8 val;
0394     u8 low_data, high_data, low_data2, high_data2;
0395     u8 ctrl1;
0396     u8 ctrl23;
0397     unsigned int delay_min = 0;
0398     unsigned int delay_max = 0;
0399     u8 data_low_addr, data_high_addr;
0400 
0401     if (!gpadc)
0402         return -ENODEV;
0403 
0404     /* check if conversion is supported */
0405     if ((gpadc->irq_sw <= 0) && !ch->hardware_control)
0406         return -ENOTSUPP;
0407     if ((gpadc->irq_hw <= 0) && ch->hardware_control)
0408         return -ENOTSUPP;
0409 
0410     /* Enable vddadc by grabbing PM runtime */
0411     pm_runtime_get_sync(gpadc->dev);
0412 
0413     /* Check if ADC is not busy, lock and proceed */
0414     do {
0415         ret = abx500_get_register_interruptible(gpadc->dev,
0416             AB8500_GPADC, AB8500_GPADC_STAT_REG, &val);
0417         if (ret < 0)
0418             goto out;
0419         if (!(val & AB8500_GPADC_STAT_BUSY))
0420             break;
0421         msleep(20);
0422     } while (++looplimit < 10);
0423     if (looplimit >= 10 && (val & AB8500_GPADC_STAT_BUSY)) {
0424         dev_err(gpadc->dev, "gpadc_conversion: GPADC busy");
0425         ret = -EINVAL;
0426         goto out;
0427     }
0428 
0429     /* Enable GPADC */
0430     ctrl1 = AB8500_GPADC_CTRL1_ENABLE;
0431 
0432     /* Select the channel source and set average samples */
0433     switch (ch->avg_sample) {
0434     case 1:
0435         ctrl23 = ch->id | AB8500_GPADC_CTRL2_AVG_1;
0436         break;
0437     case 4:
0438         ctrl23 = ch->id | AB8500_GPADC_CTRL2_AVG_4;
0439         break;
0440     case 8:
0441         ctrl23 = ch->id | AB8500_GPADC_CTRL2_AVG_8;
0442         break;
0443     default:
0444         ctrl23 = ch->id | AB8500_GPADC_CTRL2_AVG_16;
0445         break;
0446     }
0447 
0448     if (ch->hardware_control) {
0449         ret = abx500_set_register_interruptible(gpadc->dev,
0450                 AB8500_GPADC, AB8500_GPADC_CTRL3_REG, ctrl23);
0451         ctrl1 |= AB8500_GPADC_CTRL1_TRIG_ENA;
0452         if (ch->falling_edge)
0453             ctrl1 |= AB8500_GPADC_CTRL1_TRIG_EDGE;
0454     } else {
0455         ret = abx500_set_register_interruptible(gpadc->dev,
0456                 AB8500_GPADC, AB8500_GPADC_CTRL2_REG, ctrl23);
0457     }
0458     if (ret < 0) {
0459         dev_err(gpadc->dev,
0460             "gpadc_conversion: set avg samples failed\n");
0461         goto out;
0462     }
0463 
0464     /*
0465      * Enable ADC, buffering, select rising edge and enable ADC path
0466      * charging current sense if it needed, ABB 3.0 needs some special
0467      * treatment too.
0468      */
0469     switch (ch->id) {
0470     case AB8500_GPADC_CHAN_MAIN_CHARGER_CURRENT:
0471     case AB8500_GPADC_CHAN_USB_CHARGER_CURRENT:
0472         ctrl1 |= AB8500_GPADC_CTRL1_BUF_ENA |
0473             AB8500_GPADC_CTRL1_ICHAR_ENA;
0474         break;
0475     case AB8500_GPADC_CHAN_BAT_TEMP:
0476         if (!is_ab8500_2p0_or_earlier(gpadc->ab8500)) {
0477             ctrl1 |= AB8500_GPADC_CTRL1_BUF_ENA |
0478                 AB8500_GPADC_CTRL1_BTEMP_PULL_UP;
0479             /*
0480              * Delay might be needed for ABB8500 cut 3.0, if not,
0481              * remove when hardware will be available
0482              */
0483             delay_min = 1000; /* Delay in micro seconds */
0484             delay_max = 10000; /* large range optimises sleepmode */
0485             break;
0486         }
0487         fallthrough;
0488     default:
0489         ctrl1 |= AB8500_GPADC_CTRL1_BUF_ENA;
0490         break;
0491     }
0492 
0493     /* Write configuration to control register 1 */
0494     ret = abx500_set_register_interruptible(gpadc->dev,
0495         AB8500_GPADC, AB8500_GPADC_CTRL1_REG, ctrl1);
0496     if (ret < 0) {
0497         dev_err(gpadc->dev,
0498             "gpadc_conversion: set Control register failed\n");
0499         goto out;
0500     }
0501 
0502     if (delay_min != 0)
0503         usleep_range(delay_min, delay_max);
0504 
0505     if (ch->hardware_control) {
0506         /* Set trigger delay timer */
0507         ret = abx500_set_register_interruptible(gpadc->dev,
0508             AB8500_GPADC, AB8500_GPADC_AUTO_TIMER_REG,
0509             ch->trig_timer);
0510         if (ret < 0) {
0511             dev_err(gpadc->dev,
0512                 "gpadc_conversion: trig timer failed\n");
0513             goto out;
0514         }
0515         completion_timeout = 2 * HZ;
0516         data_low_addr = AB8500_GPADC_AUTODATAL_REG;
0517         data_high_addr = AB8500_GPADC_AUTODATAH_REG;
0518     } else {
0519         /* Start SW conversion */
0520         ret = abx500_mask_and_set_register_interruptible(gpadc->dev,
0521             AB8500_GPADC, AB8500_GPADC_CTRL1_REG,
0522             AB8500_GPADC_CTRL1_START_SW_CONV,
0523             AB8500_GPADC_CTRL1_START_SW_CONV);
0524         if (ret < 0) {
0525             dev_err(gpadc->dev,
0526                 "gpadc_conversion: start s/w conv failed\n");
0527             goto out;
0528         }
0529         completion_timeout = msecs_to_jiffies(AB8500_GPADC_CONVERSION_TIME);
0530         data_low_addr = AB8500_GPADC_MANDATAL_REG;
0531         data_high_addr = AB8500_GPADC_MANDATAH_REG;
0532     }
0533 
0534     /* Wait for completion of conversion */
0535     if (!wait_for_completion_timeout(&gpadc->complete,
0536             completion_timeout)) {
0537         dev_err(gpadc->dev,
0538             "timeout didn't receive GPADC conv interrupt\n");
0539         ret = -EINVAL;
0540         goto out;
0541     }
0542 
0543     /* Read the converted RAW data */
0544     ret = abx500_get_register_interruptible(gpadc->dev,
0545             AB8500_GPADC, data_low_addr, &low_data);
0546     if (ret < 0) {
0547         dev_err(gpadc->dev,
0548             "gpadc_conversion: read low data failed\n");
0549         goto out;
0550     }
0551 
0552     ret = abx500_get_register_interruptible(gpadc->dev,
0553         AB8500_GPADC, data_high_addr, &high_data);
0554     if (ret < 0) {
0555         dev_err(gpadc->dev,
0556             "gpadc_conversion: read high data failed\n");
0557         goto out;
0558     }
0559 
0560     /* Check if double conversion is required */
0561     if ((ch->id == AB8500_GPADC_CHAN_BAT_CTRL_AND_IBAT) ||
0562         (ch->id == AB8500_GPADC_CHAN_VBAT_MEAS_AND_IBAT) ||
0563         (ch->id == AB8500_GPADC_CHAN_VBAT_TRUE_MEAS_AND_IBAT) ||
0564         (ch->id == AB8500_GPADC_CHAN_BAT_TEMP_AND_IBAT)) {
0565 
0566         if (ch->hardware_control) {
0567             /* not supported */
0568             ret = -ENOTSUPP;
0569             dev_err(gpadc->dev,
0570                 "gpadc_conversion: only SW double conversion supported\n");
0571             goto out;
0572         } else {
0573             /* Read the converted RAW data 2 */
0574             ret = abx500_get_register_interruptible(gpadc->dev,
0575                 AB8500_GPADC, AB8540_GPADC_MANDATA2L_REG,
0576                 &low_data2);
0577             if (ret < 0) {
0578                 dev_err(gpadc->dev,
0579                     "gpadc_conversion: read sw low data 2 failed\n");
0580                 goto out;
0581             }
0582 
0583             ret = abx500_get_register_interruptible(gpadc->dev,
0584                 AB8500_GPADC, AB8540_GPADC_MANDATA2H_REG,
0585                 &high_data2);
0586             if (ret < 0) {
0587                 dev_err(gpadc->dev,
0588                     "gpadc_conversion: read sw high data 2 failed\n");
0589                 goto out;
0590             }
0591             if (ibat != NULL) {
0592                 *ibat = (high_data2 << 8) | low_data2;
0593             } else {
0594                 dev_warn(gpadc->dev,
0595                     "gpadc_conversion: ibat not stored\n");
0596             }
0597 
0598         }
0599     }
0600 
0601     /* Disable GPADC */
0602     ret = abx500_set_register_interruptible(gpadc->dev, AB8500_GPADC,
0603         AB8500_GPADC_CTRL1_REG, AB8500_GPADC_CTRL1_DISABLE);
0604     if (ret < 0) {
0605         dev_err(gpadc->dev, "gpadc_conversion: disable gpadc failed\n");
0606         goto out;
0607     }
0608 
0609     /* This eventually drops the regulator */
0610     pm_runtime_mark_last_busy(gpadc->dev);
0611     pm_runtime_put_autosuspend(gpadc->dev);
0612 
0613     return (high_data << 8) | low_data;
0614 
0615 out:
0616     /*
0617      * It has shown to be needed to turn off the GPADC if an error occurs,
0618      * otherwise we might have problem when waiting for the busy bit in the
0619      * GPADC status register to go low. In V1.1 there wait_for_completion
0620      * seems to timeout when waiting for an interrupt.. Not seen in V2.0
0621      */
0622     (void) abx500_set_register_interruptible(gpadc->dev, AB8500_GPADC,
0623         AB8500_GPADC_CTRL1_REG, AB8500_GPADC_CTRL1_DISABLE);
0624     pm_runtime_put(gpadc->dev);
0625     dev_err(gpadc->dev,
0626         "gpadc_conversion: Failed to AD convert channel %d\n", ch->id);
0627 
0628     return ret;
0629 }
0630 
0631 /**
0632  * ab8500_bm_gpadcconvend_handler() - isr for gpadc conversion completion
0633  * @irq: irq number
0634  * @data: pointer to the data passed during request irq
0635  *
0636  * This is a interrupt service routine for gpadc conversion completion.
0637  * Notifies the gpadc completion is completed and the converted raw value
0638  * can be read from the registers.
0639  * Returns IRQ status(IRQ_HANDLED)
0640  */
0641 static irqreturn_t ab8500_bm_gpadcconvend_handler(int irq, void *data)
0642 {
0643     struct ab8500_gpadc *gpadc = data;
0644 
0645     complete(&gpadc->complete);
0646 
0647     return IRQ_HANDLED;
0648 }
0649 
0650 static int otp_cal_regs[] = {
0651     AB8500_GPADC_CAL_1,
0652     AB8500_GPADC_CAL_2,
0653     AB8500_GPADC_CAL_3,
0654     AB8500_GPADC_CAL_4,
0655     AB8500_GPADC_CAL_5,
0656     AB8500_GPADC_CAL_6,
0657     AB8500_GPADC_CAL_7,
0658 };
0659 
0660 static int otp4_cal_regs[] = {
0661     AB8540_GPADC_OTP4_REG_7,
0662     AB8540_GPADC_OTP4_REG_6,
0663     AB8540_GPADC_OTP4_REG_5,
0664 };
0665 
0666 static void ab8500_gpadc_read_calibration_data(struct ab8500_gpadc *gpadc)
0667 {
0668     int i;
0669     int ret[ARRAY_SIZE(otp_cal_regs)];
0670     u8 gpadc_cal[ARRAY_SIZE(otp_cal_regs)];
0671     int ret_otp4[ARRAY_SIZE(otp4_cal_regs)];
0672     u8 gpadc_otp4[ARRAY_SIZE(otp4_cal_regs)];
0673     int vmain_high, vmain_low;
0674     int btemp_high, btemp_low;
0675     int vbat_high, vbat_low;
0676     int ibat_high, ibat_low;
0677     s64 V_gain, V_offset, V2A_gain, V2A_offset;
0678 
0679     /* First we read all OTP registers and store the error code */
0680     for (i = 0; i < ARRAY_SIZE(otp_cal_regs); i++) {
0681         ret[i] = abx500_get_register_interruptible(gpadc->dev,
0682             AB8500_OTP_EMUL, otp_cal_regs[i],  &gpadc_cal[i]);
0683         if (ret[i] < 0) {
0684             /* Continue anyway: maybe the other registers are OK */
0685             dev_err(gpadc->dev, "%s: read otp reg 0x%02x failed\n",
0686                 __func__, otp_cal_regs[i]);
0687         } else {
0688             /* Put this in the entropy pool as device-unique */
0689             add_device_randomness(&ret[i], sizeof(ret[i]));
0690         }
0691     }
0692 
0693     /*
0694      * The ADC calibration data is stored in OTP registers.
0695      * The layout of the calibration data is outlined below and a more
0696      * detailed description can be found in UM0836
0697      *
0698      * vm_h/l = vmain_high/low
0699      * bt_h/l = btemp_high/low
0700      * vb_h/l = vbat_high/low
0701      *
0702      * Data bits 8500/9540:
0703      * | 7     | 6     | 5     | 4     | 3     | 2     | 1     | 0
0704      * |.......|.......|.......|.......|.......|.......|.......|.......
0705      * |                           | vm_h9 | vm_h8
0706      * |.......|.......|.......|.......|.......|.......|.......|.......
0707      * |           | vm_h7 | vm_h6 | vm_h5 | vm_h4 | vm_h3 | vm_h2
0708      * |.......|.......|.......|.......|.......|.......|.......|.......
0709      * | vm_h1 | vm_h0 | vm_l4 | vm_l3 | vm_l2 | vm_l1 | vm_l0 | bt_h9
0710      * |.......|.......|.......|.......|.......|.......|.......|.......
0711      * | bt_h8 | bt_h7 | bt_h6 | bt_h5 | bt_h4 | bt_h3 | bt_h2 | bt_h1
0712      * |.......|.......|.......|.......|.......|.......|.......|.......
0713      * | bt_h0 | bt_l4 | bt_l3 | bt_l2 | bt_l1 | bt_l0 | vb_h9 | vb_h8
0714      * |.......|.......|.......|.......|.......|.......|.......|.......
0715      * | vb_h7 | vb_h6 | vb_h5 | vb_h4 | vb_h3 | vb_h2 | vb_h1 | vb_h0
0716      * |.......|.......|.......|.......|.......|.......|.......|.......
0717      * | vb_l5 | vb_l4 | vb_l3 | vb_l2 | vb_l1 | vb_l0 |
0718      * |.......|.......|.......|.......|.......|.......|.......|.......
0719      *
0720      * Data bits 8540:
0721      * OTP2
0722      * | 7     | 6     | 5     | 4     | 3     | 2     | 1     | 0
0723      * |.......|.......|.......|.......|.......|.......|.......|.......
0724      * |
0725      * |.......|.......|.......|.......|.......|.......|.......|.......
0726      * | vm_h9 | vm_h8 | vm_h7 | vm_h6 | vm_h5 | vm_h4 | vm_h3 | vm_h2
0727      * |.......|.......|.......|.......|.......|.......|.......|.......
0728      * | vm_h1 | vm_h0 | vm_l4 | vm_l3 | vm_l2 | vm_l1 | vm_l0 | bt_h9
0729      * |.......|.......|.......|.......|.......|.......|.......|.......
0730      * | bt_h8 | bt_h7 | bt_h6 | bt_h5 | bt_h4 | bt_h3 | bt_h2 | bt_h1
0731      * |.......|.......|.......|.......|.......|.......|.......|.......
0732      * | bt_h0 | bt_l4 | bt_l3 | bt_l2 | bt_l1 | bt_l0 | vb_h9 | vb_h8
0733      * |.......|.......|.......|.......|.......|.......|.......|.......
0734      * | vb_h7 | vb_h6 | vb_h5 | vb_h4 | vb_h3 | vb_h2 | vb_h1 | vb_h0
0735      * |.......|.......|.......|.......|.......|.......|.......|.......
0736      * | vb_l5 | vb_l4 | vb_l3 | vb_l2 | vb_l1 | vb_l0 |
0737      * |.......|.......|.......|.......|.......|.......|.......|.......
0738      *
0739      * Data bits 8540:
0740      * OTP4
0741      * | 7     | 6     | 5     | 4     | 3     | 2     | 1     | 0
0742      * |.......|.......|.......|.......|.......|.......|.......|.......
0743      * |                       | ib_h9 | ib_h8 | ib_h7
0744      * |.......|.......|.......|.......|.......|.......|.......|.......
0745      * | ib_h6 | ib_h5 | ib_h4 | ib_h3 | ib_h2 | ib_h1 | ib_h0 | ib_l5
0746      * |.......|.......|.......|.......|.......|.......|.......|.......
0747      * | ib_l4 | ib_l3 | ib_l2 | ib_l1 | ib_l0 |
0748      *
0749      *
0750      * Ideal output ADC codes corresponding to injected input voltages
0751      * during manufacturing is:
0752      *
0753      * vmain_high: Vin = 19500mV / ADC ideal code = 997
0754      * vmain_low:  Vin = 315mV   / ADC ideal code = 16
0755      * btemp_high: Vin = 1300mV  / ADC ideal code = 985
0756      * btemp_low:  Vin = 21mV    / ADC ideal code = 16
0757      * vbat_high:  Vin = 4700mV  / ADC ideal code = 982
0758      * vbat_low:   Vin = 2380mV  / ADC ideal code = 33
0759      */
0760 
0761     if (is_ab8540(gpadc->ab8500)) {
0762         /* Calculate gain and offset for VMAIN if all reads succeeded*/
0763         if (!(ret[1] < 0 || ret[2] < 0)) {
0764             vmain_high = (((gpadc_cal[1] & 0xFF) << 2) |
0765                 ((gpadc_cal[2] & 0xC0) >> 6));
0766             vmain_low = ((gpadc_cal[2] & 0x3E) >> 1);
0767 
0768             gpadc->cal_data[AB8500_CAL_VMAIN].otp_calib_hi =
0769                 (u16)vmain_high;
0770             gpadc->cal_data[AB8500_CAL_VMAIN].otp_calib_lo =
0771                 (u16)vmain_low;
0772 
0773             gpadc->cal_data[AB8500_CAL_VMAIN].gain = AB8500_GPADC_CALIB_SCALE *
0774                 (19500 - 315) / (vmain_high - vmain_low);
0775             gpadc->cal_data[AB8500_CAL_VMAIN].offset = AB8500_GPADC_CALIB_SCALE *
0776                 19500 - (AB8500_GPADC_CALIB_SCALE * (19500 - 315) /
0777                 (vmain_high - vmain_low)) * vmain_high;
0778         } else {
0779             gpadc->cal_data[AB8500_CAL_VMAIN].gain = 0;
0780         }
0781 
0782         /* Read IBAT calibration Data */
0783         for (i = 0; i < ARRAY_SIZE(otp4_cal_regs); i++) {
0784             ret_otp4[i] = abx500_get_register_interruptible(
0785                     gpadc->dev, AB8500_OTP_EMUL,
0786                     otp4_cal_regs[i],  &gpadc_otp4[i]);
0787             if (ret_otp4[i] < 0)
0788                 dev_err(gpadc->dev,
0789                     "%s: read otp4 reg 0x%02x failed\n",
0790                     __func__, otp4_cal_regs[i]);
0791         }
0792 
0793         /* Calculate gain and offset for IBAT if all reads succeeded */
0794         if (!(ret_otp4[0] < 0 || ret_otp4[1] < 0 || ret_otp4[2] < 0)) {
0795             ibat_high = (((gpadc_otp4[0] & 0x07) << 7) |
0796                 ((gpadc_otp4[1] & 0xFE) >> 1));
0797             ibat_low = (((gpadc_otp4[1] & 0x01) << 5) |
0798                 ((gpadc_otp4[2] & 0xF8) >> 3));
0799 
0800             gpadc->cal_data[AB8500_CAL_IBAT].otp_calib_hi =
0801                 (u16)ibat_high;
0802             gpadc->cal_data[AB8500_CAL_IBAT].otp_calib_lo =
0803                 (u16)ibat_low;
0804 
0805             V_gain = ((AB8500_GPADC_IBAT_VDROP_H - AB8500_GPADC_IBAT_VDROP_L)
0806                 << AB8500_GPADC_CALIB_SHIFT_IBAT) / (ibat_high - ibat_low);
0807 
0808             V_offset = (AB8500_GPADC_IBAT_VDROP_H << AB8500_GPADC_CALIB_SHIFT_IBAT) -
0809                 (((AB8500_GPADC_IBAT_VDROP_H - AB8500_GPADC_IBAT_VDROP_L) <<
0810                 AB8500_GPADC_CALIB_SHIFT_IBAT) / (ibat_high - ibat_low))
0811                 * ibat_high;
0812             /*
0813              * Result obtained is in mV (at a scale factor),
0814              * we need to calculate gain and offset to get mA
0815              */
0816             V2A_gain = (AB8500_ADC_CH_IBAT_MAX - AB8500_ADC_CH_IBAT_MIN)/
0817                 (AB8500_ADC_CH_IBAT_MAX_V - AB8500_ADC_CH_IBAT_MIN_V);
0818             V2A_offset = ((AB8500_ADC_CH_IBAT_MAX_V * AB8500_ADC_CH_IBAT_MIN -
0819                 AB8500_ADC_CH_IBAT_MAX * AB8500_ADC_CH_IBAT_MIN_V)
0820                 << AB8500_GPADC_CALIB_SHIFT_IBAT)
0821                 / (AB8500_ADC_CH_IBAT_MAX_V - AB8500_ADC_CH_IBAT_MIN_V);
0822 
0823             gpadc->cal_data[AB8500_CAL_IBAT].gain =
0824                 V_gain * V2A_gain;
0825             gpadc->cal_data[AB8500_CAL_IBAT].offset =
0826                 V_offset * V2A_gain + V2A_offset;
0827         } else {
0828             gpadc->cal_data[AB8500_CAL_IBAT].gain = 0;
0829         }
0830     } else {
0831         /* Calculate gain and offset for VMAIN if all reads succeeded */
0832         if (!(ret[0] < 0 || ret[1] < 0 || ret[2] < 0)) {
0833             vmain_high = (((gpadc_cal[0] & 0x03) << 8) |
0834                 ((gpadc_cal[1] & 0x3F) << 2) |
0835                 ((gpadc_cal[2] & 0xC0) >> 6));
0836             vmain_low = ((gpadc_cal[2] & 0x3E) >> 1);
0837 
0838             gpadc->cal_data[AB8500_CAL_VMAIN].otp_calib_hi =
0839                 (u16)vmain_high;
0840             gpadc->cal_data[AB8500_CAL_VMAIN].otp_calib_lo =
0841                 (u16)vmain_low;
0842 
0843             gpadc->cal_data[AB8500_CAL_VMAIN].gain = AB8500_GPADC_CALIB_SCALE *
0844                 (19500 - 315) / (vmain_high - vmain_low);
0845 
0846             gpadc->cal_data[AB8500_CAL_VMAIN].offset = AB8500_GPADC_CALIB_SCALE *
0847                 19500 - (AB8500_GPADC_CALIB_SCALE * (19500 - 315) /
0848                 (vmain_high - vmain_low)) * vmain_high;
0849         } else {
0850             gpadc->cal_data[AB8500_CAL_VMAIN].gain = 0;
0851         }
0852     }
0853 
0854     /* Calculate gain and offset for BTEMP if all reads succeeded */
0855     if (!(ret[2] < 0 || ret[3] < 0 || ret[4] < 0)) {
0856         btemp_high = (((gpadc_cal[2] & 0x01) << 9) |
0857             (gpadc_cal[3] << 1) | ((gpadc_cal[4] & 0x80) >> 7));
0858         btemp_low = ((gpadc_cal[4] & 0x7C) >> 2);
0859 
0860         gpadc->cal_data[AB8500_CAL_BTEMP].otp_calib_hi = (u16)btemp_high;
0861         gpadc->cal_data[AB8500_CAL_BTEMP].otp_calib_lo = (u16)btemp_low;
0862 
0863         gpadc->cal_data[AB8500_CAL_BTEMP].gain =
0864             AB8500_GPADC_CALIB_SCALE * (1300 - 21) / (btemp_high - btemp_low);
0865         gpadc->cal_data[AB8500_CAL_BTEMP].offset = AB8500_GPADC_CALIB_SCALE * 1300 -
0866             (AB8500_GPADC_CALIB_SCALE * (1300 - 21) / (btemp_high - btemp_low))
0867             * btemp_high;
0868     } else {
0869         gpadc->cal_data[AB8500_CAL_BTEMP].gain = 0;
0870     }
0871 
0872     /* Calculate gain and offset for VBAT if all reads succeeded */
0873     if (!(ret[4] < 0 || ret[5] < 0 || ret[6] < 0)) {
0874         vbat_high = (((gpadc_cal[4] & 0x03) << 8) | gpadc_cal[5]);
0875         vbat_low = ((gpadc_cal[6] & 0xFC) >> 2);
0876 
0877         gpadc->cal_data[AB8500_CAL_VBAT].otp_calib_hi = (u16)vbat_high;
0878         gpadc->cal_data[AB8500_CAL_VBAT].otp_calib_lo = (u16)vbat_low;
0879 
0880         gpadc->cal_data[AB8500_CAL_VBAT].gain = AB8500_GPADC_CALIB_SCALE *
0881             (4700 - 2380) / (vbat_high - vbat_low);
0882         gpadc->cal_data[AB8500_CAL_VBAT].offset = AB8500_GPADC_CALIB_SCALE * 4700 -
0883             (AB8500_GPADC_CALIB_SCALE * (4700 - 2380) /
0884             (vbat_high - vbat_low)) * vbat_high;
0885     } else {
0886         gpadc->cal_data[AB8500_CAL_VBAT].gain = 0;
0887     }
0888 }
0889 
0890 static int ab8500_gpadc_read_raw(struct iio_dev *indio_dev,
0891                  struct iio_chan_spec const *chan,
0892                  int *val, int *val2, long mask)
0893 {
0894     struct ab8500_gpadc *gpadc = iio_priv(indio_dev);
0895     const struct ab8500_gpadc_chan_info *ch;
0896     int raw_val;
0897     int processed;
0898 
0899     ch = ab8500_gpadc_get_channel(gpadc, chan->address);
0900     if (!ch) {
0901         dev_err(gpadc->dev, "no such channel %lu\n",
0902             chan->address);
0903         return -EINVAL;
0904     }
0905 
0906     raw_val = ab8500_gpadc_read(gpadc, ch, NULL);
0907     if (raw_val < 0)
0908         return raw_val;
0909 
0910     if (mask == IIO_CHAN_INFO_RAW) {
0911         *val = raw_val;
0912         return IIO_VAL_INT;
0913     }
0914 
0915     if (mask == IIO_CHAN_INFO_PROCESSED) {
0916         processed = ab8500_gpadc_ad_to_voltage(gpadc, ch->id, raw_val);
0917         if (processed < 0)
0918             return processed;
0919 
0920         /* Return millivolt or milliamps or millicentigrades */
0921         *val = processed;
0922         return IIO_VAL_INT;
0923     }
0924 
0925     return -EINVAL;
0926 }
0927 
0928 static int ab8500_gpadc_of_xlate(struct iio_dev *indio_dev,
0929                  const struct of_phandle_args *iiospec)
0930 {
0931     int i;
0932 
0933     for (i = 0; i < indio_dev->num_channels; i++)
0934         if (indio_dev->channels[i].channel == iiospec->args[0])
0935             return i;
0936 
0937     return -EINVAL;
0938 }
0939 
0940 static const struct iio_info ab8500_gpadc_info = {
0941     .of_xlate = ab8500_gpadc_of_xlate,
0942     .read_raw = ab8500_gpadc_read_raw,
0943 };
0944 
0945 static int ab8500_gpadc_runtime_suspend(struct device *dev)
0946 {
0947     struct iio_dev *indio_dev = dev_get_drvdata(dev);
0948     struct ab8500_gpadc *gpadc = iio_priv(indio_dev);
0949 
0950     regulator_disable(gpadc->vddadc);
0951 
0952     return 0;
0953 }
0954 
0955 static int ab8500_gpadc_runtime_resume(struct device *dev)
0956 {
0957     struct iio_dev *indio_dev = dev_get_drvdata(dev);
0958     struct ab8500_gpadc *gpadc = iio_priv(indio_dev);
0959     int ret;
0960 
0961     ret = regulator_enable(gpadc->vddadc);
0962     if (ret)
0963         dev_err(dev, "Failed to enable vddadc: %d\n", ret);
0964 
0965     return ret;
0966 }
0967 
0968 /**
0969  * ab8500_gpadc_parse_channel() - process devicetree channel configuration
0970  * @dev: pointer to containing device
0971  * @np: device tree node for the channel to configure
0972  * @ch: channel info to fill in
0973  * @iio_chan: IIO channel specification to fill in
0974  *
0975  * The devicetree will set up the channel for use with the specific device,
0976  * and define usage for things like AUX GPADC inputs more precisely.
0977  */
0978 static int ab8500_gpadc_parse_channel(struct device *dev,
0979                       struct device_node *np,
0980                       struct ab8500_gpadc_chan_info *ch,
0981                       struct iio_chan_spec *iio_chan)
0982 {
0983     const char *name = np->name;
0984     u32 chan;
0985     int ret;
0986 
0987     ret = of_property_read_u32(np, "reg", &chan);
0988     if (ret) {
0989         dev_err(dev, "invalid channel number %s\n", name);
0990         return ret;
0991     }
0992     if (chan > AB8500_GPADC_CHAN_BAT_TEMP_AND_IBAT) {
0993         dev_err(dev, "%s channel number out of range %d\n", name, chan);
0994         return -EINVAL;
0995     }
0996 
0997     iio_chan->channel = chan;
0998     iio_chan->datasheet_name = name;
0999     iio_chan->indexed = 1;
1000     iio_chan->address = chan;
1001     iio_chan->info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
1002         BIT(IIO_CHAN_INFO_PROCESSED);
1003     /* Most are voltages (also temperatures), some are currents */
1004     if ((chan == AB8500_GPADC_CHAN_MAIN_CHARGER_CURRENT) ||
1005         (chan == AB8500_GPADC_CHAN_USB_CHARGER_CURRENT))
1006         iio_chan->type = IIO_CURRENT;
1007     else
1008         iio_chan->type = IIO_VOLTAGE;
1009 
1010     ch->id = chan;
1011 
1012     /* Sensible defaults */
1013     ch->avg_sample = 16;
1014     ch->hardware_control = false;
1015     ch->falling_edge = false;
1016     ch->trig_timer = 0;
1017 
1018     return 0;
1019 }
1020 
1021 /**
1022  * ab8500_gpadc_parse_channels() - Parse the GPADC channels from DT
1023  * @gpadc: the GPADC to configure the channels for
1024  * @np: device tree node containing the channel configurations
1025  * @chans: the IIO channels we parsed
1026  * @nchans: the number of IIO channels we parsed
1027  */
1028 static int ab8500_gpadc_parse_channels(struct ab8500_gpadc *gpadc,
1029                        struct device_node *np,
1030                        struct iio_chan_spec **chans_parsed,
1031                        unsigned int *nchans_parsed)
1032 {
1033     struct device_node *child;
1034     struct ab8500_gpadc_chan_info *ch;
1035     struct iio_chan_spec *iio_chans;
1036     unsigned int nchans;
1037     int i;
1038 
1039     nchans = of_get_available_child_count(np);
1040     if (!nchans) {
1041         dev_err(gpadc->dev, "no channel children\n");
1042         return -ENODEV;
1043     }
1044     dev_info(gpadc->dev, "found %d ADC channels\n", nchans);
1045 
1046     iio_chans = devm_kcalloc(gpadc->dev, nchans,
1047                  sizeof(*iio_chans), GFP_KERNEL);
1048     if (!iio_chans)
1049         return -ENOMEM;
1050 
1051     gpadc->chans = devm_kcalloc(gpadc->dev, nchans,
1052                     sizeof(*gpadc->chans), GFP_KERNEL);
1053     if (!gpadc->chans)
1054         return -ENOMEM;
1055 
1056     i = 0;
1057     for_each_available_child_of_node(np, child) {
1058         struct iio_chan_spec *iio_chan;
1059         int ret;
1060 
1061         ch = &gpadc->chans[i];
1062         iio_chan = &iio_chans[i];
1063 
1064         ret = ab8500_gpadc_parse_channel(gpadc->dev, child, ch,
1065                          iio_chan);
1066         if (ret) {
1067             of_node_put(child);
1068             return ret;
1069         }
1070         i++;
1071     }
1072     gpadc->nchans = nchans;
1073     *chans_parsed = iio_chans;
1074     *nchans_parsed = nchans;
1075 
1076     return 0;
1077 }
1078 
1079 static int ab8500_gpadc_probe(struct platform_device *pdev)
1080 {
1081     struct ab8500_gpadc *gpadc;
1082     struct iio_dev *indio_dev;
1083     struct device *dev = &pdev->dev;
1084     struct device_node *np = pdev->dev.of_node;
1085     struct iio_chan_spec *iio_chans;
1086     unsigned int n_iio_chans;
1087     int ret;
1088 
1089     indio_dev = devm_iio_device_alloc(dev, sizeof(*gpadc));
1090     if (!indio_dev)
1091         return -ENOMEM;
1092 
1093     platform_set_drvdata(pdev, indio_dev);
1094     gpadc = iio_priv(indio_dev);
1095 
1096     gpadc->dev = dev;
1097     gpadc->ab8500 = dev_get_drvdata(dev->parent);
1098 
1099     ret = ab8500_gpadc_parse_channels(gpadc, np, &iio_chans, &n_iio_chans);
1100     if (ret)
1101         return ret;
1102 
1103     gpadc->irq_sw = platform_get_irq_byname(pdev, "SW_CONV_END");
1104     if (gpadc->irq_sw < 0)
1105         return dev_err_probe(dev, gpadc->irq_sw,
1106                      "failed to get platform sw_conv_end irq\n");
1107 
1108     if (is_ab8500(gpadc->ab8500)) {
1109         gpadc->irq_hw = platform_get_irq_byname(pdev, "HW_CONV_END");
1110         if (gpadc->irq_hw < 0)
1111             return dev_err_probe(dev, gpadc->irq_hw,
1112                          "failed to get platform hw_conv_end irq\n");
1113     } else {
1114         gpadc->irq_hw = 0;
1115     }
1116 
1117     /* Initialize completion used to notify completion of conversion */
1118     init_completion(&gpadc->complete);
1119 
1120     /* Request interrupts */
1121     ret = devm_request_threaded_irq(dev, gpadc->irq_sw, NULL,
1122         ab8500_bm_gpadcconvend_handler, IRQF_NO_SUSPEND | IRQF_ONESHOT,
1123         "ab8500-gpadc-sw", gpadc);
1124     if (ret < 0) {
1125         dev_err(dev,
1126             "failed to request sw conversion irq %d\n",
1127             gpadc->irq_sw);
1128         return ret;
1129     }
1130 
1131     if (gpadc->irq_hw) {
1132         ret = devm_request_threaded_irq(dev, gpadc->irq_hw, NULL,
1133             ab8500_bm_gpadcconvend_handler, IRQF_NO_SUSPEND | IRQF_ONESHOT,
1134             "ab8500-gpadc-hw", gpadc);
1135         if (ret < 0) {
1136             dev_err(dev,
1137                 "Failed to request hw conversion irq: %d\n",
1138                 gpadc->irq_hw);
1139             return ret;
1140         }
1141     }
1142 
1143     /* The VTVout LDO used to power the AB8500 GPADC */
1144     gpadc->vddadc = devm_regulator_get(dev, "vddadc");
1145     if (IS_ERR(gpadc->vddadc))
1146         return dev_err_probe(dev, PTR_ERR(gpadc->vddadc),
1147                      "failed to get vddadc\n");
1148 
1149     ret = regulator_enable(gpadc->vddadc);
1150     if (ret) {
1151         dev_err(dev, "failed to enable vddadc: %d\n", ret);
1152         return ret;
1153     }
1154 
1155     /* Enable runtime PM */
1156     pm_runtime_get_noresume(dev);
1157     pm_runtime_set_active(dev);
1158     pm_runtime_enable(dev);
1159     pm_runtime_set_autosuspend_delay(dev, AB8500_GPADC_AUTOSUSPEND_DELAY);
1160     pm_runtime_use_autosuspend(dev);
1161 
1162     ab8500_gpadc_read_calibration_data(gpadc);
1163 
1164     pm_runtime_put(dev);
1165 
1166     indio_dev->name = "ab8500-gpadc";
1167     indio_dev->modes = INDIO_DIRECT_MODE;
1168     indio_dev->info = &ab8500_gpadc_info;
1169     indio_dev->channels = iio_chans;
1170     indio_dev->num_channels = n_iio_chans;
1171 
1172     ret = devm_iio_device_register(dev, indio_dev);
1173     if (ret)
1174         goto out_dis_pm;
1175 
1176     return 0;
1177 
1178 out_dis_pm:
1179     pm_runtime_get_sync(dev);
1180     pm_runtime_put_noidle(dev);
1181     pm_runtime_disable(dev);
1182     regulator_disable(gpadc->vddadc);
1183 
1184     return ret;
1185 }
1186 
1187 static int ab8500_gpadc_remove(struct platform_device *pdev)
1188 {
1189     struct iio_dev *indio_dev = platform_get_drvdata(pdev);
1190     struct ab8500_gpadc *gpadc = iio_priv(indio_dev);
1191 
1192     pm_runtime_get_sync(gpadc->dev);
1193     pm_runtime_put_noidle(gpadc->dev);
1194     pm_runtime_disable(gpadc->dev);
1195     regulator_disable(gpadc->vddadc);
1196 
1197     return 0;
1198 }
1199 
1200 static DEFINE_RUNTIME_DEV_PM_OPS(ab8500_gpadc_pm_ops,
1201                  ab8500_gpadc_runtime_suspend,
1202                  ab8500_gpadc_runtime_resume, NULL);
1203 
1204 static struct platform_driver ab8500_gpadc_driver = {
1205     .probe = ab8500_gpadc_probe,
1206     .remove = ab8500_gpadc_remove,
1207     .driver = {
1208         .name = "ab8500-gpadc",
1209         .pm = pm_ptr(&ab8500_gpadc_pm_ops),
1210     },
1211 };
1212 builtin_platform_driver(ab8500_gpadc_driver);
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