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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Murata SCA3300 3-axis industrial accelerometer
0004  *
0005  * Copyright (c) 2021 Vaisala Oyj. All rights reserved.
0006  */
0007 
0008 #include <linux/bitops.h>
0009 #include <linux/crc8.h>
0010 #include <linux/delay.h>
0011 #include <linux/kernel.h>
0012 #include <linux/module.h>
0013 #include <linux/spi/spi.h>
0014 
0015 #include <asm/unaligned.h>
0016 
0017 #include <linux/iio/buffer.h>
0018 #include <linux/iio/iio.h>
0019 #include <linux/iio/sysfs.h>
0020 #include <linux/iio/trigger_consumer.h>
0021 #include <linux/iio/triggered_buffer.h>
0022 
0023 #define SCA3300_ALIAS "sca3300"
0024 
0025 #define SCA3300_CRC8_POLYNOMIAL 0x1d
0026 
0027 /* Device mode register */
0028 #define SCA3300_REG_MODE    0xd
0029 #define SCA3300_MODE_SW_RESET   0x20
0030 
0031 /* Last register in map */
0032 #define SCA3300_REG_SELBANK 0x1f
0033 
0034 /* Device status and mask */
0035 #define SCA3300_REG_STATUS  0x6
0036 #define SCA3300_STATUS_MASK GENMASK(8, 0)
0037 
0038 /* Device ID */
0039 #define SCA3300_REG_WHOAMI  0x10
0040 #define SCA3300_WHOAMI_ID   0x51
0041 #define SCL3300_WHOAMI_ID   0xC1
0042 
0043 /* Device return status and mask */
0044 #define SCA3300_VALUE_RS_ERROR  0x3
0045 #define SCA3300_MASK_RS_STATUS  GENMASK(1, 0)
0046 
0047 #define SCL3300_REG_ANG_CTRL 0x0C
0048 #define SCL3300_ANG_ENABLE   0x1F
0049 
0050 enum sca3300_scan_indexes {
0051     SCA3300_ACC_X = 0,
0052     SCA3300_ACC_Y,
0053     SCA3300_ACC_Z,
0054     SCA3300_TEMP,
0055     SCA3300_INCLI_X,
0056     SCA3300_INCLI_Y,
0057     SCA3300_INCLI_Z,
0058     SCA3300_SCAN_MAX
0059 };
0060 
0061 /*
0062  * Buffer size max case:
0063  * Three accel channels, two bytes per channel.
0064  * Temperature channel, two bytes.
0065  * Three incli channels, two bytes per channel.
0066  * Timestamp channel, eight bytes.
0067  */
0068 #define SCA3300_MAX_BUFFER_SIZE (ALIGN(sizeof(s16) * SCA3300_SCAN_MAX, sizeof(s64)) + sizeof(s64))
0069 
0070 #define SCA3300_ACCEL_CHANNEL(index, reg, axis) {           \
0071     .type = IIO_ACCEL,                      \
0072     .address = reg,                         \
0073     .modified = 1,                          \
0074     .channel2 = IIO_MOD_##axis,                 \
0075     .info_mask_separate = BIT(IIO_CHAN_INFO_RAW),           \
0076     .info_mask_shared_by_type =                 \
0077     BIT(IIO_CHAN_INFO_SCALE) |                  \
0078     BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY),       \
0079     .info_mask_shared_by_type_available =               \
0080     BIT(IIO_CHAN_INFO_SCALE) |                  \
0081     BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY),       \
0082     .scan_index = index,                        \
0083     .scan_type = {                          \
0084         .sign = 's',                        \
0085         .realbits = 16,                     \
0086         .storagebits = 16,                  \
0087         .endianness = IIO_CPU,                  \
0088     },                              \
0089 }
0090 
0091 #define SCA3300_INCLI_CHANNEL(index, reg, axis) {           \
0092     .type = IIO_INCLI,                      \
0093     .address = reg,                         \
0094     .modified = 1,                          \
0095     .channel2 = IIO_MOD_##axis,                 \
0096     .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),       \
0097     .info_mask_separate = BIT(IIO_CHAN_INFO_RAW),           \
0098     .info_mask_shared_by_type_available = BIT(IIO_CHAN_INFO_SCALE), \
0099     .scan_index = index,                        \
0100     .scan_type = {                          \
0101         .sign = 's',                        \
0102         .realbits = 16,                     \
0103         .storagebits = 16,                  \
0104         .endianness = IIO_CPU,                  \
0105     },                              \
0106 }
0107 
0108 #define SCA3300_TEMP_CHANNEL(index, reg) {              \
0109         .type = IIO_TEMP,                   \
0110         .address = reg,                     \
0111         .scan_index = index,                    \
0112         .info_mask_separate = BIT(IIO_CHAN_INFO_RAW),       \
0113         .scan_type = {                      \
0114             .sign = 's',                    \
0115             .realbits = 16,                 \
0116             .storagebits = 16,              \
0117             .endianness = IIO_CPU,              \
0118         },                          \
0119 }
0120 
0121 static const struct iio_chan_spec sca3300_channels[] = {
0122     SCA3300_ACCEL_CHANNEL(SCA3300_ACC_X, 0x1, X),
0123     SCA3300_ACCEL_CHANNEL(SCA3300_ACC_Y, 0x2, Y),
0124     SCA3300_ACCEL_CHANNEL(SCA3300_ACC_Z, 0x3, Z),
0125     SCA3300_TEMP_CHANNEL(SCA3300_TEMP, 0x05),
0126     IIO_CHAN_SOFT_TIMESTAMP(4),
0127 };
0128 
0129 static const int sca3300_lp_freq[] = {70, 10};
0130 static const int sca3300_lp_freq_map[] = {0, 0, 0, 1};
0131 
0132 static const int scl3300_lp_freq[] = {40, 70, 10};
0133 static const int scl3300_lp_freq_map[] = {0, 1, 2};
0134 
0135 static const int sca3300_accel_scale[][2] = {{0, 370}, {0, 741}, {0, 185}};
0136 static const int sca3300_accel_scale_map[] = {0, 1, 2, 2};
0137 
0138 static const int scl3300_accel_scale[][2] = {{0, 167}, {0, 333}, {0, 83}};
0139 static const int scl3300_accel_scale_map[] = {0, 1, 2};
0140 
0141 static const int scl3300_incli_scale[][2] = {{0, 5495}};
0142 static const int scl3300_incli_scale_map[] = {0, 0, 0};
0143 
0144 static const int sca3300_avail_modes_map[] = {0, 1, 2, 3};
0145 static const int scl3300_avail_modes_map[] = {0, 1, 3};
0146 
0147 static const struct iio_chan_spec scl3300_channels[] = {
0148     SCA3300_ACCEL_CHANNEL(SCA3300_ACC_X, 0x1, X),
0149     SCA3300_ACCEL_CHANNEL(SCA3300_ACC_Y, 0x2, Y),
0150     SCA3300_ACCEL_CHANNEL(SCA3300_ACC_Z, 0x3, Z),
0151     SCA3300_TEMP_CHANNEL(SCA3300_TEMP, 0x05),
0152     SCA3300_INCLI_CHANNEL(SCA3300_INCLI_X, 0x09, X),
0153     SCA3300_INCLI_CHANNEL(SCA3300_INCLI_Y, 0x0A, Y),
0154     SCA3300_INCLI_CHANNEL(SCA3300_INCLI_Z, 0x0B, Z),
0155     IIO_CHAN_SOFT_TIMESTAMP(7),
0156 };
0157 
0158 static const unsigned long sca3300_scan_masks[] = {
0159     BIT(SCA3300_ACC_X) | BIT(SCA3300_ACC_Y) | BIT(SCA3300_ACC_Z) |
0160     BIT(SCA3300_TEMP),
0161     0
0162 };
0163 
0164 static const unsigned long scl3300_scan_masks[] = {
0165     BIT(SCA3300_ACC_X) | BIT(SCA3300_ACC_Y) | BIT(SCA3300_ACC_Z) |
0166     BIT(SCA3300_TEMP) |
0167     BIT(SCA3300_INCLI_X) | BIT(SCA3300_INCLI_Y) | BIT(SCA3300_INCLI_Z),
0168     0
0169 };
0170 
0171 struct sca3300_chip_info {
0172     const char *name;
0173     const unsigned long *scan_masks;
0174     const struct iio_chan_spec *channels;
0175     u8 num_channels;
0176     u8 num_accel_scales;
0177     const int (*accel_scale)[2];
0178     const int *accel_scale_map;
0179     const int (*incli_scale)[2];
0180     const int *incli_scale_map;
0181     u8 num_incli_scales;
0182     u8 num_freqs;
0183     const int *freq_table;
0184     const int *freq_map;
0185     const int *avail_modes_table;
0186     u8 num_avail_modes;
0187     u8 chip_id;
0188     bool angle_supported;
0189 };
0190 
0191 /**
0192  * struct sca3300_data - device data
0193  * @spi: SPI device structure
0194  * @lock: Data buffer lock
0195  * @chip: Sensor chip specific information
0196  * @buffer: Triggered buffer:
0197  *          -SCA3300: 4 channel 16-bit data + 64-bit timestamp
0198  *          -SCL3300: 7 channel 16-bit data + 64-bit timestamp
0199  * @txbuf: Transmit buffer
0200  * @rxbuf: Receive buffer
0201  */
0202 struct sca3300_data {
0203     struct spi_device *spi;
0204     struct mutex lock;
0205     const struct sca3300_chip_info *chip;
0206     u8 buffer[SCA3300_MAX_BUFFER_SIZE] __aligned(sizeof(s64));
0207     u8 txbuf[4] __aligned(IIO_DMA_MINALIGN);
0208     u8 rxbuf[4];
0209 };
0210 
0211 static const struct sca3300_chip_info sca3300_chip_tbl[] = {
0212     {
0213         .name = "sca3300",
0214         .scan_masks = sca3300_scan_masks,
0215         .channels = sca3300_channels,
0216         .num_channels = ARRAY_SIZE(sca3300_channels),
0217         .num_accel_scales = ARRAY_SIZE(sca3300_accel_scale)*2,
0218         .accel_scale = sca3300_accel_scale,
0219         .accel_scale_map = sca3300_accel_scale_map,
0220         .num_freqs = ARRAY_SIZE(sca3300_lp_freq),
0221         .freq_table = sca3300_lp_freq,
0222         .freq_map = sca3300_lp_freq_map,
0223         .avail_modes_table = sca3300_avail_modes_map,
0224         .num_avail_modes = 4,
0225         .chip_id = SCA3300_WHOAMI_ID,
0226         .angle_supported = false,
0227     },
0228     {
0229         .name = "scl3300",
0230         .scan_masks = scl3300_scan_masks,
0231         .channels = scl3300_channels,
0232         .num_channels = ARRAY_SIZE(scl3300_channels),
0233         .num_accel_scales = ARRAY_SIZE(scl3300_accel_scale)*2,
0234         .accel_scale = scl3300_accel_scale,
0235         .accel_scale_map = scl3300_accel_scale_map,
0236         .incli_scale = scl3300_incli_scale,
0237         .incli_scale_map = scl3300_incli_scale_map,
0238         .num_incli_scales =  ARRAY_SIZE(scl3300_incli_scale)*2,
0239         .num_freqs = ARRAY_SIZE(scl3300_lp_freq),
0240         .freq_table = scl3300_lp_freq,
0241         .freq_map = scl3300_lp_freq_map,
0242         .avail_modes_table = scl3300_avail_modes_map,
0243         .num_avail_modes = 3,
0244         .chip_id = SCL3300_WHOAMI_ID,
0245         .angle_supported = true,
0246     },
0247 };
0248 
0249 DECLARE_CRC8_TABLE(sca3300_crc_table);
0250 
0251 static int sca3300_transfer(struct sca3300_data *sca_data, int *val)
0252 {
0253     /* Consecutive requests min. 10 us delay (Datasheet section 5.1.2) */
0254     struct spi_delay delay = { .value = 10, .unit = SPI_DELAY_UNIT_USECS };
0255     int32_t ret;
0256     int rs;
0257     u8 crc;
0258     struct spi_transfer xfers[2] = {
0259         {
0260             .tx_buf = sca_data->txbuf,
0261             .len = ARRAY_SIZE(sca_data->txbuf),
0262             .delay = delay,
0263             .cs_change = 1,
0264         },
0265         {
0266             .rx_buf = sca_data->rxbuf,
0267             .len = ARRAY_SIZE(sca_data->rxbuf),
0268             .delay = delay,
0269         }
0270     };
0271 
0272     /* inverted crc value as described in device data sheet */
0273     crc = ~crc8(sca3300_crc_table, &sca_data->txbuf[0], 3, CRC8_INIT_VALUE);
0274     sca_data->txbuf[3] = crc;
0275 
0276     ret = spi_sync_transfer(sca_data->spi, xfers, ARRAY_SIZE(xfers));
0277     if (ret) {
0278         dev_err(&sca_data->spi->dev,
0279             "transfer error, error: %d\n", ret);
0280         return -EIO;
0281     }
0282 
0283     crc = ~crc8(sca3300_crc_table, &sca_data->rxbuf[0], 3, CRC8_INIT_VALUE);
0284     if (sca_data->rxbuf[3] != crc) {
0285         dev_err(&sca_data->spi->dev, "CRC checksum mismatch");
0286         return -EIO;
0287     }
0288 
0289     /* get return status */
0290     rs = sca_data->rxbuf[0] & SCA3300_MASK_RS_STATUS;
0291     if (rs == SCA3300_VALUE_RS_ERROR)
0292         ret = -EINVAL;
0293 
0294     *val = sign_extend32(get_unaligned_be16(&sca_data->rxbuf[1]), 15);
0295 
0296     return ret;
0297 }
0298 
0299 static int sca3300_error_handler(struct sca3300_data *sca_data)
0300 {
0301     int ret;
0302     int val;
0303 
0304     mutex_lock(&sca_data->lock);
0305     sca_data->txbuf[0] = SCA3300_REG_STATUS << 2;
0306     ret = sca3300_transfer(sca_data, &val);
0307     mutex_unlock(&sca_data->lock);
0308     /*
0309      * Return status error is cleared after reading status register once,
0310      * expect EINVAL here.
0311      */
0312     if (ret != -EINVAL) {
0313         dev_err(&sca_data->spi->dev,
0314             "error reading device status: %d\n", ret);
0315         return ret;
0316     }
0317 
0318     dev_err(&sca_data->spi->dev, "device status: 0x%lx\n",
0319         val & SCA3300_STATUS_MASK);
0320 
0321     return 0;
0322 }
0323 
0324 static int sca3300_read_reg(struct sca3300_data *sca_data, u8 reg, int *val)
0325 {
0326     int ret;
0327 
0328     mutex_lock(&sca_data->lock);
0329     sca_data->txbuf[0] = reg << 2;
0330     ret = sca3300_transfer(sca_data, val);
0331     mutex_unlock(&sca_data->lock);
0332     if (ret != -EINVAL)
0333         return ret;
0334 
0335     return sca3300_error_handler(sca_data);
0336 }
0337 
0338 static int sca3300_write_reg(struct sca3300_data *sca_data, u8 reg, int val)
0339 {
0340     int reg_val = 0;
0341     int ret;
0342 
0343     mutex_lock(&sca_data->lock);
0344     /* BIT(7) for write operation */
0345     sca_data->txbuf[0] = BIT(7) | (reg << 2);
0346     put_unaligned_be16(val, &sca_data->txbuf[1]);
0347     ret = sca3300_transfer(sca_data, &reg_val);
0348     mutex_unlock(&sca_data->lock);
0349     if (ret != -EINVAL)
0350         return ret;
0351 
0352     return sca3300_error_handler(sca_data);
0353 }
0354 
0355 static int sca3300_set_op_mode(struct sca3300_data *sca_data, int index)
0356 {
0357     if ((index < 0) || (index >= sca_data->chip->num_avail_modes))
0358         return -EINVAL;
0359 
0360     return sca3300_write_reg(sca_data, SCA3300_REG_MODE,
0361                  sca_data->chip->avail_modes_table[index]);
0362 }
0363 
0364 static int sca3300_get_op_mode(struct sca3300_data *sca_data, int *index)
0365 {
0366     int reg_val;
0367     int ret;
0368     int i;
0369 
0370     ret = sca3300_read_reg(sca_data, SCA3300_REG_MODE, &reg_val);
0371     if (ret)
0372         return ret;
0373 
0374     for (i = 0; i < sca_data->chip->num_avail_modes; i++) {
0375         if (sca_data->chip->avail_modes_table[i] == reg_val)
0376             break;
0377     }
0378     if (i == sca_data->chip->num_avail_modes)
0379         return -EINVAL;
0380 
0381     *index = i;
0382     return 0;
0383 }
0384 
0385 static int sca3300_set_frequency(struct sca3300_data *data, int val)
0386 {
0387     const struct sca3300_chip_info *chip = data->chip;
0388     unsigned int index;
0389     int *opmode_scale;
0390     int *new_scale;
0391     unsigned int i;
0392 
0393     if (sca3300_get_op_mode(data, &index))
0394         return -EINVAL;
0395 
0396     /*
0397      * Find a mode in which the requested sampling frequency is available
0398      * and the scaling currently set is retained.
0399      */
0400     opmode_scale = (int *)chip->accel_scale[chip->accel_scale_map[index]];
0401     for (i = 0; i < chip->num_avail_modes; i++) {
0402         new_scale = (int *)chip->accel_scale[chip->accel_scale_map[i]];
0403         if ((val == chip->freq_table[chip->freq_map[i]]) &&
0404             (opmode_scale[1] == new_scale[1]) &&
0405             (opmode_scale[0] == new_scale[0]))
0406             break;
0407     }
0408     if (i == chip->num_avail_modes)
0409         return -EINVAL;
0410 
0411     return sca3300_set_op_mode(data, i);
0412 }
0413 
0414 static int sca3300_write_raw(struct iio_dev *indio_dev,
0415                  struct iio_chan_spec const *chan,
0416                  int val, int val2, long mask)
0417 {
0418     struct sca3300_data *data = iio_priv(indio_dev);
0419     int index;
0420     int i;
0421 
0422     switch (mask) {
0423     case IIO_CHAN_INFO_SCALE:
0424         if (chan->type != IIO_ACCEL)
0425             return -EINVAL;
0426         /*
0427          * Letting scale take priority over sampling frequency.
0428          * That makes sense given we can only ever end up increasing
0429          * the sampling frequency which is unlikely to be a problem.
0430          */
0431         for (i = 0; i < data->chip->num_avail_modes; i++) {
0432             index = data->chip->accel_scale_map[i];
0433             if ((val  == data->chip->accel_scale[index][0]) &&
0434                 (val2 == data->chip->accel_scale[index][1]))
0435                 return sca3300_set_op_mode(data, i);
0436         }
0437         return -EINVAL;
0438     case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
0439         return sca3300_set_frequency(data, val);
0440     default:
0441         return -EINVAL;
0442     }
0443 }
0444 
0445 static int sca3300_read_raw(struct iio_dev *indio_dev,
0446                 struct iio_chan_spec const *chan,
0447                 int *val, int *val2, long mask)
0448 {
0449     struct sca3300_data *data = iio_priv(indio_dev);
0450     int index;
0451     int ret;
0452 
0453     switch (mask) {
0454     case IIO_CHAN_INFO_RAW:
0455         ret = sca3300_read_reg(data, chan->address, val);
0456         if (ret)
0457             return ret;
0458         return IIO_VAL_INT;
0459     case IIO_CHAN_INFO_SCALE:
0460         ret = sca3300_get_op_mode(data, &index);
0461         if (ret)
0462             return ret;
0463         switch (chan->type) {
0464         case IIO_INCLI:
0465             index = data->chip->incli_scale_map[index];
0466             *val  = data->chip->incli_scale[index][0];
0467             *val2 = data->chip->incli_scale[index][1];
0468             return IIO_VAL_INT_PLUS_MICRO;
0469         case IIO_ACCEL:
0470             index = data->chip->accel_scale_map[index];
0471             *val  = data->chip->accel_scale[index][0];
0472             *val2 = data->chip->accel_scale[index][1];
0473             return IIO_VAL_INT_PLUS_MICRO;
0474         default:
0475             return -EINVAL;
0476         }
0477     case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
0478         ret = sca3300_get_op_mode(data, &index);
0479         if (ret)
0480             return ret;
0481         index = data->chip->freq_map[index];
0482         *val = data->chip->freq_table[index];
0483         return IIO_VAL_INT;
0484     default:
0485         return -EINVAL;
0486     }
0487 }
0488 
0489 static irqreturn_t sca3300_trigger_handler(int irq, void *p)
0490 {
0491     struct iio_poll_func *pf = p;
0492     struct iio_dev *indio_dev = pf->indio_dev;
0493     struct sca3300_data *data = iio_priv(indio_dev);
0494     int bit, ret, val, i = 0;
0495     s16 *channels = (s16 *)data->buffer;
0496 
0497     for_each_set_bit(bit, indio_dev->active_scan_mask,
0498              indio_dev->masklength) {
0499         ret = sca3300_read_reg(data, indio_dev->channels[bit].address, &val);
0500         if (ret) {
0501             dev_err_ratelimited(&data->spi->dev,
0502                 "failed to read register, error: %d\n", ret);
0503             /* handled, but bailing out due to errors */
0504             goto out;
0505         }
0506         channels[i++] = val;
0507     }
0508 
0509     iio_push_to_buffers_with_timestamp(indio_dev, data->buffer,
0510                        iio_get_time_ns(indio_dev));
0511 out:
0512     iio_trigger_notify_done(indio_dev->trig);
0513 
0514     return IRQ_HANDLED;
0515 }
0516 
0517 /*
0518  * sca3300_init - Device init sequence. See datasheet rev 2 section
0519  * 4.2 Start-Up Sequence for details.
0520  */
0521 static int sca3300_init(struct sca3300_data *sca_data,
0522             struct iio_dev *indio_dev)
0523 {
0524     int value = 0;
0525     int ret;
0526     int i;
0527 
0528     ret = sca3300_write_reg(sca_data, SCA3300_REG_MODE,
0529                 SCA3300_MODE_SW_RESET);
0530     if (ret)
0531         return ret;
0532 
0533     /*
0534      * Wait 1ms after SW-reset command.
0535      * Wait for the settling of signal paths,
0536      * 15ms for SCA3300 and 25ms for SCL3300,
0537      */
0538     usleep_range(26e3, 50e3);
0539 
0540     ret = sca3300_read_reg(sca_data, SCA3300_REG_WHOAMI, &value);
0541     if (ret)
0542         return ret;
0543 
0544     for (i = 0; i < ARRAY_SIZE(sca3300_chip_tbl); i++) {
0545         if (sca3300_chip_tbl[i].chip_id == value)
0546             break;
0547     }
0548     if (i == ARRAY_SIZE(sca3300_chip_tbl)) {
0549         dev_err(&sca_data->spi->dev, "unknown chip id %x\n", value);
0550         return -ENODEV;
0551     }
0552 
0553     sca_data->chip = &sca3300_chip_tbl[i];
0554 
0555     if (sca_data->chip->angle_supported) {
0556         ret = sca3300_write_reg(sca_data, SCL3300_REG_ANG_CTRL,
0557                     SCL3300_ANG_ENABLE);
0558         if (ret)
0559             return ret;
0560     }
0561 
0562     return 0;
0563 }
0564 
0565 static int sca3300_debugfs_reg_access(struct iio_dev *indio_dev,
0566                       unsigned int reg, unsigned int writeval,
0567                       unsigned int *readval)
0568 {
0569     struct sca3300_data *data = iio_priv(indio_dev);
0570     int value;
0571     int ret;
0572 
0573     if (reg > SCA3300_REG_SELBANK)
0574         return -EINVAL;
0575 
0576     if (!readval)
0577         return sca3300_write_reg(data, reg, writeval);
0578 
0579     ret = sca3300_read_reg(data, reg, &value);
0580     if (ret)
0581         return ret;
0582 
0583     *readval = value;
0584 
0585     return 0;
0586 }
0587 
0588 static int sca3300_read_avail(struct iio_dev *indio_dev,
0589                   struct iio_chan_spec const *chan,
0590                   const int **vals, int *type, int *length,
0591                   long mask)
0592 {
0593     struct sca3300_data *data = iio_priv(indio_dev);
0594     switch (mask) {
0595     case IIO_CHAN_INFO_SCALE:
0596         switch (chan->type) {
0597         case IIO_INCLI:
0598             *vals = (const int *)data->chip->incli_scale;
0599             *length = data->chip->num_incli_scales;
0600             *type = IIO_VAL_INT_PLUS_MICRO;
0601             return IIO_AVAIL_LIST;
0602         case IIO_ACCEL:
0603             *vals = (const int *)data->chip->accel_scale;
0604             *length = data->chip->num_accel_scales;
0605             *type = IIO_VAL_INT_PLUS_MICRO;
0606             return IIO_AVAIL_LIST;
0607         default:
0608             return -EINVAL;
0609         }
0610     case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
0611         *vals = (const int *)data->chip->freq_table;
0612         *length = data->chip->num_freqs;
0613         *type = IIO_VAL_INT;
0614         return IIO_AVAIL_LIST;
0615     default:
0616         return -EINVAL;
0617     }
0618 }
0619 
0620 static const struct iio_info sca3300_info = {
0621     .read_raw = sca3300_read_raw,
0622     .write_raw = sca3300_write_raw,
0623     .debugfs_reg_access = &sca3300_debugfs_reg_access,
0624     .read_avail = sca3300_read_avail,
0625 };
0626 
0627 static int sca3300_probe(struct spi_device *spi)
0628 {
0629     struct sca3300_data *sca_data;
0630     struct iio_dev *indio_dev;
0631     int ret;
0632 
0633     indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*sca_data));
0634     if (!indio_dev)
0635         return -ENOMEM;
0636 
0637     sca_data = iio_priv(indio_dev);
0638     mutex_init(&sca_data->lock);
0639     sca_data->spi = spi;
0640 
0641     crc8_populate_msb(sca3300_crc_table, SCA3300_CRC8_POLYNOMIAL);
0642 
0643     indio_dev->info = &sca3300_info;
0644 
0645     ret = sca3300_init(sca_data, indio_dev);
0646     if (ret) {
0647         dev_err(&spi->dev, "failed to init device, error: %d\n", ret);
0648         return ret;
0649     }
0650 
0651     indio_dev->name = sca_data->chip->name;
0652     indio_dev->modes = INDIO_DIRECT_MODE;
0653     indio_dev->channels = sca_data->chip->channels;
0654     indio_dev->num_channels = sca_data->chip->num_channels;
0655     indio_dev->available_scan_masks = sca_data->chip->scan_masks;
0656 
0657     ret = devm_iio_triggered_buffer_setup(&spi->dev, indio_dev,
0658                           iio_pollfunc_store_time,
0659                           sca3300_trigger_handler, NULL);
0660     if (ret) {
0661         dev_err(&spi->dev,
0662             "iio triggered buffer setup failed, error: %d\n", ret);
0663         return ret;
0664     }
0665 
0666     ret = devm_iio_device_register(&spi->dev, indio_dev);
0667     if (ret) {
0668         dev_err(&spi->dev, "iio device register failed, error: %d\n",
0669             ret);
0670     }
0671 
0672     return ret;
0673 }
0674 
0675 static const struct of_device_id sca3300_dt_ids[] = {
0676     { .compatible = "murata,sca3300"},
0677     { .compatible = "murata,scl3300"},
0678     {}
0679 };
0680 MODULE_DEVICE_TABLE(of, sca3300_dt_ids);
0681 
0682 static struct spi_driver sca3300_driver = {
0683     .driver = {
0684         .name       = SCA3300_ALIAS,
0685         .of_match_table = sca3300_dt_ids,
0686     },
0687     .probe  = sca3300_probe,
0688 };
0689 module_spi_driver(sca3300_driver);
0690 
0691 MODULE_AUTHOR("Tomas Melin <tomas.melin@vaisala.com>");
0692 MODULE_DESCRIPTION("Murata SCA3300 SPI Accelerometer");
0693 MODULE_LICENSE("GPL v2");
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