iio/accel/mxc4005.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * 3-axis accelerometer driver for MXC4005XC Memsic sensor
0004  *
0005  * Copyright (c) 2014, Intel Corporation.
0006  */
0007
0008 #include <linux/module.h>
0009 #include <linux/i2c.h>
0010 #include <linux/iio/iio.h>
0011 #include <linux/acpi.h>
0012 #include <linux/regmap.h>
0013 #include <linux/iio/sysfs.h>
0014 #include <linux/iio/trigger.h>
0015 #include <linux/iio/buffer.h>
0016 #include <linux/iio/triggered_buffer.h>
0017 #include <linux/iio/trigger_consumer.h>
0018
0019 #define MXC4005_DRV_NAME        "mxc4005"
0020 #define MXC4005_IRQ_NAME        "mxc4005_event"
0021 #define MXC4005_REGMAP_NAME     "mxc4005_regmap"
0022
0023 #define MXC4005_REG_XOUT_UPPER      0x03
0024 #define MXC4005_REG_XOUT_LOWER      0x04
0025 #define MXC4005_REG_YOUT_UPPER      0x05
0026 #define MXC4005_REG_YOUT_LOWER      0x06
0027 #define MXC4005_REG_ZOUT_UPPER      0x07
0028 #define MXC4005_REG_ZOUT_LOWER      0x08
0029
0030 #define MXC4005_REG_INT_MASK1       0x0B
0031 #define MXC4005_REG_INT_MASK1_BIT_DRDYE 0x01
0032
0033 #define MXC4005_REG_INT_CLR1        0x01
0034 #define MXC4005_REG_INT_CLR1_BIT_DRDYC  0x01
0035
0036 #define MXC4005_REG_CONTROL     0x0D
0037 #define MXC4005_REG_CONTROL_MASK_FSR    GENMASK(6, 5)
0038 #define MXC4005_CONTROL_FSR_SHIFT   5
0039
0040 #define MXC4005_REG_DEVICE_ID       0x0E
0041
0042 enum mxc4005_axis {
0043     AXIS_X,
0044     AXIS_Y,
0045     AXIS_Z,
0046 };
0047
0048 enum mxc4005_range {
0049     MXC4005_RANGE_2G,
0050     MXC4005_RANGE_4G,
0051     MXC4005_RANGE_8G,
0052 };
0053
0054 struct mxc4005_data {
0055     struct device *dev;
0056     struct mutex mutex;
0057     struct regmap *regmap;
0058     struct iio_trigger *dready_trig;
0059     /* Ensure timestamp is naturally aligned */
0060     struct {
0061         __be16 chans[3];
0062         s64 timestamp __aligned(8);
0063     } scan;
0064     bool trigger_enabled;
0065 };
0066
0067 /*
0068  * MXC4005 can operate in the following ranges:
0069  * +/- 2G, 4G, 8G (the default +/-2G)
0070  *
0071  * (2 + 2) * 9.81 / (2^12 - 1) = 0.009582
0072  * (4 + 4) * 9.81 / (2^12 - 1) = 0.019164
0073  * (8 + 8) * 9.81 / (2^12 - 1) = 0.038329
0074  */
0075 static const struct {
0076     u8 range;
0077     int scale;
0078 } mxc4005_scale_table[] = {
0079     {MXC4005_RANGE_2G, 9582},
0080     {MXC4005_RANGE_4G, 19164},
0081     {MXC4005_RANGE_8G, 38329},
0082 };
0083
0084
0085 static IIO_CONST_ATTR(in_accel_scale_available, "0.009582 0.019164 0.038329");
0086
0087 static struct attribute *mxc4005_attributes[] = {
0088     &iio_const_attr_in_accel_scale_available.dev_attr.attr,
0089     NULL,
0090 };
0091
0092 static const struct attribute_group mxc4005_attrs_group = {
0093     .attrs = mxc4005_attributes,
0094 };
0095
0096 static bool mxc4005_is_readable_reg(struct device *dev, unsigned int reg)
0097 {
0098     switch (reg) {
0099     case MXC4005_REG_XOUT_UPPER:
0100     case MXC4005_REG_XOUT_LOWER:
0101     case MXC4005_REG_YOUT_UPPER:
0102     case MXC4005_REG_YOUT_LOWER:
0103     case MXC4005_REG_ZOUT_UPPER:
0104     case MXC4005_REG_ZOUT_LOWER:
0105     case MXC4005_REG_DEVICE_ID:
0106     case MXC4005_REG_CONTROL:
0107         return true;
0108     default:
0109         return false;
0110     }
0111 }
0112
0113 static bool mxc4005_is_writeable_reg(struct device *dev, unsigned int reg)
0114 {
0115     switch (reg) {
0116     case MXC4005_REG_INT_CLR1:
0117     case MXC4005_REG_INT_MASK1:
0118     case MXC4005_REG_CONTROL:
0119         return true;
0120     default:
0121         return false;
0122     }
0123 }
0124
0125 static const struct regmap_config mxc4005_regmap_config = {
0126     .name = MXC4005_REGMAP_NAME,
0127
0128     .reg_bits = 8,
0129     .val_bits = 8,
0130
0131     .max_register = MXC4005_REG_DEVICE_ID,
0132
0133     .readable_reg = mxc4005_is_readable_reg,
0134     .writeable_reg = mxc4005_is_writeable_reg,
0135 };
0136
0137 static int mxc4005_read_xyz(struct mxc4005_data *data)
0138 {
0139     int ret;
0140
0141     ret = regmap_bulk_read(data->regmap, MXC4005_REG_XOUT_UPPER,
0142                    data->scan.chans, sizeof(data->scan.chans));
0143     if (ret < 0) {
0144         dev_err(data->dev, "failed to read axes\n");
0145         return ret;
0146     }
0147
0148     return 0;
0149 }
0150
0151 static int mxc4005_read_axis(struct mxc4005_data *data,
0152                  unsigned int addr)
0153 {
0154     __be16 reg;
0155     int ret;
0156
0157     ret = regmap_bulk_read(data->regmap, addr, &reg, sizeof(reg));
0158     if (ret < 0) {
0159         dev_err(data->dev, "failed to read reg %02x\n", addr);
0160         return ret;
0161     }
0162
0163     return be16_to_cpu(reg);
0164 }
0165
0166 static int mxc4005_read_scale(struct mxc4005_data *data)
0167 {
0168     unsigned int reg;
0169     int ret;
0170     int i;
0171
0172     ret = regmap_read(data->regmap, MXC4005_REG_CONTROL, &reg);
0173     if (ret < 0) {
0174         dev_err(data->dev, "failed to read reg_control\n");
0175         return ret;
0176     }
0177
0178     i = reg >> MXC4005_CONTROL_FSR_SHIFT;
0179
0180     if (i < 0 || i >= ARRAY_SIZE(mxc4005_scale_table))
0181         return -EINVAL;
0182
0183     return mxc4005_scale_table[i].scale;
0184 }
0185
0186 static int mxc4005_set_scale(struct mxc4005_data *data, int val)
0187 {
0188     unsigned int reg;
0189     int i;
0190     int ret;
0191
0192     for (i = 0; i < ARRAY_SIZE(mxc4005_scale_table); i++) {
0193         if (mxc4005_scale_table[i].scale == val) {
0194             reg = i << MXC4005_CONTROL_FSR_SHIFT;
0195             ret = regmap_update_bits(data->regmap,
0196                          MXC4005_REG_CONTROL,
0197                          MXC4005_REG_CONTROL_MASK_FSR,
0198                          reg);
0199             if (ret < 0)
0200                 dev_err(data->dev,
0201                     "failed to write reg_control\n");
0202             return ret;
0203         }
0204     }
0205
0206     return -EINVAL;
0207 }
0208
0209 static int mxc4005_read_raw(struct iio_dev *indio_dev,
0210                 struct iio_chan_spec const *chan,
0211                 int *val, int *val2, long mask)
0212 {
0213     struct mxc4005_data *data = iio_priv(indio_dev);
0214     int ret;
0215
0216     switch (mask) {
0217     case IIO_CHAN_INFO_RAW:
0218         switch (chan->type) {
0219         case IIO_ACCEL:
0220             if (iio_buffer_enabled(indio_dev))
0221                 return -EBUSY;
0222
0223             ret = mxc4005_read_axis(data, chan->address);
0224             if (ret < 0)
0225                 return ret;
0226             *val = sign_extend32(ret >> chan->scan_type.shift,
0227                          chan->scan_type.realbits - 1);
0228             return IIO_VAL_INT;
0229         default:
0230             return -EINVAL;
0231         }
0232     case IIO_CHAN_INFO_SCALE:
0233         ret = mxc4005_read_scale(data);
0234         if (ret < 0)
0235             return ret;
0236
0237         *val = 0;
0238         *val2 = ret;
0239         return IIO_VAL_INT_PLUS_MICRO;
0240     default:
0241         return -EINVAL;
0242     }
0243 }
0244
0245 static int mxc4005_write_raw(struct iio_dev *indio_dev,
0246                  struct iio_chan_spec const *chan,
0247                  int val, int val2, long mask)
0248 {
0249     struct mxc4005_data *data = iio_priv(indio_dev);
0250
0251     switch (mask) {
0252     case IIO_CHAN_INFO_SCALE:
0253         if (val != 0)
0254             return -EINVAL;
0255
0256         return mxc4005_set_scale(data, val2);
0257     default:
0258         return -EINVAL;
0259     }
0260 }
0261
0262 static const struct iio_info mxc4005_info = {
0263     .read_raw   = mxc4005_read_raw,
0264     .write_raw  = mxc4005_write_raw,
0265     .attrs      = &mxc4005_attrs_group,
0266 };
0267
0268 static const unsigned long mxc4005_scan_masks[] = {
0269     BIT(AXIS_X) | BIT(AXIS_Y) | BIT(AXIS_Z),
0270     0
0271 };
0272
0273 #define MXC4005_CHANNEL(_axis, _addr) {             \
0274     .type = IIO_ACCEL,                  \
0275     .modified = 1,                      \
0276     .channel2 = IIO_MOD_##_axis,                \
0277     .address = _addr,                   \
0278     .info_mask_separate = BIT(IIO_CHAN_INFO_RAW),       \
0279     .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),   \
0280     .scan_index = AXIS_##_axis,             \
0281     .scan_type = {                      \
0282         .sign = 's',                    \
0283         .realbits = 12,                 \
0284         .storagebits = 16,              \
0285         .shift = 4,                 \
0286         .endianness = IIO_BE,               \
0287     },                          \
0288 }
0289
0290 static const struct iio_chan_spec mxc4005_channels[] = {
0291     MXC4005_CHANNEL(X, MXC4005_REG_XOUT_UPPER),
0292     MXC4005_CHANNEL(Y, MXC4005_REG_YOUT_UPPER),
0293     MXC4005_CHANNEL(Z, MXC4005_REG_ZOUT_UPPER),
0294     IIO_CHAN_SOFT_TIMESTAMP(3),
0295 };
0296
0297 static irqreturn_t mxc4005_trigger_handler(int irq, void *private)
0298 {
0299     struct iio_poll_func *pf = private;
0300     struct iio_dev *indio_dev = pf->indio_dev;
0301     struct mxc4005_data *data = iio_priv(indio_dev);
0302     int ret;
0303
0304     ret = mxc4005_read_xyz(data);
0305     if (ret < 0)
0306         goto err;
0307
0308     iio_push_to_buffers_with_timestamp(indio_dev, &data->scan,
0309                        pf->timestamp);
0310
0311 err:
0312     iio_trigger_notify_done(indio_dev->trig);
0313
0314     return IRQ_HANDLED;
0315 }
0316
0317 static void mxc4005_clr_intr(struct mxc4005_data *data)
0318 {
0319     int ret;
0320
0321     /* clear interrupt */
0322     ret = regmap_write(data->regmap, MXC4005_REG_INT_CLR1,
0323                MXC4005_REG_INT_CLR1_BIT_DRDYC);
0324     if (ret < 0)
0325         dev_err(data->dev, "failed to write to reg_int_clr1\n");
0326 }
0327
0328 static int mxc4005_set_trigger_state(struct iio_trigger *trig,
0329                      bool state)
0330 {
0331     struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
0332     struct mxc4005_data *data = iio_priv(indio_dev);
0333     int ret;
0334
0335     mutex_lock(&data->mutex);
0336     if (state) {
0337         ret = regmap_write(data->regmap, MXC4005_REG_INT_MASK1,
0338                    MXC4005_REG_INT_MASK1_BIT_DRDYE);
0339     } else {
0340         ret = regmap_write(data->regmap, MXC4005_REG_INT_MASK1,
0341                    ~MXC4005_REG_INT_MASK1_BIT_DRDYE);
0342     }
0343
0344     if (ret < 0) {
0345         mutex_unlock(&data->mutex);
0346         dev_err(data->dev, "failed to update reg_int_mask1");
0347         return ret;
0348     }
0349
0350     data->trigger_enabled = state;
0351     mutex_unlock(&data->mutex);
0352
0353     return 0;
0354 }
0355
0356 static void mxc4005_trigger_reen(struct iio_trigger *trig)
0357 {
0358     struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
0359     struct mxc4005_data *data = iio_priv(indio_dev);
0360
0361     if (!data->dready_trig)
0362         return;
0363
0364     mxc4005_clr_intr(data);
0365 }
0366
0367 static const struct iio_trigger_ops mxc4005_trigger_ops = {
0368     .set_trigger_state = mxc4005_set_trigger_state,
0369     .reenable = mxc4005_trigger_reen,
0370 };
0371
0372 static int mxc4005_chip_init(struct mxc4005_data *data)
0373 {
0374     int ret;
0375     unsigned int reg;
0376
0377     ret = regmap_read(data->regmap, MXC4005_REG_DEVICE_ID, &reg);
0378     if (ret < 0) {
0379         dev_err(data->dev, "failed to read chip id\n");
0380         return ret;
0381     }
0382
0383     dev_dbg(data->dev, "MXC4005 chip id %02x\n", reg);
0384
0385     return 0;
0386 }
0387
0388 static int mxc4005_probe(struct i2c_client *client,
0389              const struct i2c_device_id *id)
0390 {
0391     struct mxc4005_data *data;
0392     struct iio_dev *indio_dev;
0393     struct regmap *regmap;
0394     int ret;
0395
0396     indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
0397     if (!indio_dev)
0398         return -ENOMEM;
0399
0400     regmap = devm_regmap_init_i2c(client, &mxc4005_regmap_config);
0401     if (IS_ERR(regmap)) {
0402         dev_err(&client->dev, "failed to initialize regmap\n");
0403         return PTR_ERR(regmap);
0404     }
0405
0406     data = iio_priv(indio_dev);
0407     i2c_set_clientdata(client, indio_dev);
0408     data->dev = &client->dev;
0409     data->regmap = regmap;
0410
0411     ret = mxc4005_chip_init(data);
0412     if (ret < 0) {
0413         dev_err(&client->dev, "failed to initialize chip\n");
0414         return ret;
0415     }
0416
0417     mutex_init(&data->mutex);
0418
0419     indio_dev->channels = mxc4005_channels;
0420     indio_dev->num_channels = ARRAY_SIZE(mxc4005_channels);
0421     indio_dev->available_scan_masks = mxc4005_scan_masks;
0422     indio_dev->name = MXC4005_DRV_NAME;
0423     indio_dev->modes = INDIO_DIRECT_MODE;
0424     indio_dev->info = &mxc4005_info;
0425
0426     ret = devm_iio_triggered_buffer_setup(&client->dev, indio_dev,
0427                      iio_pollfunc_store_time,
0428                      mxc4005_trigger_handler,
0429                      NULL);
0430     if (ret < 0) {
0431         dev_err(&client->dev,
0432             "failed to setup iio triggered buffer\n");
0433         return ret;
0434     }
0435
0436     if (client->irq > 0) {
0437         data->dready_trig = devm_iio_trigger_alloc(&client->dev,
0438                                "%s-dev%d",
0439                                indio_dev->name,
0440                                iio_device_id(indio_dev));
0441         if (!data->dready_trig)
0442             return -ENOMEM;
0443
0444         ret = devm_request_threaded_irq(&client->dev, client->irq,
0445                         iio_trigger_generic_data_rdy_poll,
0446                         NULL,
0447                         IRQF_TRIGGER_FALLING |
0448                         IRQF_ONESHOT,
0449                         MXC4005_IRQ_NAME,
0450                         data->dready_trig);
0451         if (ret) {
0452             dev_err(&client->dev,
0453                 "failed to init threaded irq\n");
0454             return ret;
0455         }
0456
0457         data->dready_trig->ops = &mxc4005_trigger_ops;
0458         iio_trigger_set_drvdata(data->dready_trig, indio_dev);
0459         ret = devm_iio_trigger_register(&client->dev,
0460                         data->dready_trig);
0461         if (ret) {
0462             dev_err(&client->dev,
0463                 "failed to register trigger\n");
0464             return ret;
0465         }
0466
0467         indio_dev->trig = iio_trigger_get(data->dready_trig);
0468     }
0469
0470     return devm_iio_device_register(&client->dev, indio_dev);
0471 }
0472
0473 static const struct acpi_device_id mxc4005_acpi_match[] = {
0474     {"MXC4005", 0},
0475     {"MXC6655", 0},
0476     { },
0477 };
0478 MODULE_DEVICE_TABLE(acpi, mxc4005_acpi_match);
0479
0480 static const struct i2c_device_id mxc4005_id[] = {
0481     {"mxc4005", 0},
0482     {"mxc6655", 0},
0483     { },
0484 };
0485 MODULE_DEVICE_TABLE(i2c, mxc4005_id);
0486
0487 static struct i2c_driver mxc4005_driver = {
0488     .driver = {
0489         .name = MXC4005_DRV_NAME,
0490         .acpi_match_table = ACPI_PTR(mxc4005_acpi_match),
0491     },
0492     .probe      = mxc4005_probe,
0493     .id_table   = mxc4005_id,
0494 };
0495
0496 module_i2c_driver(mxc4005_driver);
0497
0498 MODULE_AUTHOR("Teodora Baluta <teodora.baluta@intel.com>");
0499 MODULE_LICENSE("GPL v2");
0500 MODULE_DESCRIPTION("MXC4005 3-axis accelerometer driver");