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0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * mma8452.c - Support for following Freescale / NXP 3-axis accelerometers:
0004  *
0005  * device name  digital output  7-bit I2C slave address (pin selectable)
0006  * ---------------------------------------------------------------------
0007  * MMA8451Q 14 bit      0x1c / 0x1d
0008  * MMA8452Q 12 bit      0x1c / 0x1d
0009  * MMA8453Q 10 bit      0x1c / 0x1d
0010  * MMA8652FC    12 bit      0x1d
0011  * MMA8653FC    10 bit      0x1d
0012  * FXLS8471Q    14 bit      0x1e / 0x1d / 0x1c / 0x1f
0013  *
0014  * Copyright 2015 Martin Kepplinger <martink@posteo.de>
0015  * Copyright 2014 Peter Meerwald <pmeerw@pmeerw.net>
0016  *
0017  *
0018  * TODO: orientation events
0019  */
0020 
0021 #include <linux/module.h>
0022 #include <linux/i2c.h>
0023 #include <linux/iio/iio.h>
0024 #include <linux/iio/sysfs.h>
0025 #include <linux/iio/buffer.h>
0026 #include <linux/iio/trigger.h>
0027 #include <linux/iio/trigger_consumer.h>
0028 #include <linux/iio/triggered_buffer.h>
0029 #include <linux/iio/events.h>
0030 #include <linux/delay.h>
0031 #include <linux/of_device.h>
0032 #include <linux/of_irq.h>
0033 #include <linux/pm_runtime.h>
0034 #include <linux/regulator/consumer.h>
0035 
0036 #define MMA8452_STATUS              0x00
0037 #define  MMA8452_STATUS_DRDY            (BIT(2) | BIT(1) | BIT(0))
0038 #define MMA8452_OUT_X               0x01 /* MSB first */
0039 #define MMA8452_OUT_Y               0x03
0040 #define MMA8452_OUT_Z               0x05
0041 #define MMA8452_INT_SRC             0x0c
0042 #define MMA8452_WHO_AM_I            0x0d
0043 #define MMA8452_DATA_CFG            0x0e
0044 #define  MMA8452_DATA_CFG_FS_MASK       GENMASK(1, 0)
0045 #define  MMA8452_DATA_CFG_FS_2G         0
0046 #define  MMA8452_DATA_CFG_FS_4G         1
0047 #define  MMA8452_DATA_CFG_FS_8G         2
0048 #define  MMA8452_DATA_CFG_HPF_MASK      BIT(4)
0049 #define MMA8452_HP_FILTER_CUTOFF        0x0f
0050 #define  MMA8452_HP_FILTER_CUTOFF_SEL_MASK  GENMASK(1, 0)
0051 #define MMA8452_FF_MT_CFG           0x15
0052 #define  MMA8452_FF_MT_CFG_OAE          BIT(6)
0053 #define  MMA8452_FF_MT_CFG_ELE          BIT(7)
0054 #define MMA8452_FF_MT_SRC           0x16
0055 #define  MMA8452_FF_MT_SRC_XHE          BIT(1)
0056 #define  MMA8452_FF_MT_SRC_YHE          BIT(3)
0057 #define  MMA8452_FF_MT_SRC_ZHE          BIT(5)
0058 #define MMA8452_FF_MT_THS           0x17
0059 #define  MMA8452_FF_MT_THS_MASK         0x7f
0060 #define MMA8452_FF_MT_COUNT         0x18
0061 #define MMA8452_FF_MT_CHAN_SHIFT        3
0062 #define MMA8452_TRANSIENT_CFG           0x1d
0063 #define  MMA8452_TRANSIENT_CFG_CHAN(chan)   BIT(chan + 1)
0064 #define  MMA8452_TRANSIENT_CFG_HPF_BYP      BIT(0)
0065 #define  MMA8452_TRANSIENT_CFG_ELE      BIT(4)
0066 #define MMA8452_TRANSIENT_SRC           0x1e
0067 #define  MMA8452_TRANSIENT_SRC_XTRANSE      BIT(1)
0068 #define  MMA8452_TRANSIENT_SRC_YTRANSE      BIT(3)
0069 #define  MMA8452_TRANSIENT_SRC_ZTRANSE      BIT(5)
0070 #define MMA8452_TRANSIENT_THS           0x1f
0071 #define  MMA8452_TRANSIENT_THS_MASK     GENMASK(6, 0)
0072 #define MMA8452_TRANSIENT_COUNT         0x20
0073 #define MMA8452_TRANSIENT_CHAN_SHIFT        1
0074 #define MMA8452_CTRL_REG1           0x2a
0075 #define  MMA8452_CTRL_ACTIVE            BIT(0)
0076 #define  MMA8452_CTRL_DR_MASK           GENMASK(5, 3)
0077 #define  MMA8452_CTRL_DR_SHIFT          3
0078 #define  MMA8452_CTRL_DR_DEFAULT        0x4 /* 50 Hz sample frequency */
0079 #define MMA8452_CTRL_REG2           0x2b
0080 #define  MMA8452_CTRL_REG2_RST          BIT(6)
0081 #define  MMA8452_CTRL_REG2_MODS_SHIFT       3
0082 #define  MMA8452_CTRL_REG2_MODS_MASK        0x1b
0083 #define MMA8452_CTRL_REG4           0x2d
0084 #define MMA8452_CTRL_REG5           0x2e
0085 #define MMA8452_OFF_X               0x2f
0086 #define MMA8452_OFF_Y               0x30
0087 #define MMA8452_OFF_Z               0x31
0088 
0089 #define MMA8452_MAX_REG             0x31
0090 
0091 #define  MMA8452_INT_DRDY           BIT(0)
0092 #define  MMA8452_INT_FF_MT          BIT(2)
0093 #define  MMA8452_INT_TRANS          BIT(5)
0094 
0095 #define MMA8451_DEVICE_ID           0x1a
0096 #define MMA8452_DEVICE_ID           0x2a
0097 #define MMA8453_DEVICE_ID           0x3a
0098 #define MMA8652_DEVICE_ID           0x4a
0099 #define MMA8653_DEVICE_ID           0x5a
0100 #define FXLS8471_DEVICE_ID          0x6a
0101 
0102 #define MMA8452_AUTO_SUSPEND_DELAY_MS       2000
0103 
0104 struct mma8452_data {
0105     struct i2c_client *client;
0106     struct mutex lock;
0107     struct iio_mount_matrix orientation;
0108     u8 ctrl_reg1;
0109     u8 data_cfg;
0110     const struct mma_chip_info *chip_info;
0111     int sleep_val;
0112     struct regulator *vdd_reg;
0113     struct regulator *vddio_reg;
0114 
0115     /* Ensure correct alignment of time stamp when present */
0116     struct {
0117         __be16 channels[3];
0118         s64 ts __aligned(8);
0119     } buffer;
0120 };
0121 
0122  /**
0123   * struct mma8452_event_regs - chip specific data related to events
0124   * @ev_cfg:            event config register address
0125   * @ev_cfg_ele:            latch bit in event config register
0126   * @ev_cfg_chan_shift:     number of the bit to enable events in X
0127   *             direction; in event config register
0128   * @ev_src:            event source register address
0129   * @ev_ths:            event threshold register address
0130   * @ev_ths_mask:       mask for the threshold value
0131   * @ev_count:          event count (period) register address
0132   *
0133   * Since not all chips supported by the driver support comparing high pass
0134   * filtered data for events (interrupts), different interrupt sources are
0135   * used for different chips and the relevant registers are included here.
0136   */
0137 struct mma8452_event_regs {
0138     u8 ev_cfg;
0139     u8 ev_cfg_ele;
0140     u8 ev_cfg_chan_shift;
0141     u8 ev_src;
0142     u8 ev_ths;
0143     u8 ev_ths_mask;
0144     u8 ev_count;
0145 };
0146 
0147 static const struct mma8452_event_regs ff_mt_ev_regs = {
0148     .ev_cfg = MMA8452_FF_MT_CFG,
0149     .ev_cfg_ele = MMA8452_FF_MT_CFG_ELE,
0150     .ev_cfg_chan_shift = MMA8452_FF_MT_CHAN_SHIFT,
0151     .ev_src = MMA8452_FF_MT_SRC,
0152     .ev_ths = MMA8452_FF_MT_THS,
0153     .ev_ths_mask = MMA8452_FF_MT_THS_MASK,
0154     .ev_count = MMA8452_FF_MT_COUNT
0155 };
0156 
0157 static const struct mma8452_event_regs trans_ev_regs = {
0158     .ev_cfg = MMA8452_TRANSIENT_CFG,
0159     .ev_cfg_ele = MMA8452_TRANSIENT_CFG_ELE,
0160     .ev_cfg_chan_shift = MMA8452_TRANSIENT_CHAN_SHIFT,
0161     .ev_src = MMA8452_TRANSIENT_SRC,
0162     .ev_ths = MMA8452_TRANSIENT_THS,
0163     .ev_ths_mask = MMA8452_TRANSIENT_THS_MASK,
0164     .ev_count = MMA8452_TRANSIENT_COUNT,
0165 };
0166 
0167 /**
0168  * struct mma_chip_info - chip specific data
0169  * @name:           part number of device reported via 'name' attr
0170  * @chip_id:            WHO_AM_I register's value
0171  * @channels:           struct iio_chan_spec matching the device's
0172  *              capabilities
0173  * @num_channels:       number of channels
0174  * @mma_scales:         scale factors for converting register values
0175  *              to m/s^2; 3 modes: 2g, 4g, 8g; 2 integers
0176  *              per mode: m/s^2 and micro m/s^2
0177  * @all_events:         all events supported by this chip
0178  * @enabled_events:     event flags enabled and handled by this driver
0179  */
0180 struct mma_chip_info {
0181     const char *name;
0182     u8 chip_id;
0183     const struct iio_chan_spec *channels;
0184     int num_channels;
0185     const int mma_scales[3][2];
0186     int all_events;
0187     int enabled_events;
0188 };
0189 
0190 enum {
0191     idx_x,
0192     idx_y,
0193     idx_z,
0194     idx_ts,
0195 };
0196 
0197 static int mma8452_drdy(struct mma8452_data *data)
0198 {
0199     int tries = 150;
0200 
0201     while (tries-- > 0) {
0202         int ret = i2c_smbus_read_byte_data(data->client,
0203             MMA8452_STATUS);
0204         if (ret < 0)
0205             return ret;
0206         if ((ret & MMA8452_STATUS_DRDY) == MMA8452_STATUS_DRDY)
0207             return 0;
0208 
0209         if (data->sleep_val <= 20)
0210             usleep_range(data->sleep_val * 250,
0211                      data->sleep_val * 500);
0212         else
0213             msleep(20);
0214     }
0215 
0216     dev_err(&data->client->dev, "data not ready\n");
0217 
0218     return -EIO;
0219 }
0220 
0221 static int mma8452_set_runtime_pm_state(struct i2c_client *client, bool on)
0222 {
0223 #ifdef CONFIG_PM
0224     int ret;
0225 
0226     if (on) {
0227         ret = pm_runtime_resume_and_get(&client->dev);
0228     } else {
0229         pm_runtime_mark_last_busy(&client->dev);
0230         ret = pm_runtime_put_autosuspend(&client->dev);
0231     }
0232 
0233     if (ret < 0) {
0234         dev_err(&client->dev,
0235             "failed to change power state to %d\n", on);
0236 
0237         return ret;
0238     }
0239 #endif
0240 
0241     return 0;
0242 }
0243 
0244 static int mma8452_read(struct mma8452_data *data, __be16 buf[3])
0245 {
0246     int ret = mma8452_drdy(data);
0247 
0248     if (ret < 0)
0249         return ret;
0250 
0251     ret = mma8452_set_runtime_pm_state(data->client, true);
0252     if (ret)
0253         return ret;
0254 
0255     ret = i2c_smbus_read_i2c_block_data(data->client, MMA8452_OUT_X,
0256                         3 * sizeof(__be16), (u8 *)buf);
0257 
0258     ret = mma8452_set_runtime_pm_state(data->client, false);
0259 
0260     return ret;
0261 }
0262 
0263 static ssize_t mma8452_show_int_plus_micros(char *buf, const int (*vals)[2],
0264                         int n)
0265 {
0266     size_t len = 0;
0267 
0268     while (n-- > 0)
0269         len += scnprintf(buf + len, PAGE_SIZE - len, "%d.%06d ",
0270                  vals[n][0], vals[n][1]);
0271 
0272     /* replace trailing space by newline */
0273     buf[len - 1] = '\n';
0274 
0275     return len;
0276 }
0277 
0278 static int mma8452_get_int_plus_micros_index(const int (*vals)[2], int n,
0279                          int val, int val2)
0280 {
0281     while (n-- > 0)
0282         if (val == vals[n][0] && val2 == vals[n][1])
0283             return n;
0284 
0285     return -EINVAL;
0286 }
0287 
0288 static unsigned int mma8452_get_odr_index(struct mma8452_data *data)
0289 {
0290     return (data->ctrl_reg1 & MMA8452_CTRL_DR_MASK) >>
0291             MMA8452_CTRL_DR_SHIFT;
0292 }
0293 
0294 static const int mma8452_samp_freq[8][2] = {
0295     {800, 0}, {400, 0}, {200, 0}, {100, 0}, {50, 0}, {12, 500000},
0296     {6, 250000}, {1, 560000}
0297 };
0298 
0299 /* Datasheet table: step time "Relationship with the ODR" (sample frequency) */
0300 static const unsigned int mma8452_time_step_us[4][8] = {
0301     { 1250, 2500, 5000, 10000, 20000, 20000, 20000, 20000 },  /* normal */
0302     { 1250, 2500, 5000, 10000, 20000, 80000, 80000, 80000 },  /* l p l n */
0303     { 1250, 2500, 2500, 2500, 2500, 2500, 2500, 2500 },   /* high res*/
0304     { 1250, 2500, 5000, 10000, 20000, 80000, 160000, 160000 } /* l p */
0305 };
0306 
0307 /* Datasheet table "High-Pass Filter Cutoff Options" */
0308 static const int mma8452_hp_filter_cutoff[4][8][4][2] = {
0309     { /* normal */
0310     { {16, 0}, {8, 0}, {4, 0}, {2, 0} },        /* 800 Hz sample */
0311     { {16, 0}, {8, 0}, {4, 0}, {2, 0} },        /* 400 Hz sample */
0312     { {8, 0}, {4, 0}, {2, 0}, {1, 0} },     /* 200 Hz sample */
0313     { {4, 0}, {2, 0}, {1, 0}, {0, 500000} },    /* 100 Hz sample */
0314     { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} },   /* 50 Hz sample */
0315     { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} },   /* 12.5 Hz sample */
0316     { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} },   /* 6.25 Hz sample */
0317     { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} }    /* 1.56 Hz sample */
0318     },
0319     { /* low noise low power */
0320     { {16, 0}, {8, 0}, {4, 0}, {2, 0} },
0321     { {16, 0}, {8, 0}, {4, 0}, {2, 0} },
0322     { {8, 0}, {4, 0}, {2, 0}, {1, 0} },
0323     { {4, 0}, {2, 0}, {1, 0}, {0, 500000} },
0324     { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} },
0325     { {0, 500000}, {0, 250000}, {0, 125000}, {0, 063000} },
0326     { {0, 500000}, {0, 250000}, {0, 125000}, {0, 063000} },
0327     { {0, 500000}, {0, 250000}, {0, 125000}, {0, 063000} }
0328     },
0329     { /* high resolution */
0330     { {16, 0}, {8, 0}, {4, 0}, {2, 0} },
0331     { {16, 0}, {8, 0}, {4, 0}, {2, 0} },
0332     { {16, 0}, {8, 0}, {4, 0}, {2, 0} },
0333     { {16, 0}, {8, 0}, {4, 0}, {2, 0} },
0334     { {16, 0}, {8, 0}, {4, 0}, {2, 0} },
0335     { {16, 0}, {8, 0}, {4, 0}, {2, 0} },
0336     { {16, 0}, {8, 0}, {4, 0}, {2, 0} },
0337     { {16, 0}, {8, 0}, {4, 0}, {2, 0} }
0338     },
0339     { /* low power */
0340     { {16, 0}, {8, 0}, {4, 0}, {2, 0} },
0341     { {8, 0}, {4, 0}, {2, 0}, {1, 0} },
0342     { {4, 0}, {2, 0}, {1, 0}, {0, 500000} },
0343     { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} },
0344     { {1, 0}, {0, 500000}, {0, 250000}, {0, 125000} },
0345     { {0, 250000}, {0, 125000}, {0, 063000}, {0, 031000} },
0346     { {0, 250000}, {0, 125000}, {0, 063000}, {0, 031000} },
0347     { {0, 250000}, {0, 125000}, {0, 063000}, {0, 031000} }
0348     }
0349 };
0350 
0351 /* Datasheet table "MODS Oversampling modes averaging values at each ODR" */
0352 static const u16 mma8452_os_ratio[4][8] = {
0353     /* 800 Hz, 400 Hz, ... , 1.56 Hz */
0354     { 2, 4, 4, 4, 4, 16, 32, 128 },     /* normal */
0355     { 2, 4, 4, 4, 4, 4, 8, 32 },        /* low power low noise */
0356     { 2, 4, 8, 16, 32, 128, 256, 1024 },    /* high resolution */
0357     { 2, 2, 2, 2, 2, 2, 4, 16 }     /* low power */
0358 };
0359 
0360 static int mma8452_get_power_mode(struct mma8452_data *data)
0361 {
0362     int reg;
0363 
0364     reg = i2c_smbus_read_byte_data(data->client,
0365                        MMA8452_CTRL_REG2);
0366     if (reg < 0)
0367         return reg;
0368 
0369     return ((reg & MMA8452_CTRL_REG2_MODS_MASK) >>
0370         MMA8452_CTRL_REG2_MODS_SHIFT);
0371 }
0372 
0373 static ssize_t mma8452_show_samp_freq_avail(struct device *dev,
0374                         struct device_attribute *attr,
0375                         char *buf)
0376 {
0377     return mma8452_show_int_plus_micros(buf, mma8452_samp_freq,
0378                         ARRAY_SIZE(mma8452_samp_freq));
0379 }
0380 
0381 static ssize_t mma8452_show_scale_avail(struct device *dev,
0382                     struct device_attribute *attr,
0383                     char *buf)
0384 {
0385     struct iio_dev *indio_dev = dev_to_iio_dev(dev);
0386     struct mma8452_data *data = iio_priv(indio_dev);
0387 
0388     return mma8452_show_int_plus_micros(buf, data->chip_info->mma_scales,
0389         ARRAY_SIZE(data->chip_info->mma_scales));
0390 }
0391 
0392 static ssize_t mma8452_show_hp_cutoff_avail(struct device *dev,
0393                         struct device_attribute *attr,
0394                         char *buf)
0395 {
0396     struct iio_dev *indio_dev = dev_to_iio_dev(dev);
0397     struct mma8452_data *data = iio_priv(indio_dev);
0398     int i, j;
0399 
0400     i = mma8452_get_odr_index(data);
0401     j = mma8452_get_power_mode(data);
0402     if (j < 0)
0403         return j;
0404 
0405     return mma8452_show_int_plus_micros(buf, mma8452_hp_filter_cutoff[j][i],
0406         ARRAY_SIZE(mma8452_hp_filter_cutoff[0][0]));
0407 }
0408 
0409 static ssize_t mma8452_show_os_ratio_avail(struct device *dev,
0410                        struct device_attribute *attr,
0411                        char *buf)
0412 {
0413     struct iio_dev *indio_dev = dev_to_iio_dev(dev);
0414     struct mma8452_data *data = iio_priv(indio_dev);
0415     int i = mma8452_get_odr_index(data);
0416     int j;
0417     u16 val = 0;
0418     size_t len = 0;
0419 
0420     for (j = 0; j < ARRAY_SIZE(mma8452_os_ratio); j++) {
0421         if (val == mma8452_os_ratio[j][i])
0422             continue;
0423 
0424         val = mma8452_os_ratio[j][i];
0425 
0426         len += scnprintf(buf + len, PAGE_SIZE - len, "%d ", val);
0427     }
0428     buf[len - 1] = '\n';
0429 
0430     return len;
0431 }
0432 
0433 static IIO_DEV_ATTR_SAMP_FREQ_AVAIL(mma8452_show_samp_freq_avail);
0434 static IIO_DEVICE_ATTR(in_accel_scale_available, 0444,
0435                mma8452_show_scale_avail, NULL, 0);
0436 static IIO_DEVICE_ATTR(in_accel_filter_high_pass_3db_frequency_available,
0437                0444, mma8452_show_hp_cutoff_avail, NULL, 0);
0438 static IIO_DEVICE_ATTR(in_accel_oversampling_ratio_available, 0444,
0439                mma8452_show_os_ratio_avail, NULL, 0);
0440 
0441 static int mma8452_get_samp_freq_index(struct mma8452_data *data,
0442                        int val, int val2)
0443 {
0444     return mma8452_get_int_plus_micros_index(mma8452_samp_freq,
0445                          ARRAY_SIZE(mma8452_samp_freq),
0446                          val, val2);
0447 }
0448 
0449 static int mma8452_get_scale_index(struct mma8452_data *data, int val, int val2)
0450 {
0451     return mma8452_get_int_plus_micros_index(data->chip_info->mma_scales,
0452             ARRAY_SIZE(data->chip_info->mma_scales), val, val2);
0453 }
0454 
0455 static int mma8452_get_hp_filter_index(struct mma8452_data *data,
0456                        int val, int val2)
0457 {
0458     int i, j;
0459 
0460     i = mma8452_get_odr_index(data);
0461     j = mma8452_get_power_mode(data);
0462     if (j < 0)
0463         return j;
0464 
0465     return mma8452_get_int_plus_micros_index(mma8452_hp_filter_cutoff[j][i],
0466         ARRAY_SIZE(mma8452_hp_filter_cutoff[0][0]), val, val2);
0467 }
0468 
0469 static int mma8452_read_hp_filter(struct mma8452_data *data, int *hz, int *uHz)
0470 {
0471     int j, i, ret;
0472 
0473     ret = i2c_smbus_read_byte_data(data->client, MMA8452_HP_FILTER_CUTOFF);
0474     if (ret < 0)
0475         return ret;
0476 
0477     i = mma8452_get_odr_index(data);
0478     j = mma8452_get_power_mode(data);
0479     if (j < 0)
0480         return j;
0481 
0482     ret &= MMA8452_HP_FILTER_CUTOFF_SEL_MASK;
0483     *hz = mma8452_hp_filter_cutoff[j][i][ret][0];
0484     *uHz = mma8452_hp_filter_cutoff[j][i][ret][1];
0485 
0486     return 0;
0487 }
0488 
0489 static int mma8452_read_raw(struct iio_dev *indio_dev,
0490                 struct iio_chan_spec const *chan,
0491                 int *val, int *val2, long mask)
0492 {
0493     struct mma8452_data *data = iio_priv(indio_dev);
0494     __be16 buffer[3];
0495     int i, ret;
0496 
0497     switch (mask) {
0498     case IIO_CHAN_INFO_RAW:
0499         ret = iio_device_claim_direct_mode(indio_dev);
0500         if (ret)
0501             return ret;
0502 
0503         mutex_lock(&data->lock);
0504         ret = mma8452_read(data, buffer);
0505         mutex_unlock(&data->lock);
0506         iio_device_release_direct_mode(indio_dev);
0507         if (ret < 0)
0508             return ret;
0509 
0510         *val = sign_extend32(be16_to_cpu(
0511             buffer[chan->scan_index]) >> chan->scan_type.shift,
0512             chan->scan_type.realbits - 1);
0513 
0514         return IIO_VAL_INT;
0515     case IIO_CHAN_INFO_SCALE:
0516         i = data->data_cfg & MMA8452_DATA_CFG_FS_MASK;
0517         *val = data->chip_info->mma_scales[i][0];
0518         *val2 = data->chip_info->mma_scales[i][1];
0519 
0520         return IIO_VAL_INT_PLUS_MICRO;
0521     case IIO_CHAN_INFO_SAMP_FREQ:
0522         i = mma8452_get_odr_index(data);
0523         *val = mma8452_samp_freq[i][0];
0524         *val2 = mma8452_samp_freq[i][1];
0525 
0526         return IIO_VAL_INT_PLUS_MICRO;
0527     case IIO_CHAN_INFO_CALIBBIAS:
0528         ret = i2c_smbus_read_byte_data(data->client,
0529                            MMA8452_OFF_X +
0530                            chan->scan_index);
0531         if (ret < 0)
0532             return ret;
0533 
0534         *val = sign_extend32(ret, 7);
0535 
0536         return IIO_VAL_INT;
0537     case IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY:
0538         if (data->data_cfg & MMA8452_DATA_CFG_HPF_MASK) {
0539             ret = mma8452_read_hp_filter(data, val, val2);
0540             if (ret < 0)
0541                 return ret;
0542         } else {
0543             *val = 0;
0544             *val2 = 0;
0545         }
0546 
0547         return IIO_VAL_INT_PLUS_MICRO;
0548     case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
0549         ret = mma8452_get_power_mode(data);
0550         if (ret < 0)
0551             return ret;
0552 
0553         i = mma8452_get_odr_index(data);
0554 
0555         *val = mma8452_os_ratio[ret][i];
0556         return IIO_VAL_INT;
0557     }
0558 
0559     return -EINVAL;
0560 }
0561 
0562 static int mma8452_calculate_sleep(struct mma8452_data *data)
0563 {
0564     int ret, i = mma8452_get_odr_index(data);
0565 
0566     if (mma8452_samp_freq[i][0] > 0)
0567         ret = 1000 / mma8452_samp_freq[i][0];
0568     else
0569         ret = 1000;
0570 
0571     return ret == 0 ? 1 : ret;
0572 }
0573 
0574 static int mma8452_standby(struct mma8452_data *data)
0575 {
0576     return i2c_smbus_write_byte_data(data->client, MMA8452_CTRL_REG1,
0577                     data->ctrl_reg1 & ~MMA8452_CTRL_ACTIVE);
0578 }
0579 
0580 static int mma8452_active(struct mma8452_data *data)
0581 {
0582     return i2c_smbus_write_byte_data(data->client, MMA8452_CTRL_REG1,
0583                      data->ctrl_reg1);
0584 }
0585 
0586 /* returns >0 if active, 0 if in standby and <0 on error */
0587 static int mma8452_is_active(struct mma8452_data *data)
0588 {
0589     int reg;
0590 
0591     reg = i2c_smbus_read_byte_data(data->client, MMA8452_CTRL_REG1);
0592     if (reg < 0)
0593         return reg;
0594 
0595     return reg & MMA8452_CTRL_ACTIVE;
0596 }
0597 
0598 static int mma8452_change_config(struct mma8452_data *data, u8 reg, u8 val)
0599 {
0600     int ret;
0601     int is_active;
0602 
0603     mutex_lock(&data->lock);
0604 
0605     is_active = mma8452_is_active(data);
0606     if (is_active < 0) {
0607         ret = is_active;
0608         goto fail;
0609     }
0610 
0611     /* config can only be changed when in standby */
0612     if (is_active > 0) {
0613         ret = mma8452_standby(data);
0614         if (ret < 0)
0615             goto fail;
0616     }
0617 
0618     ret = i2c_smbus_write_byte_data(data->client, reg, val);
0619     if (ret < 0)
0620         goto fail;
0621 
0622     if (is_active > 0) {
0623         ret = mma8452_active(data);
0624         if (ret < 0)
0625             goto fail;
0626     }
0627 
0628     ret = 0;
0629 fail:
0630     mutex_unlock(&data->lock);
0631 
0632     return ret;
0633 }
0634 
0635 static int mma8452_set_power_mode(struct mma8452_data *data, u8 mode)
0636 {
0637     int reg;
0638 
0639     reg = i2c_smbus_read_byte_data(data->client,
0640                        MMA8452_CTRL_REG2);
0641     if (reg < 0)
0642         return reg;
0643 
0644     reg &= ~MMA8452_CTRL_REG2_MODS_MASK;
0645     reg |= mode << MMA8452_CTRL_REG2_MODS_SHIFT;
0646 
0647     return mma8452_change_config(data, MMA8452_CTRL_REG2, reg);
0648 }
0649 
0650 /* returns >0 if in freefall mode, 0 if not or <0 if an error occurred */
0651 static int mma8452_freefall_mode_enabled(struct mma8452_data *data)
0652 {
0653     int val;
0654 
0655     val = i2c_smbus_read_byte_data(data->client, MMA8452_FF_MT_CFG);
0656     if (val < 0)
0657         return val;
0658 
0659     return !(val & MMA8452_FF_MT_CFG_OAE);
0660 }
0661 
0662 static int mma8452_set_freefall_mode(struct mma8452_data *data, bool state)
0663 {
0664     int val;
0665 
0666     if ((state && mma8452_freefall_mode_enabled(data)) ||
0667         (!state && !(mma8452_freefall_mode_enabled(data))))
0668         return 0;
0669 
0670     val = i2c_smbus_read_byte_data(data->client, MMA8452_FF_MT_CFG);
0671     if (val < 0)
0672         return val;
0673 
0674     if (state) {
0675         val |= BIT(idx_x + MMA8452_FF_MT_CHAN_SHIFT);
0676         val |= BIT(idx_y + MMA8452_FF_MT_CHAN_SHIFT);
0677         val |= BIT(idx_z + MMA8452_FF_MT_CHAN_SHIFT);
0678         val &= ~MMA8452_FF_MT_CFG_OAE;
0679     } else {
0680         val &= ~BIT(idx_x + MMA8452_FF_MT_CHAN_SHIFT);
0681         val &= ~BIT(idx_y + MMA8452_FF_MT_CHAN_SHIFT);
0682         val &= ~BIT(idx_z + MMA8452_FF_MT_CHAN_SHIFT);
0683         val |= MMA8452_FF_MT_CFG_OAE;
0684     }
0685 
0686     return mma8452_change_config(data, MMA8452_FF_MT_CFG, val);
0687 }
0688 
0689 static int mma8452_set_hp_filter_frequency(struct mma8452_data *data,
0690                        int val, int val2)
0691 {
0692     int i, reg;
0693 
0694     i = mma8452_get_hp_filter_index(data, val, val2);
0695     if (i < 0)
0696         return i;
0697 
0698     reg = i2c_smbus_read_byte_data(data->client,
0699                        MMA8452_HP_FILTER_CUTOFF);
0700     if (reg < 0)
0701         return reg;
0702 
0703     reg &= ~MMA8452_HP_FILTER_CUTOFF_SEL_MASK;
0704     reg |= i;
0705 
0706     return mma8452_change_config(data, MMA8452_HP_FILTER_CUTOFF, reg);
0707 }
0708 
0709 static int mma8452_write_raw(struct iio_dev *indio_dev,
0710                  struct iio_chan_spec const *chan,
0711                  int val, int val2, long mask)
0712 {
0713     struct mma8452_data *data = iio_priv(indio_dev);
0714     int i, ret;
0715 
0716     ret = iio_device_claim_direct_mode(indio_dev);
0717     if (ret)
0718         return ret;
0719 
0720     switch (mask) {
0721     case IIO_CHAN_INFO_SAMP_FREQ:
0722         i = mma8452_get_samp_freq_index(data, val, val2);
0723         if (i < 0) {
0724             ret = i;
0725             break;
0726         }
0727         data->ctrl_reg1 &= ~MMA8452_CTRL_DR_MASK;
0728         data->ctrl_reg1 |= i << MMA8452_CTRL_DR_SHIFT;
0729 
0730         data->sleep_val = mma8452_calculate_sleep(data);
0731 
0732         ret = mma8452_change_config(data, MMA8452_CTRL_REG1,
0733                         data->ctrl_reg1);
0734         break;
0735     case IIO_CHAN_INFO_SCALE:
0736         i = mma8452_get_scale_index(data, val, val2);
0737         if (i < 0) {
0738             ret = i;
0739             break;
0740         }
0741 
0742         data->data_cfg &= ~MMA8452_DATA_CFG_FS_MASK;
0743         data->data_cfg |= i;
0744 
0745         ret = mma8452_change_config(data, MMA8452_DATA_CFG,
0746                         data->data_cfg);
0747         break;
0748     case IIO_CHAN_INFO_CALIBBIAS:
0749         if (val < -128 || val > 127) {
0750             ret = -EINVAL;
0751             break;
0752         }
0753 
0754         ret = mma8452_change_config(data,
0755                         MMA8452_OFF_X + chan->scan_index,
0756                         val);
0757         break;
0758 
0759     case IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY:
0760         if (val == 0 && val2 == 0) {
0761             data->data_cfg &= ~MMA8452_DATA_CFG_HPF_MASK;
0762         } else {
0763             data->data_cfg |= MMA8452_DATA_CFG_HPF_MASK;
0764             ret = mma8452_set_hp_filter_frequency(data, val, val2);
0765             if (ret < 0)
0766                 break;
0767         }
0768 
0769         ret = mma8452_change_config(data, MMA8452_DATA_CFG,
0770                          data->data_cfg);
0771         break;
0772 
0773     case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
0774         ret = mma8452_get_odr_index(data);
0775 
0776         for (i = 0; i < ARRAY_SIZE(mma8452_os_ratio); i++) {
0777             if (mma8452_os_ratio[i][ret] == val) {
0778                 ret = mma8452_set_power_mode(data, i);
0779                 break;
0780             }
0781         }
0782         break;
0783     default:
0784         ret = -EINVAL;
0785         break;
0786     }
0787 
0788     iio_device_release_direct_mode(indio_dev);
0789     return ret;
0790 }
0791 
0792 static int mma8452_get_event_regs(struct mma8452_data *data,
0793         const struct iio_chan_spec *chan, enum iio_event_direction dir,
0794         const struct mma8452_event_regs **ev_reg)
0795 {
0796     if (!chan)
0797         return -EINVAL;
0798 
0799     switch (chan->type) {
0800     case IIO_ACCEL:
0801         switch (dir) {
0802         case IIO_EV_DIR_RISING:
0803             if ((data->chip_info->all_events
0804                     & MMA8452_INT_TRANS) &&
0805                 (data->chip_info->enabled_events
0806                     & MMA8452_INT_TRANS))
0807                 *ev_reg = &trans_ev_regs;
0808             else
0809                 *ev_reg = &ff_mt_ev_regs;
0810             return 0;
0811         case IIO_EV_DIR_FALLING:
0812             *ev_reg = &ff_mt_ev_regs;
0813             return 0;
0814         default:
0815             return -EINVAL;
0816         }
0817     default:
0818         return -EINVAL;
0819     }
0820 }
0821 
0822 static int mma8452_read_event_value(struct iio_dev *indio_dev,
0823                    const struct iio_chan_spec *chan,
0824                    enum iio_event_type type,
0825                    enum iio_event_direction dir,
0826                    enum iio_event_info info,
0827                    int *val, int *val2)
0828 {
0829     struct mma8452_data *data = iio_priv(indio_dev);
0830     int ret, us, power_mode;
0831     const struct mma8452_event_regs *ev_regs;
0832 
0833     ret = mma8452_get_event_regs(data, chan, dir, &ev_regs);
0834     if (ret)
0835         return ret;
0836 
0837     switch (info) {
0838     case IIO_EV_INFO_VALUE:
0839         ret = i2c_smbus_read_byte_data(data->client, ev_regs->ev_ths);
0840         if (ret < 0)
0841             return ret;
0842 
0843         *val = ret & ev_regs->ev_ths_mask;
0844 
0845         return IIO_VAL_INT;
0846 
0847     case IIO_EV_INFO_PERIOD:
0848         ret = i2c_smbus_read_byte_data(data->client, ev_regs->ev_count);
0849         if (ret < 0)
0850             return ret;
0851 
0852         power_mode = mma8452_get_power_mode(data);
0853         if (power_mode < 0)
0854             return power_mode;
0855 
0856         us = ret * mma8452_time_step_us[power_mode][
0857                 mma8452_get_odr_index(data)];
0858         *val = us / USEC_PER_SEC;
0859         *val2 = us % USEC_PER_SEC;
0860 
0861         return IIO_VAL_INT_PLUS_MICRO;
0862 
0863     case IIO_EV_INFO_HIGH_PASS_FILTER_3DB:
0864         ret = i2c_smbus_read_byte_data(data->client,
0865                            MMA8452_TRANSIENT_CFG);
0866         if (ret < 0)
0867             return ret;
0868 
0869         if (ret & MMA8452_TRANSIENT_CFG_HPF_BYP) {
0870             *val = 0;
0871             *val2 = 0;
0872         } else {
0873             ret = mma8452_read_hp_filter(data, val, val2);
0874             if (ret < 0)
0875                 return ret;
0876         }
0877 
0878         return IIO_VAL_INT_PLUS_MICRO;
0879 
0880     default:
0881         return -EINVAL;
0882     }
0883 }
0884 
0885 static int mma8452_write_event_value(struct iio_dev *indio_dev,
0886                 const struct iio_chan_spec *chan,
0887                 enum iio_event_type type,
0888                 enum iio_event_direction dir,
0889                 enum iio_event_info info,
0890                 int val, int val2)
0891 {
0892     struct mma8452_data *data = iio_priv(indio_dev);
0893     int ret, reg, steps;
0894     const struct mma8452_event_regs *ev_regs;
0895 
0896     ret = mma8452_get_event_regs(data, chan, dir, &ev_regs);
0897     if (ret)
0898         return ret;
0899 
0900     switch (info) {
0901     case IIO_EV_INFO_VALUE:
0902         if (val < 0 || val > ev_regs->ev_ths_mask)
0903             return -EINVAL;
0904 
0905         return mma8452_change_config(data, ev_regs->ev_ths, val);
0906 
0907     case IIO_EV_INFO_PERIOD:
0908         ret = mma8452_get_power_mode(data);
0909         if (ret < 0)
0910             return ret;
0911 
0912         steps = (val * USEC_PER_SEC + val2) /
0913                 mma8452_time_step_us[ret][
0914                     mma8452_get_odr_index(data)];
0915 
0916         if (steps < 0 || steps > 0xff)
0917             return -EINVAL;
0918 
0919         return mma8452_change_config(data, ev_regs->ev_count, steps);
0920 
0921     case IIO_EV_INFO_HIGH_PASS_FILTER_3DB:
0922         reg = i2c_smbus_read_byte_data(data->client,
0923                            MMA8452_TRANSIENT_CFG);
0924         if (reg < 0)
0925             return reg;
0926 
0927         if (val == 0 && val2 == 0) {
0928             reg |= MMA8452_TRANSIENT_CFG_HPF_BYP;
0929         } else {
0930             reg &= ~MMA8452_TRANSIENT_CFG_HPF_BYP;
0931             ret = mma8452_set_hp_filter_frequency(data, val, val2);
0932             if (ret < 0)
0933                 return ret;
0934         }
0935 
0936         return mma8452_change_config(data, MMA8452_TRANSIENT_CFG, reg);
0937 
0938     default:
0939         return -EINVAL;
0940     }
0941 }
0942 
0943 static int mma8452_read_event_config(struct iio_dev *indio_dev,
0944                      const struct iio_chan_spec *chan,
0945                      enum iio_event_type type,
0946                      enum iio_event_direction dir)
0947 {
0948     struct mma8452_data *data = iio_priv(indio_dev);
0949     int ret;
0950     const struct mma8452_event_regs *ev_regs;
0951 
0952     ret = mma8452_get_event_regs(data, chan, dir, &ev_regs);
0953     if (ret)
0954         return ret;
0955 
0956     switch (dir) {
0957     case IIO_EV_DIR_FALLING:
0958         return mma8452_freefall_mode_enabled(data);
0959     case IIO_EV_DIR_RISING:
0960         ret = i2c_smbus_read_byte_data(data->client,
0961                 ev_regs->ev_cfg);
0962         if (ret < 0)
0963             return ret;
0964 
0965         return !!(ret & BIT(chan->scan_index +
0966                 ev_regs->ev_cfg_chan_shift));
0967     default:
0968         return -EINVAL;
0969     }
0970 }
0971 
0972 static int mma8452_write_event_config(struct iio_dev *indio_dev,
0973                       const struct iio_chan_spec *chan,
0974                       enum iio_event_type type,
0975                       enum iio_event_direction dir,
0976                       int state)
0977 {
0978     struct mma8452_data *data = iio_priv(indio_dev);
0979     int val, ret;
0980     const struct mma8452_event_regs *ev_regs;
0981 
0982     ret = mma8452_get_event_regs(data, chan, dir, &ev_regs);
0983     if (ret)
0984         return ret;
0985 
0986     ret = mma8452_set_runtime_pm_state(data->client, state);
0987     if (ret)
0988         return ret;
0989 
0990     switch (dir) {
0991     case IIO_EV_DIR_FALLING:
0992         return mma8452_set_freefall_mode(data, state);
0993     case IIO_EV_DIR_RISING:
0994         val = i2c_smbus_read_byte_data(data->client, ev_regs->ev_cfg);
0995         if (val < 0)
0996             return val;
0997 
0998         if (state) {
0999             if (mma8452_freefall_mode_enabled(data)) {
1000                 val &= ~BIT(idx_x + ev_regs->ev_cfg_chan_shift);
1001                 val &= ~BIT(idx_y + ev_regs->ev_cfg_chan_shift);
1002                 val &= ~BIT(idx_z + ev_regs->ev_cfg_chan_shift);
1003                 val |= MMA8452_FF_MT_CFG_OAE;
1004             }
1005             val |= BIT(chan->scan_index +
1006                     ev_regs->ev_cfg_chan_shift);
1007         } else {
1008             if (mma8452_freefall_mode_enabled(data))
1009                 return 0;
1010 
1011             val &= ~BIT(chan->scan_index +
1012                     ev_regs->ev_cfg_chan_shift);
1013         }
1014 
1015         val |= ev_regs->ev_cfg_ele;
1016 
1017         return mma8452_change_config(data, ev_regs->ev_cfg, val);
1018     default:
1019         return -EINVAL;
1020     }
1021 }
1022 
1023 static void mma8452_transient_interrupt(struct iio_dev *indio_dev)
1024 {
1025     struct mma8452_data *data = iio_priv(indio_dev);
1026     s64 ts = iio_get_time_ns(indio_dev);
1027     int src;
1028 
1029     src = i2c_smbus_read_byte_data(data->client, MMA8452_TRANSIENT_SRC);
1030     if (src < 0)
1031         return;
1032 
1033     if (src & MMA8452_TRANSIENT_SRC_XTRANSE)
1034         iio_push_event(indio_dev,
1035                    IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_X,
1036                           IIO_EV_TYPE_MAG,
1037                           IIO_EV_DIR_RISING),
1038                    ts);
1039 
1040     if (src & MMA8452_TRANSIENT_SRC_YTRANSE)
1041         iio_push_event(indio_dev,
1042                    IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_Y,
1043                           IIO_EV_TYPE_MAG,
1044                           IIO_EV_DIR_RISING),
1045                    ts);
1046 
1047     if (src & MMA8452_TRANSIENT_SRC_ZTRANSE)
1048         iio_push_event(indio_dev,
1049                    IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_Z,
1050                           IIO_EV_TYPE_MAG,
1051                           IIO_EV_DIR_RISING),
1052                    ts);
1053 }
1054 
1055 static irqreturn_t mma8452_interrupt(int irq, void *p)
1056 {
1057     struct iio_dev *indio_dev = p;
1058     struct mma8452_data *data = iio_priv(indio_dev);
1059     irqreturn_t ret = IRQ_NONE;
1060     int src;
1061 
1062     src = i2c_smbus_read_byte_data(data->client, MMA8452_INT_SRC);
1063     if (src < 0)
1064         return IRQ_NONE;
1065 
1066     if (!(src & (data->chip_info->enabled_events | MMA8452_INT_DRDY)))
1067         return IRQ_NONE;
1068 
1069     if (src & MMA8452_INT_DRDY) {
1070         iio_trigger_poll_chained(indio_dev->trig);
1071         ret = IRQ_HANDLED;
1072     }
1073 
1074     if (src & MMA8452_INT_FF_MT) {
1075         if (mma8452_freefall_mode_enabled(data)) {
1076             s64 ts = iio_get_time_ns(indio_dev);
1077 
1078             iio_push_event(indio_dev,
1079                        IIO_MOD_EVENT_CODE(IIO_ACCEL, 0,
1080                               IIO_MOD_X_AND_Y_AND_Z,
1081                               IIO_EV_TYPE_MAG,
1082                               IIO_EV_DIR_FALLING),
1083                     ts);
1084         }
1085         ret = IRQ_HANDLED;
1086     }
1087 
1088     if (src & MMA8452_INT_TRANS) {
1089         mma8452_transient_interrupt(indio_dev);
1090         ret = IRQ_HANDLED;
1091     }
1092 
1093     return ret;
1094 }
1095 
1096 static irqreturn_t mma8452_trigger_handler(int irq, void *p)
1097 {
1098     struct iio_poll_func *pf = p;
1099     struct iio_dev *indio_dev = pf->indio_dev;
1100     struct mma8452_data *data = iio_priv(indio_dev);
1101     int ret;
1102 
1103     ret = mma8452_read(data, data->buffer.channels);
1104     if (ret < 0)
1105         goto done;
1106 
1107     iio_push_to_buffers_with_timestamp(indio_dev, &data->buffer,
1108                        iio_get_time_ns(indio_dev));
1109 
1110 done:
1111     iio_trigger_notify_done(indio_dev->trig);
1112 
1113     return IRQ_HANDLED;
1114 }
1115 
1116 static int mma8452_reg_access_dbg(struct iio_dev *indio_dev,
1117                   unsigned int reg, unsigned int writeval,
1118                   unsigned int *readval)
1119 {
1120     int ret;
1121     struct mma8452_data *data = iio_priv(indio_dev);
1122 
1123     if (reg > MMA8452_MAX_REG)
1124         return -EINVAL;
1125 
1126     if (!readval)
1127         return mma8452_change_config(data, reg, writeval);
1128 
1129     ret = i2c_smbus_read_byte_data(data->client, reg);
1130     if (ret < 0)
1131         return ret;
1132 
1133     *readval = ret;
1134 
1135     return 0;
1136 }
1137 
1138 static const struct iio_event_spec mma8452_freefall_event[] = {
1139     {
1140         .type = IIO_EV_TYPE_MAG,
1141         .dir = IIO_EV_DIR_FALLING,
1142         .mask_separate = BIT(IIO_EV_INFO_ENABLE),
1143         .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) |
1144                     BIT(IIO_EV_INFO_PERIOD) |
1145                     BIT(IIO_EV_INFO_HIGH_PASS_FILTER_3DB)
1146     },
1147 };
1148 
1149 static const struct iio_event_spec mma8652_freefall_event[] = {
1150     {
1151         .type = IIO_EV_TYPE_MAG,
1152         .dir = IIO_EV_DIR_FALLING,
1153         .mask_separate = BIT(IIO_EV_INFO_ENABLE),
1154         .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) |
1155                     BIT(IIO_EV_INFO_PERIOD)
1156     },
1157 };
1158 
1159 static const struct iio_event_spec mma8452_transient_event[] = {
1160     {
1161         .type = IIO_EV_TYPE_MAG,
1162         .dir = IIO_EV_DIR_RISING,
1163         .mask_separate = BIT(IIO_EV_INFO_ENABLE),
1164         .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) |
1165                     BIT(IIO_EV_INFO_PERIOD) |
1166                     BIT(IIO_EV_INFO_HIGH_PASS_FILTER_3DB)
1167     },
1168 };
1169 
1170 static const struct iio_event_spec mma8452_motion_event[] = {
1171     {
1172         .type = IIO_EV_TYPE_MAG,
1173         .dir = IIO_EV_DIR_RISING,
1174         .mask_separate = BIT(IIO_EV_INFO_ENABLE),
1175         .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) |
1176                     BIT(IIO_EV_INFO_PERIOD)
1177     },
1178 };
1179 
1180 /*
1181  * Threshold is configured in fixed 8G/127 steps regardless of
1182  * currently selected scale for measurement.
1183  */
1184 static IIO_CONST_ATTR_NAMED(accel_transient_scale, in_accel_scale, "0.617742");
1185 
1186 static struct attribute *mma8452_event_attributes[] = {
1187     &iio_const_attr_accel_transient_scale.dev_attr.attr,
1188     NULL,
1189 };
1190 
1191 static const struct attribute_group mma8452_event_attribute_group = {
1192     .attrs = mma8452_event_attributes,
1193 };
1194 
1195 static const struct iio_mount_matrix *
1196 mma8452_get_mount_matrix(const struct iio_dev *indio_dev,
1197                const struct iio_chan_spec *chan)
1198 {
1199     struct mma8452_data *data = iio_priv(indio_dev);
1200 
1201     return &data->orientation;
1202 }
1203 
1204 static const struct iio_chan_spec_ext_info mma8452_ext_info[] = {
1205     IIO_MOUNT_MATRIX(IIO_SHARED_BY_TYPE, mma8452_get_mount_matrix),
1206     { }
1207 };
1208 
1209 #define MMA8452_FREEFALL_CHANNEL(modifier) { \
1210     .type = IIO_ACCEL, \
1211     .modified = 1, \
1212     .channel2 = modifier, \
1213     .scan_index = -1, \
1214     .event_spec = mma8452_freefall_event, \
1215     .num_event_specs = ARRAY_SIZE(mma8452_freefall_event), \
1216 }
1217 
1218 #define MMA8652_FREEFALL_CHANNEL(modifier) { \
1219     .type = IIO_ACCEL, \
1220     .modified = 1, \
1221     .channel2 = modifier, \
1222     .scan_index = -1, \
1223     .event_spec = mma8652_freefall_event, \
1224     .num_event_specs = ARRAY_SIZE(mma8652_freefall_event), \
1225 }
1226 
1227 #define MMA8452_CHANNEL(axis, idx, bits) { \
1228     .type = IIO_ACCEL, \
1229     .modified = 1, \
1230     .channel2 = IIO_MOD_##axis, \
1231     .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
1232                   BIT(IIO_CHAN_INFO_CALIBBIAS), \
1233     .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \
1234             BIT(IIO_CHAN_INFO_SCALE) | \
1235             BIT(IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY) | \
1236             BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \
1237     .scan_index = idx, \
1238     .scan_type = { \
1239         .sign = 's', \
1240         .realbits = (bits), \
1241         .storagebits = 16, \
1242         .shift = 16 - (bits), \
1243         .endianness = IIO_BE, \
1244     }, \
1245     .event_spec = mma8452_transient_event, \
1246     .num_event_specs = ARRAY_SIZE(mma8452_transient_event), \
1247     .ext_info = mma8452_ext_info, \
1248 }
1249 
1250 #define MMA8652_CHANNEL(axis, idx, bits) { \
1251     .type = IIO_ACCEL, \
1252     .modified = 1, \
1253     .channel2 = IIO_MOD_##axis, \
1254     .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
1255         BIT(IIO_CHAN_INFO_CALIBBIAS), \
1256     .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \
1257         BIT(IIO_CHAN_INFO_SCALE) | \
1258         BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \
1259     .scan_index = idx, \
1260     .scan_type = { \
1261         .sign = 's', \
1262         .realbits = (bits), \
1263         .storagebits = 16, \
1264         .shift = 16 - (bits), \
1265         .endianness = IIO_BE, \
1266     }, \
1267     .event_spec = mma8452_motion_event, \
1268     .num_event_specs = ARRAY_SIZE(mma8452_motion_event), \
1269     .ext_info = mma8452_ext_info, \
1270 }
1271 
1272 static const struct iio_chan_spec mma8451_channels[] = {
1273     MMA8452_CHANNEL(X, idx_x, 14),
1274     MMA8452_CHANNEL(Y, idx_y, 14),
1275     MMA8452_CHANNEL(Z, idx_z, 14),
1276     IIO_CHAN_SOFT_TIMESTAMP(idx_ts),
1277     MMA8452_FREEFALL_CHANNEL(IIO_MOD_X_AND_Y_AND_Z),
1278 };
1279 
1280 static const struct iio_chan_spec mma8452_channels[] = {
1281     MMA8452_CHANNEL(X, idx_x, 12),
1282     MMA8452_CHANNEL(Y, idx_y, 12),
1283     MMA8452_CHANNEL(Z, idx_z, 12),
1284     IIO_CHAN_SOFT_TIMESTAMP(idx_ts),
1285     MMA8452_FREEFALL_CHANNEL(IIO_MOD_X_AND_Y_AND_Z),
1286 };
1287 
1288 static const struct iio_chan_spec mma8453_channels[] = {
1289     MMA8452_CHANNEL(X, idx_x, 10),
1290     MMA8452_CHANNEL(Y, idx_y, 10),
1291     MMA8452_CHANNEL(Z, idx_z, 10),
1292     IIO_CHAN_SOFT_TIMESTAMP(idx_ts),
1293     MMA8452_FREEFALL_CHANNEL(IIO_MOD_X_AND_Y_AND_Z),
1294 };
1295 
1296 static const struct iio_chan_spec mma8652_channels[] = {
1297     MMA8652_CHANNEL(X, idx_x, 12),
1298     MMA8652_CHANNEL(Y, idx_y, 12),
1299     MMA8652_CHANNEL(Z, idx_z, 12),
1300     IIO_CHAN_SOFT_TIMESTAMP(idx_ts),
1301     MMA8652_FREEFALL_CHANNEL(IIO_MOD_X_AND_Y_AND_Z),
1302 };
1303 
1304 static const struct iio_chan_spec mma8653_channels[] = {
1305     MMA8652_CHANNEL(X, idx_x, 10),
1306     MMA8652_CHANNEL(Y, idx_y, 10),
1307     MMA8652_CHANNEL(Z, idx_z, 10),
1308     IIO_CHAN_SOFT_TIMESTAMP(idx_ts),
1309     MMA8652_FREEFALL_CHANNEL(IIO_MOD_X_AND_Y_AND_Z),
1310 };
1311 
1312 enum {
1313     mma8451,
1314     mma8452,
1315     mma8453,
1316     mma8652,
1317     mma8653,
1318     fxls8471,
1319 };
1320 
1321 static const struct mma_chip_info mma_chip_info_table[] = {
1322     [mma8451] = {
1323         .name = "mma8451",
1324         .chip_id = MMA8451_DEVICE_ID,
1325         .channels = mma8451_channels,
1326         .num_channels = ARRAY_SIZE(mma8451_channels),
1327         /*
1328          * Hardware has fullscale of -2G, -4G, -8G corresponding to
1329          * raw value -8192 for 14 bit, -2048 for 12 bit or -512 for 10
1330          * bit.
1331          * The userspace interface uses m/s^2 and we declare micro units
1332          * So scale factor for 12 bit here is given by:
1333          *  g * N * 1000000 / 2048 for N = 2, 4, 8 and g=9.80665
1334          */
1335         .mma_scales = { {0, 2394}, {0, 4788}, {0, 9577} },
1336         /*
1337          * Although we enable the interrupt sources once and for
1338          * all here the event detection itself is not enabled until
1339          * userspace asks for it by mma8452_write_event_config()
1340          */
1341         .all_events = MMA8452_INT_DRDY |
1342                     MMA8452_INT_TRANS |
1343                     MMA8452_INT_FF_MT,
1344         .enabled_events = MMA8452_INT_TRANS |
1345                     MMA8452_INT_FF_MT,
1346     },
1347     [mma8452] = {
1348         .name = "mma8452",
1349         .chip_id = MMA8452_DEVICE_ID,
1350         .channels = mma8452_channels,
1351         .num_channels = ARRAY_SIZE(mma8452_channels),
1352         .mma_scales = { {0, 9577}, {0, 19154}, {0, 38307} },
1353         /*
1354          * Although we enable the interrupt sources once and for
1355          * all here the event detection itself is not enabled until
1356          * userspace asks for it by mma8452_write_event_config()
1357          */
1358         .all_events = MMA8452_INT_DRDY |
1359                     MMA8452_INT_TRANS |
1360                     MMA8452_INT_FF_MT,
1361         .enabled_events = MMA8452_INT_TRANS |
1362                     MMA8452_INT_FF_MT,
1363     },
1364     [mma8453] = {
1365         .name = "mma8453",
1366         .chip_id = MMA8453_DEVICE_ID,
1367         .channels = mma8453_channels,
1368         .num_channels = ARRAY_SIZE(mma8453_channels),
1369         .mma_scales = { {0, 38307}, {0, 76614}, {0, 153228} },
1370         /*
1371          * Although we enable the interrupt sources once and for
1372          * all here the event detection itself is not enabled until
1373          * userspace asks for it by mma8452_write_event_config()
1374          */
1375         .all_events = MMA8452_INT_DRDY |
1376                     MMA8452_INT_TRANS |
1377                     MMA8452_INT_FF_MT,
1378         .enabled_events = MMA8452_INT_TRANS |
1379                     MMA8452_INT_FF_MT,
1380     },
1381     [mma8652] = {
1382         .name = "mma8652",
1383         .chip_id = MMA8652_DEVICE_ID,
1384         .channels = mma8652_channels,
1385         .num_channels = ARRAY_SIZE(mma8652_channels),
1386         .mma_scales = { {0, 9577}, {0, 19154}, {0, 38307} },
1387         .all_events = MMA8452_INT_DRDY |
1388                     MMA8452_INT_FF_MT,
1389         .enabled_events = MMA8452_INT_FF_MT,
1390     },
1391     [mma8653] = {
1392         .name = "mma8653",
1393         .chip_id = MMA8653_DEVICE_ID,
1394         .channels = mma8653_channels,
1395         .num_channels = ARRAY_SIZE(mma8653_channels),
1396         .mma_scales = { {0, 38307}, {0, 76614}, {0, 153228} },
1397         /*
1398          * Although we enable the interrupt sources once and for
1399          * all here the event detection itself is not enabled until
1400          * userspace asks for it by mma8452_write_event_config()
1401          */
1402         .all_events = MMA8452_INT_DRDY |
1403                     MMA8452_INT_FF_MT,
1404         .enabled_events = MMA8452_INT_FF_MT,
1405     },
1406     [fxls8471] = {
1407         .name = "fxls8471",
1408         .chip_id = FXLS8471_DEVICE_ID,
1409         .channels = mma8451_channels,
1410         .num_channels = ARRAY_SIZE(mma8451_channels),
1411         .mma_scales = { {0, 2394}, {0, 4788}, {0, 9577} },
1412         /*
1413          * Although we enable the interrupt sources once and for
1414          * all here the event detection itself is not enabled until
1415          * userspace asks for it by mma8452_write_event_config()
1416          */
1417         .all_events = MMA8452_INT_DRDY |
1418                     MMA8452_INT_TRANS |
1419                     MMA8452_INT_FF_MT,
1420         .enabled_events = MMA8452_INT_TRANS |
1421                     MMA8452_INT_FF_MT,
1422     },
1423 };
1424 
1425 static struct attribute *mma8452_attributes[] = {
1426     &iio_dev_attr_sampling_frequency_available.dev_attr.attr,
1427     &iio_dev_attr_in_accel_scale_available.dev_attr.attr,
1428     &iio_dev_attr_in_accel_filter_high_pass_3db_frequency_available.dev_attr.attr,
1429     &iio_dev_attr_in_accel_oversampling_ratio_available.dev_attr.attr,
1430     NULL
1431 };
1432 
1433 static const struct attribute_group mma8452_group = {
1434     .attrs = mma8452_attributes,
1435 };
1436 
1437 static const struct iio_info mma8452_info = {
1438     .attrs = &mma8452_group,
1439     .read_raw = &mma8452_read_raw,
1440     .write_raw = &mma8452_write_raw,
1441     .event_attrs = &mma8452_event_attribute_group,
1442     .read_event_value = &mma8452_read_event_value,
1443     .write_event_value = &mma8452_write_event_value,
1444     .read_event_config = &mma8452_read_event_config,
1445     .write_event_config = &mma8452_write_event_config,
1446     .debugfs_reg_access = &mma8452_reg_access_dbg,
1447 };
1448 
1449 static const unsigned long mma8452_scan_masks[] = {0x7, 0};
1450 
1451 static int mma8452_data_rdy_trigger_set_state(struct iio_trigger *trig,
1452                           bool state)
1453 {
1454     struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
1455     struct mma8452_data *data = iio_priv(indio_dev);
1456     int reg, ret;
1457 
1458     ret = mma8452_set_runtime_pm_state(data->client, state);
1459     if (ret)
1460         return ret;
1461 
1462     reg = i2c_smbus_read_byte_data(data->client, MMA8452_CTRL_REG4);
1463     if (reg < 0)
1464         return reg;
1465 
1466     if (state)
1467         reg |= MMA8452_INT_DRDY;
1468     else
1469         reg &= ~MMA8452_INT_DRDY;
1470 
1471     return mma8452_change_config(data, MMA8452_CTRL_REG4, reg);
1472 }
1473 
1474 static const struct iio_trigger_ops mma8452_trigger_ops = {
1475     .set_trigger_state = mma8452_data_rdy_trigger_set_state,
1476     .validate_device = iio_trigger_validate_own_device,
1477 };
1478 
1479 static int mma8452_trigger_setup(struct iio_dev *indio_dev)
1480 {
1481     struct mma8452_data *data = iio_priv(indio_dev);
1482     struct iio_trigger *trig;
1483     int ret;
1484 
1485     trig = devm_iio_trigger_alloc(&data->client->dev, "%s-dev%d",
1486                       indio_dev->name,
1487                       iio_device_id(indio_dev));
1488     if (!trig)
1489         return -ENOMEM;
1490 
1491     trig->ops = &mma8452_trigger_ops;
1492     iio_trigger_set_drvdata(trig, indio_dev);
1493 
1494     ret = iio_trigger_register(trig);
1495     if (ret)
1496         return ret;
1497 
1498     indio_dev->trig = iio_trigger_get(trig);
1499 
1500     return 0;
1501 }
1502 
1503 static void mma8452_trigger_cleanup(struct iio_dev *indio_dev)
1504 {
1505     if (indio_dev->trig)
1506         iio_trigger_unregister(indio_dev->trig);
1507 }
1508 
1509 static int mma8452_reset(struct i2c_client *client)
1510 {
1511     int i;
1512     int ret;
1513 
1514     /*
1515      * Find on fxls8471, after config reset bit, it reset immediately,
1516      * and will not give ACK, so here do not check the return value.
1517      * The following code will read the reset register, and check whether
1518      * this reset works.
1519      */
1520     i2c_smbus_write_byte_data(client, MMA8452_CTRL_REG2,
1521                     MMA8452_CTRL_REG2_RST);
1522 
1523     for (i = 0; i < 10; i++) {
1524         usleep_range(100, 200);
1525         ret = i2c_smbus_read_byte_data(client, MMA8452_CTRL_REG2);
1526         if (ret == -EIO)
1527             continue; /* I2C comm reset */
1528         if (ret < 0)
1529             return ret;
1530         if (!(ret & MMA8452_CTRL_REG2_RST))
1531             return 0;
1532     }
1533 
1534     return -ETIMEDOUT;
1535 }
1536 
1537 static const struct of_device_id mma8452_dt_ids[] = {
1538     { .compatible = "fsl,mma8451", .data = &mma_chip_info_table[mma8451] },
1539     { .compatible = "fsl,mma8452", .data = &mma_chip_info_table[mma8452] },
1540     { .compatible = "fsl,mma8453", .data = &mma_chip_info_table[mma8453] },
1541     { .compatible = "fsl,mma8652", .data = &mma_chip_info_table[mma8652] },
1542     { .compatible = "fsl,mma8653", .data = &mma_chip_info_table[mma8653] },
1543     { .compatible = "fsl,fxls8471", .data = &mma_chip_info_table[fxls8471] },
1544     { }
1545 };
1546 MODULE_DEVICE_TABLE(of, mma8452_dt_ids);
1547 
1548 static int mma8452_probe(struct i2c_client *client,
1549              const struct i2c_device_id *id)
1550 {
1551     struct mma8452_data *data;
1552     struct iio_dev *indio_dev;
1553     int ret;
1554 
1555     indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
1556     if (!indio_dev)
1557         return -ENOMEM;
1558 
1559     data = iio_priv(indio_dev);
1560     data->client = client;
1561     mutex_init(&data->lock);
1562 
1563     data->chip_info = device_get_match_data(&client->dev);
1564     if (!data->chip_info) {
1565         if (id) {
1566             data->chip_info = &mma_chip_info_table[id->driver_data];
1567         } else {
1568             dev_err(&client->dev, "unknown device model\n");
1569             return -ENODEV;
1570         }
1571     }
1572 
1573     ret = iio_read_mount_matrix(&client->dev, &data->orientation);
1574     if (ret)
1575         return ret;
1576 
1577     data->vdd_reg = devm_regulator_get(&client->dev, "vdd");
1578     if (IS_ERR(data->vdd_reg))
1579         return dev_err_probe(&client->dev, PTR_ERR(data->vdd_reg),
1580                      "failed to get VDD regulator!\n");
1581 
1582     data->vddio_reg = devm_regulator_get(&client->dev, "vddio");
1583     if (IS_ERR(data->vddio_reg))
1584         return dev_err_probe(&client->dev, PTR_ERR(data->vddio_reg),
1585                      "failed to get VDDIO regulator!\n");
1586 
1587     ret = regulator_enable(data->vdd_reg);
1588     if (ret) {
1589         dev_err(&client->dev, "failed to enable VDD regulator!\n");
1590         return ret;
1591     }
1592 
1593     ret = regulator_enable(data->vddio_reg);
1594     if (ret) {
1595         dev_err(&client->dev, "failed to enable VDDIO regulator!\n");
1596         goto disable_regulator_vdd;
1597     }
1598 
1599     ret = i2c_smbus_read_byte_data(client, MMA8452_WHO_AM_I);
1600     if (ret < 0)
1601         goto disable_regulators;
1602 
1603     switch (ret) {
1604     case MMA8451_DEVICE_ID:
1605     case MMA8452_DEVICE_ID:
1606     case MMA8453_DEVICE_ID:
1607     case MMA8652_DEVICE_ID:
1608     case MMA8653_DEVICE_ID:
1609     case FXLS8471_DEVICE_ID:
1610         if (ret == data->chip_info->chip_id)
1611             break;
1612         fallthrough;
1613     default:
1614         ret = -ENODEV;
1615         goto disable_regulators;
1616     }
1617 
1618     dev_info(&client->dev, "registering %s accelerometer; ID 0x%x\n",
1619          data->chip_info->name, data->chip_info->chip_id);
1620 
1621     i2c_set_clientdata(client, indio_dev);
1622     indio_dev->info = &mma8452_info;
1623     indio_dev->name = data->chip_info->name;
1624     indio_dev->modes = INDIO_DIRECT_MODE;
1625     indio_dev->channels = data->chip_info->channels;
1626     indio_dev->num_channels = data->chip_info->num_channels;
1627     indio_dev->available_scan_masks = mma8452_scan_masks;
1628 
1629     ret = mma8452_reset(client);
1630     if (ret < 0)
1631         goto disable_regulators;
1632 
1633     data->data_cfg = MMA8452_DATA_CFG_FS_2G;
1634     ret = i2c_smbus_write_byte_data(client, MMA8452_DATA_CFG,
1635                     data->data_cfg);
1636     if (ret < 0)
1637         goto disable_regulators;
1638 
1639     /*
1640      * By default set transient threshold to max to avoid events if
1641      * enabling without configuring threshold.
1642      */
1643     ret = i2c_smbus_write_byte_data(client, MMA8452_TRANSIENT_THS,
1644                     MMA8452_TRANSIENT_THS_MASK);
1645     if (ret < 0)
1646         goto disable_regulators;
1647 
1648     if (client->irq) {
1649         int irq2;
1650 
1651         irq2 = of_irq_get_byname(client->dev.of_node, "INT2");
1652 
1653         if (irq2 == client->irq) {
1654             dev_dbg(&client->dev, "using interrupt line INT2\n");
1655         } else {
1656             ret = i2c_smbus_write_byte_data(client,
1657                         MMA8452_CTRL_REG5,
1658                         data->chip_info->all_events);
1659             if (ret < 0)
1660                 goto disable_regulators;
1661 
1662             dev_dbg(&client->dev, "using interrupt line INT1\n");
1663         }
1664 
1665         ret = i2c_smbus_write_byte_data(client,
1666                     MMA8452_CTRL_REG4,
1667                     data->chip_info->enabled_events);
1668         if (ret < 0)
1669             goto disable_regulators;
1670 
1671         ret = mma8452_trigger_setup(indio_dev);
1672         if (ret < 0)
1673             goto disable_regulators;
1674     }
1675 
1676     data->ctrl_reg1 = MMA8452_CTRL_ACTIVE |
1677               (MMA8452_CTRL_DR_DEFAULT << MMA8452_CTRL_DR_SHIFT);
1678 
1679     data->sleep_val = mma8452_calculate_sleep(data);
1680 
1681     ret = i2c_smbus_write_byte_data(client, MMA8452_CTRL_REG1,
1682                     data->ctrl_reg1);
1683     if (ret < 0)
1684         goto trigger_cleanup;
1685 
1686     ret = iio_triggered_buffer_setup(indio_dev, NULL,
1687                      mma8452_trigger_handler, NULL);
1688     if (ret < 0)
1689         goto trigger_cleanup;
1690 
1691     if (client->irq) {
1692         ret = devm_request_threaded_irq(&client->dev,
1693                         client->irq,
1694                         NULL, mma8452_interrupt,
1695                         IRQF_TRIGGER_LOW | IRQF_ONESHOT,
1696                         client->name, indio_dev);
1697         if (ret)
1698             goto buffer_cleanup;
1699     }
1700 
1701     ret = pm_runtime_set_active(&client->dev);
1702     if (ret < 0)
1703         goto buffer_cleanup;
1704 
1705     pm_runtime_enable(&client->dev);
1706     pm_runtime_set_autosuspend_delay(&client->dev,
1707                      MMA8452_AUTO_SUSPEND_DELAY_MS);
1708     pm_runtime_use_autosuspend(&client->dev);
1709 
1710     ret = iio_device_register(indio_dev);
1711     if (ret < 0)
1712         goto buffer_cleanup;
1713 
1714     ret = mma8452_set_freefall_mode(data, false);
1715     if (ret < 0)
1716         goto unregister_device;
1717 
1718     return 0;
1719 
1720 unregister_device:
1721     iio_device_unregister(indio_dev);
1722 
1723 buffer_cleanup:
1724     iio_triggered_buffer_cleanup(indio_dev);
1725 
1726 trigger_cleanup:
1727     mma8452_trigger_cleanup(indio_dev);
1728 
1729 disable_regulators:
1730     regulator_disable(data->vddio_reg);
1731 
1732 disable_regulator_vdd:
1733     regulator_disable(data->vdd_reg);
1734 
1735     return ret;
1736 }
1737 
1738 static int mma8452_remove(struct i2c_client *client)
1739 {
1740     struct iio_dev *indio_dev = i2c_get_clientdata(client);
1741     struct mma8452_data *data = iio_priv(indio_dev);
1742 
1743     iio_device_unregister(indio_dev);
1744 
1745     pm_runtime_disable(&client->dev);
1746     pm_runtime_set_suspended(&client->dev);
1747 
1748     iio_triggered_buffer_cleanup(indio_dev);
1749     mma8452_trigger_cleanup(indio_dev);
1750     mma8452_standby(iio_priv(indio_dev));
1751 
1752     regulator_disable(data->vddio_reg);
1753     regulator_disable(data->vdd_reg);
1754 
1755     return 0;
1756 }
1757 
1758 #ifdef CONFIG_PM
1759 static int mma8452_runtime_suspend(struct device *dev)
1760 {
1761     struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
1762     struct mma8452_data *data = iio_priv(indio_dev);
1763     int ret;
1764 
1765     mutex_lock(&data->lock);
1766     ret = mma8452_standby(data);
1767     mutex_unlock(&data->lock);
1768     if (ret < 0) {
1769         dev_err(&data->client->dev, "powering off device failed\n");
1770         return -EAGAIN;
1771     }
1772 
1773     ret = regulator_disable(data->vddio_reg);
1774     if (ret) {
1775         dev_err(dev, "failed to disable VDDIO regulator\n");
1776         return ret;
1777     }
1778 
1779     ret = regulator_disable(data->vdd_reg);
1780     if (ret) {
1781         dev_err(dev, "failed to disable VDD regulator\n");
1782         return ret;
1783     }
1784 
1785     return 0;
1786 }
1787 
1788 static int mma8452_runtime_resume(struct device *dev)
1789 {
1790     struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
1791     struct mma8452_data *data = iio_priv(indio_dev);
1792     int ret, sleep_val;
1793 
1794     ret = regulator_enable(data->vdd_reg);
1795     if (ret) {
1796         dev_err(dev, "failed to enable VDD regulator\n");
1797         return ret;
1798     }
1799 
1800     ret = regulator_enable(data->vddio_reg);
1801     if (ret) {
1802         dev_err(dev, "failed to enable VDDIO regulator\n");
1803         regulator_disable(data->vdd_reg);
1804         return ret;
1805     }
1806 
1807     ret = mma8452_active(data);
1808     if (ret < 0)
1809         goto runtime_resume_failed;
1810 
1811     ret = mma8452_get_odr_index(data);
1812     sleep_val = 1000 / mma8452_samp_freq[ret][0];
1813     if (sleep_val < 20)
1814         usleep_range(sleep_val * 1000, 20000);
1815     else
1816         msleep_interruptible(sleep_val);
1817 
1818     return 0;
1819 
1820 runtime_resume_failed:
1821     regulator_disable(data->vddio_reg);
1822     regulator_disable(data->vdd_reg);
1823 
1824     return ret;
1825 }
1826 #endif
1827 
1828 static const struct dev_pm_ops mma8452_pm_ops = {
1829     SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, pm_runtime_force_resume)
1830     SET_RUNTIME_PM_OPS(mma8452_runtime_suspend,
1831                mma8452_runtime_resume, NULL)
1832 };
1833 
1834 static const struct i2c_device_id mma8452_id[] = {
1835     { "mma8451", mma8451 },
1836     { "mma8452", mma8452 },
1837     { "mma8453", mma8453 },
1838     { "mma8652", mma8652 },
1839     { "mma8653", mma8653 },
1840     { "fxls8471", fxls8471 },
1841     { }
1842 };
1843 MODULE_DEVICE_TABLE(i2c, mma8452_id);
1844 
1845 static struct i2c_driver mma8452_driver = {
1846     .driver = {
1847         .name   = "mma8452",
1848         .of_match_table = mma8452_dt_ids,
1849         .pm = &mma8452_pm_ops,
1850     },
1851     .probe = mma8452_probe,
1852     .remove = mma8452_remove,
1853     .id_table = mma8452_id,
1854 };
1855 module_i2c_driver(mma8452_driver);
1856 
1857 MODULE_AUTHOR("Peter Meerwald <pmeerw@pmeerw.net>");
1858 MODULE_DESCRIPTION("Freescale / NXP MMA8452 accelerometer driver");
1859 MODULE_LICENSE("GPL");
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